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Commit 35d2bec0 by Siddhesh Poyarekar Committed by Richard Earnshaw
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[ARM/AArch64] Add Falkor CPU support. 

	2016-11-10  Siddhesh Poyarekar  <siddhesh.poyarekar@linaro.org>

	* config/aarch64/aarch64-cores.def (qdf24xx): Update part
	number.
	(falkor): New core.
	* config/aarch64/aarch64-tune.md: Regenerated.
	* config/arm/arm-cores.def (falkor): New core.
	* config/arm/arm-tables.opt: Regenerated.
	* config/arm/arm-tune.md: Regenerated.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Add falkor support.
	* config/arm/t-aprofile (MULTILIB_MATCHES): Likewise.
	* doc/invoke.texi (AArch64 Options/-mtune): Document it.
	(ARM Options/-mtune): Likewise.

From-SVN: r242033
parent e32d2c92
Showing with 32 additions and 9 deletions
gcc/ChangeLog
2016-11-10 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org>
* config/aarch64/aarch64-cores.def (qdf24xx): Update part
number.
(falkor): New core.
* config/aarch64/aarch64-tune.md: Regenerated.
* config/arm/arm-cores.def (falkor): New core.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add falkor support.
* config/arm/t-aprofile (MULTILIB_MATCHES): Likewise.
* doc/invoke.texi (AArch64 Options/-mtune): Document it.
(ARM Options/-mtune): Likewise.
2016-11-10 Kugan Vivekanandarajah <kuganv@linaro.org> 2016-11-10 Kugan Vivekanandarajah <kuganv@linaro.org>
Revert Revert
gcc/config/aarch64/aarch64-cores.def
...@@ -54,7 +54,8 @@ AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AA ...@@ -54,7 +54,8 @@ AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AA
AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001) AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001)
/* Qualcomm ('Q') cores. */ /* Qualcomm ('Q') cores. */
AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0x800) AARCH64_CORE("falkor", falkor, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00)
AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00)
/* Cavium ('C') cores. */ /* Cavium ('C') cores. */
AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a1) AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a1)
......
gcc/config/aarch64/aarch64-tune.md
;; -*- buffer-read-only: t -*- ;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def ;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune" (define_attr "tune"
"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53" "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,falkor,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
(const (symbol_ref "((enum attr_tune) aarch64_tune)"))) (const (symbol_ref "((enum attr_tune) aarch64_tune)")))
gcc/config/arm/arm-cores.def
...@@ -175,6 +175,7 @@ ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED ...@@ -175,6 +175,7 @@ ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED
ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1) ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
ARM_CORE("falkor", falkor, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1) ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1)
......
gcc/config/arm/arm-tables.opt
...@@ -334,6 +334,9 @@ EnumValue ...@@ -334,6 +334,9 @@ EnumValue
Enum(processor_type) String(exynos-m1) Value(exynosm1) Enum(processor_type) String(exynos-m1) Value(exynosm1)
EnumValue EnumValue
Enum(processor_type) String(falkor) Value(falkor)
EnumValue
Enum(processor_type) String(qdf24xx) Value(qdf24xx) Enum(processor_type) String(qdf24xx) Value(qdf24xx)
EnumValue EnumValue
......
gcc/config/arm/arm-tune.md
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
cortexa17cortexa7,cortexm23,cortexa32, cortexa17cortexa7,cortexm23,cortexa32,
cortexm33,cortexa35,cortexa53, cortexm33,cortexa35,cortexa53,
cortexa57,cortexa72,cortexa73, cortexa57,cortexa72,cortexa73,
exynosm1,qdf24xx,xgene1, exynosm1,falkor,qdf24xx,
cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, xgene1,cortexa57cortexa53,cortexa72cortexa53,
cortexa73cortexa53" cortexa73cortexa35,cortexa73cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)"))) (const (symbol_ref "((enum attr_tune) arm_tune)")))
gcc/config/arm/bpabi.h
...@@ -79,6 +79,7 @@ ...@@ -79,6 +79,7 @@
|mcpu=cortex-a73.cortex-a35 \ |mcpu=cortex-a73.cortex-a35 \
|mcpu=cortex-a73.cortex-a53 \ |mcpu=cortex-a73.cortex-a53 \
|mcpu=exynos-m1 \ |mcpu=exynos-m1 \
|mcpu=falkor \
|mcpu=qdf24xx \ |mcpu=qdf24xx \
|mcpu=xgene1 \ |mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \ |mcpu=cortex-m1.small-multiply \
...@@ -117,6 +118,7 @@ ...@@ -117,6 +118,7 @@
|mcpu=cortex-a73.cortex-a35 \ |mcpu=cortex-a73.cortex-a35 \
|mcpu=cortex-a73.cortex-a53 \ |mcpu=cortex-a73.cortex-a53 \
|mcpu=exynos-m1 \ |mcpu=exynos-m1 \
|mcpu=falkor \
|mcpu=qdf24xx \ |mcpu=qdf24xx \
|mcpu=xgene1 \ |mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \ |mcpu=cortex-m1.small-multiply \
......
gcc/config/arm/t-aprofile
...@@ -92,6 +92,7 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73 ...@@ -92,6 +92,7 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53
MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1 MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1
MULTILIB_MATCHES += march?armv8-a=mcpu?falkor
MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx
MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1 MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1
......
gcc/doc/invoke.texi
...@@ -13878,10 +13878,10 @@ processors implementing the target architecture. ...@@ -13878,10 +13878,10 @@ processors implementing the target architecture.
Specify the name of the target processor for which GCC should tune the Specify the name of the target processor for which GCC should tune the
performance of the code. Permissible values for this option are: performance of the code. Permissible values for this option are:
@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{falkor},
@samp{thunderx}, @samp{xgene1}, @samp{vulcan}, @samp{cortex-a57.cortex-a53}, @samp{qdf24xx}, @samp{thunderx}, @samp{xgene1}, @samp{vulcan},
@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
@samp{cortex-a73.cortex-a53}, @samp{native}. @samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}, @samp{native}.
The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53} @samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}
...@@ -14970,6 +14970,7 @@ Permissible names are: @samp{arm2}, @samp{arm250}, ...@@ -14970,6 +14970,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m0.small-multiply}, @samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply}, @samp{cortex-m0plus.small-multiply},
@samp{exynos-m1}, @samp{exynos-m1},
@samp{falkor},
@samp{qdf24xx}, @samp{qdf24xx},
@samp{marvell-pj4}, @samp{marvell-pj4},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
......
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