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Commit 33d72b63 by Jiong Wang Committed by Jiong Wang
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[AArch64][3/10] ARMv8.2-A FP16 two operands vector intrinsics 

gcc/
	* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
	* config/aarch64/aarch64-simd.md
	(aarch64_rsqrts<mode>): Extend to HF modes.
	(fabd<mode>3): Likewise.
	(<FCVT_F2FIXED:fcvt_fixed_insn><VHSDF_SDF:mode>3): Likewise.
	(<FCVT_FIXED2F:fcvt_fixed_insn><VHSDI_SDI:mode>3): Likewise.
	(aarch64_<maxmin_uns>p<mode>): Likewise.
	(<su><maxmin><mode>3): Likewise.
	(<maxmin_uns><mode>3): Likewise.
	(<fmaxmin><mode>3): Likewise.
	(aarch64_faddp<mode>): Likewise.
	(aarch64_fmulx<mode>): Likewise.
	(aarch64_frecps<mode>): Likewise.
	(*aarch64_fac<optab><mode>): Rename to aarch64_fac<optab><mode>.
	(add<mode>3): Extend to HF modes.
	(sub<mode>3): Likewise.
	(mul<mode>3): Likewise.
	(div<mode>3): Likewise.
	(*div<mode>3): Likewise.
	* config/aarch64/aarch64.c (aarch64_emit_approx_div): Return false for
	HF, V4HF and V8HF.
	* config/aarch64/iterators.md (VDQ_HSDI, VSDQ_HSDI): New mode iterator.
	* config/aarch64/arm_neon.h (vadd_f16): New.
	(vaddq_f16, vabd_f16, vabdq_f16, vcage_f16, vcageq_f16, vcagt_f16,
	vcagtq_f16, vcale_f16, vcaleq_f16, vcalt_f16, vcaltq_f16, vceq_f16,
	vceqq_f16, vcge_f16, vcgeq_f16, vcgt_f16, vcgtq_f16, vcle_f16,
	vcleq_f16, vclt_f16, vcltq_f16, vcvt_n_f16_s16, vcvtq_n_f16_s16,
	vcvt_n_f16_u16, vcvtq_n_f16_u16, vcvt_n_s16_f16, vcvtq_n_s16_f16,
	vcvt_n_u16_f16, vcvtq_n_u16_f16, vdiv_f16, vdivq_f16, vdup_lane_f16,
	vdup_laneq_f16, vdupq_lane_f16, vdupq_laneq_f16, vdups_lane_f16,
	vdups_laneq_f16, vmax_f16, vmaxq_f16, vmaxnm_f16, vmaxnmq_f16, vmin_f16,
	vminq_f16, vminnm_f16, vminnmq_f16, vmul_f16, vmulq_f16, vmulx_f16,
	vmulxq_f16, vpadd_f16, vpaddq_f16, vpmax_f16, vpmaxq_f16, vpmaxnm_f16,
	vpmaxnmq_f16, vpmin_f16, vpminq_f16, vpminnm_f16, vpminnmq_f16,
	vrecps_f16, vrecpsq_f16, vrsqrts_f16, vrsqrtsq_f16, vsub_f16,
	vsubq_f16): Likewise.

From-SVN: r238717
parent daef0a8c
Showing with 78 additions and 19 deletions
gcc/ChangeLog
2016-07-25 Jiong Wang <jiong.wang@arm.com> 2016-07-25 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
* config/aarch64/aarch64-simd.md
(aarch64_rsqrts<mode>): Extend to HF modes.
(fabd<mode>3): Likewise.
(<FCVT_F2FIXED:fcvt_fixed_insn><VHSDF_SDF:mode>3): Likewise.
(<FCVT_FIXED2F:fcvt_fixed_insn><VHSDI_SDI:mode>3): Likewise.
(aarch64_<maxmin_uns>p<mode>): Likewise.
(<su><maxmin><mode>3): Likewise.
(<maxmin_uns><mode>3): Likewise.
(<fmaxmin><mode>3): Likewise.
(aarch64_faddp<mode>): Likewise.
(aarch64_fmulx<mode>): Likewise.
(aarch64_frecps<mode>): Likewise.
(*aarch64_fac<optab><mode>): Rename to aarch64_fac<optab><mode>.
(add<mode>3): Extend to HF modes.
(sub<mode>3): Likewise.
(mul<mode>3): Likewise.
(div<mode>3): Likewise.
(*div<mode>3): Likewise.
* config/aarch64/aarch64.c (aarch64_emit_approx_div): Return false for
HF, V4HF and V8HF.
* config/aarch64/iterators.md (VDQ_HSDI, VSDQ_HSDI): New mode iterator.
* config/aarch64/arm_neon.h (vadd_f16): New.
(vaddq_f16, vabd_f16, vabdq_f16, vcage_f16, vcageq_f16, vcagt_f16,
vcagtq_f16, vcale_f16, vcaleq_f16, vcalt_f16, vcaltq_f16, vceq_f16,
vceqq_f16, vcge_f16, vcgeq_f16, vcgt_f16, vcgtq_f16, vcle_f16,
vcleq_f16, vclt_f16, vcltq_f16, vcvt_n_f16_s16, vcvtq_n_f16_s16,
vcvt_n_f16_u16, vcvtq_n_f16_u16, vcvt_n_s16_f16, vcvtq_n_s16_f16,
vcvt_n_u16_f16, vcvtq_n_u16_f16, vdiv_f16, vdivq_f16, vdup_lane_f16,
vdup_laneq_f16, vdupq_lane_f16, vdupq_laneq_f16, vdups_lane_f16,
vdups_laneq_f16, vmax_f16, vmaxq_f16, vmaxnm_f16, vmaxnmq_f16, vmin_f16,
vminq_f16, vminnm_f16, vminnmq_f16, vmul_f16, vmulq_f16, vmulx_f16,
vmulxq_f16, vpadd_f16, vpaddq_f16, vpmax_f16, vpmaxq_f16, vpmaxnm_f16,
vpmaxnmq_f16, vpmin_f16, vpminq_f16, vpminnm_f16, vpminnmq_f16,
vrecps_f16, vrecpsq_f16, vrsqrts_f16, vrsqrtsq_f16, vsub_f16,
vsubq_f16): Likewise.
2016-07-25 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_BINOP_USS): New. * config/aarch64/aarch64-builtins.c (TYPES_BINOP_USS): New.
* config/aarch64/aarch64-simd-builtins.def: Register new builtins. * config/aarch64/aarch64-simd-builtins.def: Register new builtins.
* config/aarch64/aarch64-simd.md (aarch64_rsqrte<mode>): Extend to HF modes. * config/aarch64/aarch64-simd.md (aarch64_rsqrte<mode>): Extend to HF modes.
...@@ -15,8 +54,8 @@ ...@@ -15,8 +54,8 @@
(*sqrt<mode>2): Likewise. (*sqrt<mode>2): Likewise.
(aarch64_frecpe<mode>): Likewise. (aarch64_frecpe<mode>): Likewise.
(aarch64_cm<optab><mode>): Likewise. (aarch64_cm<optab><mode>): Likewise.
* config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Return * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Return false for
false for V4HF and V8HF. HF, V4HF and V8HF.
* config/aarch64/iterators.md (VHSDF, VHSDF_DF, VHSDF_SDF): New. * config/aarch64/iterators.md (VHSDF, VHSDF_DF, VHSDF_SDF): New.
(VDQF_COND, fcvt_target, FCVT_TARGET, hcon): Extend mode attribute to HF modes. (VDQF_COND, fcvt_target, FCVT_TARGET, hcon): Extend mode attribute to HF modes.
(stype): New. (stype): New.
......
gcc/config/aarch64/aarch64-simd-builtins.def
...@@ -41,7 +41,7 @@ ...@@ -41,7 +41,7 @@
BUILTIN_VDC (COMBINE, combine, 0) BUILTIN_VDC (COMBINE, combine, 0)
BUILTIN_VB (BINOP, pmul, 0) BUILTIN_VB (BINOP, pmul, 0)
BUILTIN_VALLF (BINOP, fmulx, 0) BUILTIN_VHSDF_SDF (BINOP, fmulx, 0)
BUILTIN_VHSDF_DF (UNOP, sqrt, 2) BUILTIN_VHSDF_DF (UNOP, sqrt, 2)
BUILTIN_VD_BHSI (BINOP, addp, 0) BUILTIN_VD_BHSI (BINOP, addp, 0)
VAR1 (UNOP, addp, 0, di) VAR1 (UNOP, addp, 0, di)
...@@ -248,22 +248,22 @@ ...@@ -248,22 +248,22 @@
BUILTIN_VDQ_BHSI (BINOP, smin, 3) BUILTIN_VDQ_BHSI (BINOP, smin, 3)
BUILTIN_VDQ_BHSI (BINOP, umax, 3) BUILTIN_VDQ_BHSI (BINOP, umax, 3)
BUILTIN_VDQ_BHSI (BINOP, umin, 3) BUILTIN_VDQ_BHSI (BINOP, umin, 3)
BUILTIN_VDQF (BINOP, smax_nan, 3) BUILTIN_VHSDF (BINOP, smax_nan, 3)
BUILTIN_VDQF (BINOP, smin_nan, 3) BUILTIN_VHSDF (BINOP, smin_nan, 3)
/* Implemented by <fmaxmin><mode>3. */ /* Implemented by <fmaxmin><mode>3. */
BUILTIN_VDQF (BINOP, fmax, 3) BUILTIN_VHSDF (BINOP, fmax, 3)
BUILTIN_VDQF (BINOP, fmin, 3) BUILTIN_VHSDF (BINOP, fmin, 3)
/* Implemented by aarch64_<maxmin_uns>p<mode>. */ /* Implemented by aarch64_<maxmin_uns>p<mode>. */
BUILTIN_VDQ_BHSI (BINOP, smaxp, 0) BUILTIN_VDQ_BHSI (BINOP, smaxp, 0)
BUILTIN_VDQ_BHSI (BINOP, sminp, 0) BUILTIN_VDQ_BHSI (BINOP, sminp, 0)
BUILTIN_VDQ_BHSI (BINOP, umaxp, 0) BUILTIN_VDQ_BHSI (BINOP, umaxp, 0)
BUILTIN_VDQ_BHSI (BINOP, uminp, 0) BUILTIN_VDQ_BHSI (BINOP, uminp, 0)
BUILTIN_VDQF (BINOP, smaxp, 0) BUILTIN_VHSDF (BINOP, smaxp, 0)
BUILTIN_VDQF (BINOP, sminp, 0) BUILTIN_VHSDF (BINOP, sminp, 0)
BUILTIN_VDQF (BINOP, smax_nanp, 0) BUILTIN_VHSDF (BINOP, smax_nanp, 0)
BUILTIN_VDQF (BINOP, smin_nanp, 0) BUILTIN_VHSDF (BINOP, smin_nanp, 0)
/* Implemented by <frint_pattern><mode>2. */ /* Implemented by <frint_pattern><mode>2. */
BUILTIN_VHSDF (UNOP, btrunc, 2) BUILTIN_VHSDF (UNOP, btrunc, 2)
...@@ -383,7 +383,7 @@ ...@@ -383,7 +383,7 @@
BUILTIN_VDQ_SI (UNOP, urecpe, 0) BUILTIN_VDQ_SI (UNOP, urecpe, 0)
BUILTIN_VHSDF (UNOP, frecpe, 0) BUILTIN_VHSDF (UNOP, frecpe, 0)
BUILTIN_VDQF (BINOP, frecps, 0) BUILTIN_VHSDF (BINOP, frecps, 0)
/* Implemented by a mixture of abs2 patterns. Note the DImode builtin is /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is
only ever used for the int64x1_t intrinsic, there is no scalar version. */ only ever used for the int64x1_t intrinsic, there is no scalar version. */
...@@ -475,22 +475,22 @@ ...@@ -475,22 +475,22 @@
BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0) BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
/* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */ /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */
BUILTIN_VSDQ_SDI (SHIFTIMM, scvtf, 3) BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3)
BUILTIN_VSDQ_SDI (FCVTIMM_SUS, ucvtf, 3) BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3)
BUILTIN_VALLF (SHIFTIMM, fcvtzs, 3) BUILTIN_VHSDF_SDF (SHIFTIMM, fcvtzs, 3)
BUILTIN_VALLF (SHIFTIMM_USS, fcvtzu, 3) BUILTIN_VHSDF_SDF (SHIFTIMM_USS, fcvtzu, 3)
/* Implemented by aarch64_rsqrte<mode>. */ /* Implemented by aarch64_rsqrte<mode>. */
BUILTIN_VHSDF_SDF (UNOP, rsqrte, 0) BUILTIN_VHSDF_SDF (UNOP, rsqrte, 0)
/* Implemented by aarch64_rsqrts<mode>. */ /* Implemented by aarch64_rsqrts<mode>. */
BUILTIN_VALLF (BINOP, rsqrts, 0) BUILTIN_VHSDF_SDF (BINOP, rsqrts, 0)
/* Implemented by fabd<mode>3. */ /* Implemented by fabd<mode>3. */
BUILTIN_VALLF (BINOP, fabd, 3) BUILTIN_VHSDF_SDF (BINOP, fabd, 3)
/* Implemented by aarch64_faddp<mode>. */ /* Implemented by aarch64_faddp<mode>. */
BUILTIN_VDQF (BINOP, faddp, 0) BUILTIN_VHSDF (BINOP, faddp, 0)
/* Implemented by aarch64_cm<optab><mode>. */ /* Implemented by aarch64_cm<optab><mode>. */
BUILTIN_VHSDF_SDF (BINOP_USS, cmeq, 0) BUILTIN_VHSDF_SDF (BINOP_USS, cmeq, 0)
...@@ -501,3 +501,9 @@ ...@@ -501,3 +501,9 @@
/* Implemented by neg<mode>2. */ /* Implemented by neg<mode>2. */
BUILTIN_VHSDF (UNOP, neg, 2) BUILTIN_VHSDF (UNOP, neg, 2)
/* Implemented by aarch64_fac<optab><mode>. */
BUILTIN_VHSDF_SDF (BINOP_USS, faclt, 0)
BUILTIN_VHSDF_SDF (BINOP_USS, facle, 0)
BUILTIN_VHSDF_SDF (BINOP_USS, facgt, 0)
BUILTIN_VHSDF_SDF (BINOP_USS, facge, 0)
gcc/config/aarch64/aarch64.c
...@@ -7604,6 +7604,10 @@ bool ...@@ -7604,6 +7604,10 @@ bool
aarch64_emit_approx_div (rtx quo, rtx num, rtx den) aarch64_emit_approx_div (rtx quo, rtx num, rtx den)
{ {
machine_mode mode = GET_MODE (quo); machine_mode mode = GET_MODE (quo);
if (GET_MODE_INNER (mode) == HFmode)
return false;
bool use_approx_division_p = (flag_mlow_precision_div bool use_approx_division_p = (flag_mlow_precision_div
|| (aarch64_tune_params.approx_modes->division || (aarch64_tune_params.approx_modes->division
& AARCH64_APPROX_MODE (mode))); & AARCH64_APPROX_MODE (mode)));
......
gcc/config/aarch64/iterators.md
...@@ -166,9 +166,19 @@ ...@@ -166,9 +166,19 @@
;; Vector modes for S and D ;; Vector modes for S and D
(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI]) (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
;; Vector modes for H, S and D
(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
(V8HI "TARGET_SIMD_F16INST")
V2SI V4SI V2DI])
;; Scalar and Vector modes for S and D ;; Scalar and Vector modes for S and D
(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI]) (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
;; Scalar and Vector modes for S and D, Vector modes for H.
(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
(V8HI "TARGET_SIMD_F16INST")
V2SI V4SI V2DI SI DI])
;; Vector modes for Q and H types. ;; Vector modes for Q and H types.
(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
......
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