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riscv-gcc-1
Commit 3298c037 by Andreas Krebbel Committed by Andreas Krebbel
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s390.md ("Y", "y"): New mode attribute. 

2006-01-19  Andreas Krebbel  <krebbel1@de.ibm.com>

	* config/s390/s390.md ("Y", "y"): New mode attribute.
	("*cmpdi_ccs", "*cmpsi_ccs", "*adddi3_imm_cc", "*adddi3_carry1_cc", 
	"*adddi3_carry1_cconly", "*adddi3_carry2_cc", "*adddi3_carry2_cconly",
	"*adddi3_cc", "*adddi3_cconly", "*adddi3_cconly2", "*adddi3_64", 
	"*addsi3_imm_cc", "*addsi3_carry1_cc", 
	"*addsi3_carry1_cconly", "*addsi3_carry2_cc", "*addsi3_carr2_cconly",
	"*addsi3_cc", "*addsi3_cconly", "*addsi3_cconly2",
	"*subdi3_borrow_cc", "*subdi3_borrow_cconly", "*subdi3_cc", 
	"*subdi3_cc2", "*subdi3_cconly", "*subdi3_cconly2", "*subdi3_64",
	"*subsi3_borrow_cc", "*subsi3_borrow_cconly", "*subsi3_cc",
	"*subsi3_cc2", "*subsi3_cconly", "*subsi3_cconly", "*subsi3_cconly2",
	"addsi3", "subsi3"): Insn patterns removed.
	("*add<mode>3_carry1_cc", "*add<mode>3_carry1_cconly",
	"*add<mode>3_carry2_cc", "*add<mode>3_carry2_cconly", "*add<mode>3_cc",
	"*add<mode>3_cconly", "*add<mode>3_cconly2", "*add<mode>3_imm_cc",
	"*sub<mode>3_borrow_cc", "*sub<mode>3_borrow_cconly",
	"*sub<mode>3_cc", "*sub<mode>3_cc2", "*sub<mode>3_cconly", 
	"*sub<mode>3_cconly2"): New insn patterns.
	("addsi3", "subsi3"): New expanders.

From-SVN: r109957
parent 20f06221
Showing with 255 additions and 417 deletions
gcc/ChangeLog
2006-01-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("Y", "y"): New mode attribute.
("*cmpdi_ccs", "*cmpsi_ccs", "*adddi3_imm_cc", "*adddi3_carry1_cc",
"*adddi3_carry1_cconly", "*adddi3_carry2_cc", "*adddi3_carry2_cconly",
"*adddi3_cc", "*adddi3_cconly", "*adddi3_cconly2", "*adddi3_64",
"*addsi3_imm_cc", "*addsi3_carry1_cc",
"*addsi3_carry1_cconly", "*addsi3_carry2_cc", "*addsi3_carr2_cconly",
"*addsi3_cc", "*addsi3_cconly", "*addsi3_cconly2",
"*subdi3_borrow_cc", "*subdi3_borrow_cconly", "*subdi3_cc",
"*subdi3_cc2", "*subdi3_cconly", "*subdi3_cconly2", "*subdi3_64",
"*subsi3_borrow_cc", "*subsi3_borrow_cconly", "*subsi3_cc",
"*subsi3_cc2", "*subsi3_cconly", "*subsi3_cconly", "*subsi3_cconly2",
"addsi3", "subsi3"): Insn patterns removed.
("*add<mode>3_carry1_cc", "*add<mode>3_carry1_cconly",
"*add<mode>3_carry2_cc", "*add<mode>3_carry2_cconly", "*add<mode>3_cc",
"*add<mode>3_cconly", "*add<mode>3_cconly2", "*add<mode>3_imm_cc",
"*sub<mode>3_borrow_cc", "*sub<mode>3_borrow_cconly",
"*sub<mode>3_cc", "*sub<mode>3_cc2", "*sub<mode>3_cconly",
"*sub<mode>3_cconly2"): New insn patterns.
("addsi3", "subsi3"): New expanders.
2006-01-19 Dorit Nuzman <dorit@il.ibm.com>
* Makefile.in (tree-vect-patterns.o): Add rule for new file.
......
gcc/config/s390/s390.md
......@@ -321,6 +321,10 @@
;; in "RRE" for DImode and "RR" for SImode.
(define_mode_attr E [(DI "E") (SI "")])
;; This attribute handles differences in the instruction 'type' and makes RX<Y>
;; to result in "RXY" for DImode and "RX" for SImode.
(define_mode_attr Y [(DI "Y") (SI "")])
;; This attribute handles differences in the instruction 'type' and will result
;; in "RSE" for TImode and "RS" for DImode.
(define_mode_attr TE [(TI "E") (DI "")])
......@@ -329,6 +333,12 @@
;; and "lcr" in SImode.
(define_mode_attr g [(DI "g") (SI "")])
;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
;; were enhanced with long displacements whereas 31bit instructions got a ..y
;; variant for long displacements.
(define_mode_attr y [(DI "g") (SI "y")])
;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
;; and "cds" in DImode.
(define_mode_attr tg [(TI "g") (DI "")])
......@@ -626,18 +636,6 @@
cgf\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccs"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d,d,d,d")
(match_operand:DI 1 "general_operand" "d,K,Os,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"@
cgr\t%0,%1
cghi\t%0,%h1
cgfi\t%0,%1
cg\t%0,%1"
[(set_attr "op_type" "RRE,RI,RIL,RXY")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg CC_REGNUM)
(compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
......@@ -648,18 +646,18 @@
chy\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*cmpsi_ccs"
(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
(match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
(compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
(match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
"s390_match_ccmode(insn, CCSmode)"
"@
cr\t%0,%1
chi\t%0,%h1
cfi\t%0,%1
c\t%0,%1
cy\t%0,%1"
[(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
c<g>r\t%0,%1
c<g>hi\t%0,%h1
c<g>fi\t%0,%1
c<g>\t%0,%1
c<y>\t%0,%1"
[(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
; Compare (unsigned) instructions
......@@ -2746,11 +2744,6 @@
})
;
; extendqihi2 instruction pattern(s).
;
;
; zero_extendsidi2 instruction pattern(s).
;
......@@ -3264,6 +3257,15 @@
; adddi3 instruction pattern(s).
;
(define_expand "adddi3"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "general_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
(define_insn "*adddi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
......@@ -3311,128 +3313,6 @@
algf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc"
[(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "const_int_operand" "K,Os"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT
&& s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
"@
aghi\t%0,%h2
agfi\t%0,%2"
[(set_attr "op_type" "RI,RIL")])
(define_insn "*adddi3_carry1_cc"
[(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,Op,On,m"))
(match_dup 1)))
(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(plus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
"@
algr\t%0,%2
algfi\t%0,%2
slgfi\t%0,%n2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RIL,RIL,RXY")])
(define_insn "*adddi3_carry1_cconly"
[(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
"@
algr\t%0,%2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_carry2_cc"
[(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,Op,On,m"))
(match_dup 2)))
(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(plus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
"@
algr\t%0,%2
algfi\t%0,%2
slgfi\t%0,%n2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RIL,RIL,RXY")])
(define_insn "*adddi3_carry2_cconly"
[(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 2)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
"@
algr\t%0,%2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cc"
[(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,Op,On,m"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(plus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algr\t%0,%2
algfi\t%0,%2
slgfi\t%0,%n2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RIL,RIL,RXY")])
(define_insn "*adddi3_cconly"
[(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algr\t%0,%2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
"@
algr\t%0,%2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
agr\t%0,%2
aghi\t%0,%h2
algfi\t%0,%2
slgfi\t%0,%n2
ag\t%0,%2"
[(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
(define_insn_and_split "*adddi3_31z"
[(set (match_operand:DI 0 "register_operand" "=&d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
......@@ -3489,155 +3369,163 @@
operands[8] = operand_subword (operands[2], 1, 0, DImode);
operands[9] = gen_label_rtx ();")
(define_expand "adddi3"
;
; addsi3 instruction pattern(s).
;
(define_expand "addsi3"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "general_operand" "")))
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
(define_insn "*addsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
(match_operand:SI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
""
"@
ah\t%0,%2
ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
;
; addsi3 instruction pattern(s).
; add(di|si)3 instruction pattern(s).
;
(define_insn "*addsi3_imm_cc"
[(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:SI 2 "const_int_operand" "K,Os"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
&& INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
(define_insn "*add<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
(plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
(match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
(clobber (reg:CC CC_REGNUM))]
""
"@
ahi\t%0,%h2
afi\t%0,%2"
[(set_attr "op_type" "RI,RIL")])
a<g>r\t%0,%2
a<g>hi\t%0,%h2
al<g>fi\t%0,%2
sl<g>fi\t%0,%n2
a<g>\t%0,%2
a<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
(define_insn "*addsi3_carry1_cc"
(define_insn "*add<mode>3_carry1_cc"
[(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,Os,R,T"))
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
(match_dup 1)))
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\t%0,%2
alfi\t%0,%o2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RIL,RX,RXY")])
al<g>r\t%0,%2
al<g>fi\t%0,%2
sl<g>fi\t%0,%n2
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
(define_insn "*addsi3_carry1_cconly"
(define_insn "*add<mode>3_carry1_cconly"
[(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))
(match_dup 1)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
(clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
al<g>r\t%0,%2
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*addsi3_carry2_cc"
(define_insn "*add<mode>3_carry2_cc"
[(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,Os,R,T"))
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
(match_dup 2)))
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\t%0,%2
alfi\t%0,%o2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RIL,RX,RXY")])
al<g>r\t%0,%2
al<g>fi\t%0,%2
sl<g>fi\t%0,%n2
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
(define_insn "*addsi3_carry2_cconly"
(define_insn "*add<mode>3_carry2_cconly"
[(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))
(match_dup 2)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
(clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
al<g>r\t%0,%2
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*addsi3_cc"
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,Os,R,T"))
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\t%0,%2
alfi\t%0,%o2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RIL,RX,RXY")])
al<g>r\t%0,%2
al<g>fi\t%0,%2
sl<g>fi\t%0,%n2
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
(define_insn "*addsi3_cconly"
(define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
(clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
al<g>r\t%0,%2
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*addsi3_cconly2"
(define_insn "*add<mode>3_cconly2"
[(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
(match_operand:SI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
""
(compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
(neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
(clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
ah\t%0,%2
ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
al<g>r\t%0,%2
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
(clobber (reg:CC CC_REGNUM))]
""
(define_insn "*add<mode>3_imm_cc"
[(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
(match_operand:GPR 2 "const_int_operand" "K,Os"))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
&& INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
"@
ar\t%0,%2
ahi\t%0,%h2
afi\t%0,%2
a\t%0,%2
ay\t%0,%2"
[(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
a<g>hi\t%0,%h2
a<g>fi\t%0,%2"
[(set_attr "op_type" "RI,RIL")])
;
; add(df|sf)3 instruction pattern(s).
......@@ -3740,6 +3628,15 @@
; subdi3 instruction pattern(s).
;
(define_expand "subdi3"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "general_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
(define_insn "*subdi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
......@@ -3787,90 +3684,6 @@
slgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_borrow_cc"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
"@
slgr\t%0,%2
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_borrow_cconly"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
"@
slgr\t%0,%2
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgr\t%0,%2
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc2"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
"@
slgr\t%0,%2
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgr\t%0,%2
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly2"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
"@
slgr\t%0,%2
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m") ) )
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
sgr\t%0,%2
sg\t%0,%2"
[(set_attr "op_type" "RRE,RRE")])
(define_insn_and_split "*subdi3_31z"
[(set (match_operand:DI 0 "register_operand" "=&d")
(minus:DI (match_operand:DI 1 "register_operand" "0")
......@@ -3927,121 +3740,124 @@
operands[8] = operand_subword (operands[2], 1, 0, DImode);
operands[9] = gen_label_rtx ();")
(define_expand "subdi3"
;
; subsi3 instruction pattern(s).
;
(define_expand "subsi3"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "general_operand" "")))
[(set (match_operand:SI 0 "register_operand" "")
(minus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
(define_insn "*subsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0")
(sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC CC_REGNUM))]
""
"@
sh\t%0,%2
shy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
;
; subsi3 instruction pattern(s).
; sub(di|si)3 instruction pattern(s).
;
(define_insn "*subsi3_borrow_cc"
(define_insn "*sub<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d,d,d")
(minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T") ) )
(clobber (reg:CC CC_REGNUM))]
""
"@
s<g>r\t%0,%2
s<g>\t%0,%2
s<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*sub<mode>3_borrow_cc"
[(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))
(match_dup 1)))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
(set (match_operand:GPR 0 "register_operand" "=d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL2mode)"
"@
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
sl<g>r\t%0,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*subsi3_borrow_cconly"
(define_insn "*sub<mode>3_borrow_cconly"
[(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))
(match_dup 1)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
(clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL2mode)"
"@
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
sl<g>r\t%0,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*subsi3_cc"
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
(set (match_operand:GPR 0 "register_operand" "=d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
sl<g>r\t%0,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*subsi3_cc2"
(define_insn "*sub<mode>3_cc2"
[(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
(compare (match_operand:GPR 1 "register_operand" "0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")))
(set (match_operand:GPR 0 "register_operand" "=d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL3mode)"
"@
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
sl<g>r\t%0,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*subsi3_cconly"
(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
(clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
sl<g>r\t%0,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
(define_insn "*subsi3_cconly2"
(define_insn "*sub<mode>3_cconly2"
[(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (match_scratch:SI 0 "=d,d,d"))]
(compare (match_operand:GPR 1 "register_operand" "0,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")))
(clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL3mode)"
"@
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0")
(sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC CC_REGNUM))]
""
"@
sh\t%0,%2
shy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC CC_REGNUM))]
""
"@
sr\t%0,%2
s\t%0,%2
sy\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
sl<g>r\t%0,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
;
; sub(df|sf)3 instruction pattern(s).
......
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