Fixed some stack size allocation in G5's mixed mode.

Oked by David Edelsohn.

From-SVN: r79624

gcc/ChangeLog

+2004-03-17  Fariborz Jahanian <fjahanian@apple.com>
+
+        * config/rs6000/rs6000.c (rs6000_stack_info): correct reg_size
+        for mixed mode.
+        (rs6000_emit_prologue): Ditto.
+        (rs6000_emit_epilogue): Ditto.
+        * config/rs6000/rs6000.h: Definition of DWARF_CIE_DATA_ALIGNMENT
+        macro for mixed mode.
+
 2004-03-18  Jan Hubicka  <jh@suse.cz>
 
 	* predict.c (propagate_freq): Compute correctly frequency of

gcc/config/rs6000/rs6000.c

@@ -10671,7 +10671,7 @@ rs6000_stack_info (void)
 {
   static rs6000_stack_t info, zero_info;
   rs6000_stack_t *info_ptr = &info;
-  int reg_size = TARGET_POWERPC64 ? 8 : 4;
+  int reg_size = TARGET_32BIT ? 4 : 8;
   int ehrd_size;
   HOST_WIDE_INT total_raw_size;
 
@@ -11871,7 +11871,7 @@ rs6000_emit_prologue (void)
 {
   rs6000_stack_t *info = rs6000_stack_info ();
   enum machine_mode reg_mode = Pmode;
-  int reg_size = UNITS_PER_WORD;
+  int reg_size = TARGET_32BIT ? 4 : 8;
   rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
   rtx frame_reg_rtx = sp_reg_rtx;
@@ -12338,7 +12338,7 @@ rs6000_emit_epilogue (int sibcall)
   rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
   rtx frame_reg_rtx = sp_reg_rtx;
   enum machine_mode reg_mode = Pmode;
-  int reg_size = UNITS_PER_WORD;
+  int reg_size = TARGET_32BIT ? 4 : 8;
   int i;
 
   info = rs6000_stack_info ();

gcc/config/rs6000/rs6000.h

@@ -1536,6 +1536,9 @@ extern enum rs6000_abi rs6000_current_abi;	/* available for use by subtarget */
    makes the stack pointer a smaller address.  */
 #define STACK_GROWS_DOWNWARD
 
+/* Offsets recorded in opcodes are a multiple of this alignment factor.  */
+#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
+
 /* Define this if the nominal address of the stack frame
    is at the high-address end of the local variables;
    that is, each additional local variable allocated