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Commit 32041385 by Chao-ying Fu Committed by Chao-ying Fu
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extend.texi (MIPS DSP Built-in Functions): Document the DSP REV 2. 

* doc/extend.texi (MIPS DSP Built-in Functions): Document the DSP
REV 2.
* doc/invoke.texi (-mdspr2): Document new option.
* config/mips/mips.md (UNSPEC_ABSQ_S_QB .. UNSPEC_DPSQX_SA_W_PH):
New unspec for DSP REV 2.
(<u>mulsidi3_32bit_internal): Check if !TARGET_DSPR2, because
these instructions are extended in DSP REV 2.
(mips-dspr2.md): Include.
* config/mips/mips.opt (mdspr2): New option.
* config/mips/mips.c (mips_function_type): Add MIPS_V4QI_FTYPE_V4QI,
MIPS_SI_FTYPE_SI_SI_SI, MIPS_DI_FTYPE_DI_USI_USI, MIPS_DI_FTYPE_SI_SI,
MIPS_DI_FTYPE_USI_USI, MIPS_V2HI_FTYPE_SI_SI_SI.
(override_options): Check TARGET_DSPR2 to enable MASK_DSP.
(CODE_FOR_mips_mul_ph): Define it to CODE_FOR_mulv2hi3.
(dsp_bdesc): Add DSP REV 2 builtins.  Remove 32-bit only DSP builtins.
(dsp_32only_bdesc): New description table for 32-bit only DSP REV 1
and 2 builtins.
(bdesc_map): Add one field of unsupported_target_flags.
(bdesc_arrays):  Update entries to have extra fields.  Add
dsp_32only_bdesc.
(mips_init_builtins): Initialize new function types.
Check unsupported_target_fileds to filter out builtins.
* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_dspr2 if
TARGET_DSPR2.
(ASM_SPEC): Pass mdspr2 to the assembler.
* config/mips/mips-dspr2.md: New file.

From-SVN: r122756
parent 4a71edd9
Showing with 192 additions and 10 deletions
gcc/ChangeLog
2007-03-09 Chao-ying Fu <fu@mips.com>
* doc/extend.texi (MIPS DSP Built-in Functions): Document the DSP
REV 2.
* doc/invoke.texi (-mdspr2): Document new option.
* config/mips/mips.md (UNSPEC_ABSQ_S_QB .. UNSPEC_DPSQX_SA_W_PH):
New unspec for DSP REV 2.
(<u>mulsidi3_32bit_internal): Check if !TARGET_DSPR2, because
these instructions are extended in DSP REV 2.
(mips-dspr2.md): Include.
* config/mips/mips.opt (mdspr2): New option.
* config/mips/mips.c (mips_function_type): Add MIPS_V4QI_FTYPE_V4QI,
MIPS_SI_FTYPE_SI_SI_SI, MIPS_DI_FTYPE_DI_USI_USI, MIPS_DI_FTYPE_SI_SI,
MIPS_DI_FTYPE_USI_USI, MIPS_V2HI_FTYPE_SI_SI_SI.
(override_options): Check TARGET_DSPR2 to enable MASK_DSP.
(CODE_FOR_mips_mul_ph): Define it to CODE_FOR_mulv2hi3.
(dsp_bdesc): Add DSP REV 2 builtins. Remove 32-bit only DSP builtins.
(dsp_32only_bdesc): New description table for 32-bit only DSP REV 1
and 2 builtins.
(bdesc_map): Add one field of unsupported_target_flags.
(bdesc_arrays): Update entries to have extra fields. Add
dsp_32only_bdesc.
(mips_init_builtins): Initialize new function types.
Check unsupported_target_fileds to filter out builtins.
* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_dspr2 if
TARGET_DSPR2.
(ASM_SPEC): Pass mdspr2 to the assembler.
* config/mips/mips-dspr2.md: New file.
2007-03-09 Sa Liu <saliu@de.ibm.com>
* config/rs6000/altivec.md: Fix vcond patterns using if_then_else.
......
gcc/config/mips/mips.h
......@@ -340,6 +340,9 @@ extern const struct mips_rtx_cost_data *mips_cost;
if (TARGET_DSP) \
builtin_define ("__mips_dsp"); \
\
if (TARGET_DSPR2) \
builtin_define ("__mips_dspr2"); \
\
MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
\
......@@ -820,6 +823,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%{mips3d:-mips3d} \
%{mdsp} \
%{mdspr2} \
%{mfix-vr4120} %{mfix-vr4130} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
......
gcc/config/mips/mips.md
......@@ -147,6 +147,57 @@
(UNSPEC_MTHLIP 365)
(UNSPEC_WRDSP 366)
(UNSPEC_RDDSP 367)
;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
(UNSPEC_ABSQ_S_QB 400)
(UNSPEC_ADDU_PH 401)
(UNSPEC_ADDU_S_PH 402)
(UNSPEC_ADDUH_QB 403)
(UNSPEC_ADDUH_R_QB 404)
(UNSPEC_APPEND 405)
(UNSPEC_BALIGN 406)
(UNSPEC_CMPGDU_EQ_QB 407)
(UNSPEC_CMPGDU_LT_QB 408)
(UNSPEC_CMPGDU_LE_QB 409)
(UNSPEC_DPA_W_PH 410)
(UNSPEC_DPS_W_PH 411)
(UNSPEC_MADD 412)
(UNSPEC_MADDU 413)
(UNSPEC_MSUB 414)
(UNSPEC_MSUBU 415)
(UNSPEC_MUL_PH 416)
(UNSPEC_MUL_S_PH 417)
(UNSPEC_MULQ_RS_W 418)
(UNSPEC_MULQ_S_PH 419)
(UNSPEC_MULQ_S_W 420)
(UNSPEC_MULSA_W_PH 421)
(UNSPEC_MULT 422)
(UNSPEC_MULTU 423)
(UNSPEC_PRECR_QB_PH 424)
(UNSPEC_PRECR_SRA_PH_W 425)
(UNSPEC_PRECR_SRA_R_PH_W 426)
(UNSPEC_PREPEND 427)
(UNSPEC_SHRA_QB 428)
(UNSPEC_SHRA_R_QB 429)
(UNSPEC_SHRL_PH 430)
(UNSPEC_SUBU_PH 431)
(UNSPEC_SUBU_S_PH 432)
(UNSPEC_SUBUH_QB 433)
(UNSPEC_SUBUH_R_QB 434)
(UNSPEC_ADDQH_PH 435)
(UNSPEC_ADDQH_R_PH 436)
(UNSPEC_ADDQH_W 437)
(UNSPEC_ADDQH_R_W 438)
(UNSPEC_SUBQH_PH 439)
(UNSPEC_SUBQH_R_PH 440)
(UNSPEC_SUBQH_W 441)
(UNSPEC_SUBQH_R_W 442)
(UNSPEC_DPAX_W_PH 443)
(UNSPEC_DPSX_W_PH 444)
(UNSPEC_DPAQX_S_W_PH 445)
(UNSPEC_DPAQX_SA_W_PH 446)
(UNSPEC_DPSQX_S_W_PH 447)
(UNSPEC_DPSQX_SA_W_PH 448)
]
)
......@@ -1505,7 +1556,7 @@
[(set (match_operand:DI 0 "register_operand" "=x")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
"!TARGET_64BIT && !TARGET_FIX_R4000"
"!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
"mult<u>\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
......@@ -5514,3 +5565,7 @@
; The MIPS DSP Instructions.
(include "mips-dsp.md")
; The MIPS DSP REV 2 Instructions.
(include "mips-dspr2.md")
gcc/config/mips/mips.opt
......@@ -59,6 +59,10 @@ mdsp
Target Report Mask(DSP)
Use MIPS-DSP instructions
mdspr2
Target Report Mask(DSPR2)
Use MIPS-DSP REV 2 instructions
mdebug
Target Var(TARGET_DEBUG_MODE) Undocumented
......
gcc/doc/extend.texi
......@@ -7403,25 +7403,36 @@ v2si __builtin_ia32_pswapdsi (v2si)
The MIPS DSP Application-Specific Extension (ASE) includes new
instructions that are designed to improve the performance of DSP and
media applications. It provides instructions that operate on packed
8-bit integer data, Q15 fractional data and Q31 fractional data.
8-bit/16-bit integer data, Q7, Q15 and Q31 fractional data.
GCC supports MIPS DSP operations using both the generic
vector extensions (@pxref{Vector Extensions}) and a collection of
MIPS-specific built-in functions. Both kinds of support are
enabled by the @option{-mdsp} command-line option.
Revision 2 of the ASE was introduced in the second half of 2006.
This revision adds extra instructions to the original ASE, but is
otherwise backwards-compatible with it. You can select revision 2
using the command-line option @option{-mdspr2}; this option implies
@option{-mdsp}.
At present, GCC only provides support for operations on 32-bit
vectors. The vector type associated with 8-bit integer data is
usually called @code{v4i8} and the vector type associated with Q15 is
usually called @code{v2q15}. They can be defined in C as follows:
usually called @code{v4i8}, the vector type associated with Q7
is usually called @code{v4q7}, the vector type associated with 16-bit
integer data is usually called @code{v2i16}, and the vector type
associated with Q15 is usually called @code{v2q15}. They can be
defined in C as follows:
@smallexample
typedef char v4i8 __attribute__ ((vector_size(4)));
typedef signed char v4i8 __attribute__ ((vector_size(4)));
typedef signed char v4q7 __attribute__ ((vector_size(4)));
typedef short v2i16 __attribute__ ((vector_size(4)));
typedef short v2q15 __attribute__ ((vector_size(4)));
@end smallexample
@code{v4i8} and @code{v2q15} values are initialized in the same way as
aggregates. For example:
@code{v4i8}, @code{v4q7}, @code{v2i16} and @code{v2q15} values are
initialized in the same way as aggregates. For example:
@smallexample
v4i8 a = @{1, 2, 3, 4@};
......@@ -7440,9 +7451,10 @@ order applies to big-endian targets. For example, the code above will
set the lowest byte of @code{a} to @code{1} on little-endian targets
and @code{4} on big-endian targets.
@emph{Note:} Q15 and Q31 values must be initialized with their integer
@emph{Note:} Q7, Q15 and Q31 values must be initialized with their integer
representation. As shown in this example, the integer representation
of a Q15 value can be obtained by multiplying the fractional value by
of a Q7 value can be obtained by multiplying the fractional value by
@code{0x1.0p7}. The equivalent for Q15 values is to multiply by
@code{0x1.0p15}. The equivalent for Q31 values is to multiply by
@code{0x1.0p31}.
......@@ -7458,12 +7470,22 @@ and @code{c} and @code{d} are @code{v2q15} values.
@item @code{c - d} @tab @code{subq.ph}
@end multitable
The table below lists the @code{v2i16} operation for which
hardware support exists for the DSP ASE REV 2. @code{e} and @code{f} are
@code{v2i16} values.
@multitable @columnfractions .50 .50
@item C code @tab MIPS instruction
@item @code{e * f} @tab @code{mul.ph}
@end multitable
It is easier to describe the DSP built-in functions if we first define
the following types:
@smallexample
typedef int q31;
typedef int i32;
typedef unsigned int ui32;
typedef long long a64;
@end smallexample
......@@ -7480,6 +7502,7 @@ numbers and register operands, or accept immediate numbers only. The
immediate parameters are listed as follows.
@smallexample
imm0_3: 0 to 3.
imm0_7: 0 to 7.
imm0_15: 0 to 15.
imm0_31: 0 to 31.
......@@ -7599,6 +7622,66 @@ i32 __builtin_mips_lwx (void *, i32)
i32 __builtin_mips_bposge32 (void)
@end smallexample
The following built-in functions map directly to a particular MIPS DSP REV 2
instruction. Please refer to the architecture specification
for details on what each instruction does.
@smallexample
v4q7 __builtin_mips_absq_s_qb (v4q7);
v2i16 __builtin_mips_addu_ph (v2i16, v2i16);
v2i16 __builtin_mips_addu_s_ph (v2i16, v2i16);
v4i8 __builtin_mips_adduh_qb (v4i8, v4i8);
v4i8 __builtin_mips_adduh_r_qb (v4i8, v4i8);
i32 __builtin_mips_append (i32, i32, imm0_31);
i32 __builtin_mips_balign (i32, i32, imm0_3);
i32 __builtin_mips_cmpgdu_eq_qb (v4i8, v4i8);
i32 __builtin_mips_cmpgdu_lt_qb (v4i8, v4i8);
i32 __builtin_mips_cmpgdu_le_qb (v4i8, v4i8);
a64 __builtin_mips_dpa_w_ph (a64, v2i16, v2i16);
a64 __builtin_mips_dps_w_ph (a64, v2i16, v2i16);
a64 __builtin_mips_madd (a64, i32, i32);
a64 __builtin_mips_maddu (a64, ui32, ui32);
a64 __builtin_mips_msub (a64, i32, i32);
a64 __builtin_mips_msubu (a64, ui32, ui32);
v2i16 __builtin_mips_mul_ph (v2i16, v2i16);
v2i16 __builtin_mips_mul_s_ph (v2i16, v2i16);
q31 __builtin_mips_mulq_rs_w (q31, q31);
v2q15 __builtin_mips_mulq_s_ph (v2q15, v2q15);
q31 __builtin_mips_mulq_s_w (q31, q31);
a64 __builtin_mips_mulsa_w_ph (a64, v2i16, v2i16);
a64 __builtin_mips_mult (i32, i32);
a64 __builtin_mips_multu (ui32, ui32);
v4i8 __builtin_mips_precr_qb_ph (v2i16, v2i16);
v2i16 __builtin_mips_precr_sra_ph_w (i32, i32, imm0_31);
v2i16 __builtin_mips_precr_sra_r_ph_w (i32, i32, imm0_31);
i32 __builtin_mips_prepend (i32, i32, imm0_31);
v4i8 __builtin_mips_shra_qb (v4i8, imm0_7);
v4i8 __builtin_mips_shra_r_qb (v4i8, imm0_7);
v4i8 __builtin_mips_shra_qb (v4i8, i32);
v4i8 __builtin_mips_shra_r_qb (v4i8, i32);
v2i16 __builtin_mips_shrl_ph (v2i16, imm0_15);
v2i16 __builtin_mips_shrl_ph (v2i16, i32);
v2i16 __builtin_mips_subu_ph (v2i16, v2i16);
v2i16 __builtin_mips_subu_s_ph (v2i16, v2i16);
v4i8 __builtin_mips_subuh_qb (v4i8, v4i8);
v4i8 __builtin_mips_subuh_r_qb (v4i8, v4i8);
v2q15 __builtin_mips_addqh_ph (v2q15, v2q15);
v2q15 __builtin_mips_addqh_r_ph (v2q15, v2q15);
q31 __builtin_mips_addqh_w (q31, q31);
q31 __builtin_mips_addqh_r_w (q31, q31);
v2q15 __builtin_mips_subqh_ph (v2q15, v2q15);
v2q15 __builtin_mips_subqh_r_ph (v2q15, v2q15);
q31 __builtin_mips_subqh_w (q31, q31);
q31 __builtin_mips_subqh_r_w (q31, q31);
a64 __builtin_mips_dpax_w_ph (a64, v2i16, v2i16);
a64 __builtin_mips_dpsx_w_ph (a64, v2i16, v2i16);
a64 __builtin_mips_dpaqx_s_w_ph (a64, v2q15, v2q15);
a64 __builtin_mips_dpaqx_sa_w_ph (a64, v2q15, v2q15);
a64 __builtin_mips_dpsqx_s_w_ph (a64, v2q15, v2q15);
a64 __builtin_mips_dpsqx_sa_w_ph (a64, v2q15, v2q15);
@end smallexample
@node MIPS Paired-Single Support
@subsection MIPS Paired-Single Support
......
gcc/doc/invoke.texi
......@@ -613,7 +613,7 @@ Objective-C and Objective-C++ Dialects}.
-mips16 -mno-mips16 -mabi=@var{abi} -mabicalls -mno-abicalls @gol
-mshared -mno-shared -mxgot -mno-xgot -mgp32 -mgp64 @gol
-mfp32 -mfp64 -mhard-float -msoft-float @gol
-msingle-float -mdouble-float -mdsp -mpaired-single -mips3d @gol
-msingle-float -mdouble-float -mdsp -mdspr2 -mpaired-single -mips3d @gol
-mlong64 -mlong32 -msym32 -mno-sym32 @gol
-G@var{num} -membedded-data -mno-embedded-data @gol
-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
......@@ -11318,6 +11318,13 @@ operations. This is the default.
@opindex mno-dsp
Use (do not use) the MIPS DSP ASE. @xref{MIPS DSP Built-in Functions}.
@itemx -mdspr2
@itemx -mno-dspr2
@opindex mdspr2
@opindex mno-dspr2
Use (do not use) the MIPS DSP ASE REV 2. @xref{MIPS DSP Built-in Functions}.
The option @option{-mdspr2} implies @option{-mdsp}.
@itemx -mpaired-single
@itemx -mno-paired-single
@opindex mpaired-single
......
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