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riscv-gcc-1
Commit 31fa16b6 by Richard Earnshaw Committed by Richard Earnshaw
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arm.c (arm_gen_rotated_half_load): Delete. 

	* arm.c (arm_gen_rotated_half_load): Delete.
	(vfp_emit_fstmx, arm_set_return_address): Use gen_frame_mem.
	(emit_multi_reg_push, emit_sfm, arm_expand_prologue)
	(thumb_set_return_address): Likewise.
	(thumb_load_double_from_address): Use adjust_address.
	* arm.md (splits calling arm_gen_rotated_half_load): Delete.
	(extendhsisi2_mem, movhi_bytes): Use change_address.
	(movhi): Use widen_memory_access.
	(reload_out_df): Use replace_equiv_address.
	* arm-protos.h (arm_gen_rotated_half_load): Delete prototype.

From-SVN: r104124
parent 072dd139
Showing with 48 additions and 123 deletions
gcc/ChangeLog
2005-09-10 Richard Earnshaw <richard.earnshaw@arm.com>
* arm.c (arm_gen_rotated_half_load): Delete.
(vfp_emit_fstmx, arm_set_return_address): Use gen_frame_mem.
(emit_multi_reg_push, emit_sfm, arm_expand_prologue)
(thumb_set_return_address): Likewise.
(thumb_load_double_from_address): Use adjust_address.
* arm.md (splits calling arm_gen_rotated_half_load): Delete.
(extendhsisi2_mem, movhi_bytes): Use change_address.
(movhi): Use widen_memory_access.
(reload_out_df): Use replace_equiv_address.
* arm-protos.h (arm_gen_rotated_half_load): Delete prototype.
2005-09-09 Richard Henderson <rth@redhat.com> 2005-09-09 Richard Henderson <rth@redhat.com>
PR debug/20998 PR debug/20998
......
gcc/config/arm/arm-protos.h
...@@ -87,7 +87,6 @@ extern rtx arm_gen_load_multiple (int, int, rtx, int, int, ...@@ -87,7 +87,6 @@ extern rtx arm_gen_load_multiple (int, int, rtx, int, int,
extern rtx arm_gen_store_multiple (int, int, rtx, int, int, extern rtx arm_gen_store_multiple (int, int, rtx, int, int,
rtx, HOST_WIDE_INT *); rtx, HOST_WIDE_INT *);
extern int arm_gen_movmemqi (rtx *); extern int arm_gen_movmemqi (rtx *);
extern rtx arm_gen_rotated_half_load (rtx);
extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
HOST_WIDE_INT); HOST_WIDE_INT);
......
gcc/config/arm/arm.c
...@@ -6117,30 +6117,6 @@ arm_gen_movmemqi (rtx *operands) ...@@ -6117,30 +6117,6 @@ arm_gen_movmemqi (rtx *operands)
into the top 16 bits of the word. We can assume that the address is into the top 16 bits of the word. We can assume that the address is
known to be alignable and of the form reg, or plus (reg, const). */ known to be alignable and of the form reg, or plus (reg, const). */
rtx
arm_gen_rotated_half_load (rtx memref)
{
HOST_WIDE_INT offset = 0;
rtx base = XEXP (memref, 0);
if (GET_CODE (base) == PLUS)
{
offset = INTVAL (XEXP (base, 1));
base = XEXP (base, 0);
}
/* If we aren't allowed to generate unaligned addresses, then fail. */
if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
return NULL;
base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
return base;
return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
}
/* Select a dominance comparison mode if possible for a test of the general /* Select a dominance comparison mode if possible for a test of the general
form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
COND_OR == DOM_CC_X_AND_Y => (X && Y) COND_OR == DOM_CC_X_AND_Y => (X && Y)
...@@ -8128,8 +8104,9 @@ vfp_emit_fstmx (int base_reg, int count) ...@@ -8128,8 +8104,9 @@ vfp_emit_fstmx (int base_reg, int count)
XVECEXP (par, 0, 0) XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode, = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (BLKmode, gen_frame_mem (BLKmode,
gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), gen_rtx_PRE_DEC (BLKmode,
stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode, gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg), gen_rtvec (1, reg),
UNSPEC_PUSH_MULT)); UNSPEC_PUSH_MULT));
...@@ -8141,7 +8118,7 @@ vfp_emit_fstmx (int base_reg, int count) ...@@ -8141,7 +8118,7 @@ vfp_emit_fstmx (int base_reg, int count)
XVECEXP (dwarf, 0, 0) = tmp; XVECEXP (dwarf, 0, 0) = tmp;
tmp = gen_rtx_SET (VOIDmode, tmp = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (DFmode, stack_pointer_rtx), gen_frame_mem (DFmode, stack_pointer_rtx),
reg); reg);
RTX_FRAME_RELATED_P (tmp) = 1; RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, 1) = tmp; XVECEXP (dwarf, 0, 1) = tmp;
...@@ -8153,7 +8130,7 @@ vfp_emit_fstmx (int base_reg, int count) ...@@ -8153,7 +8130,7 @@ vfp_emit_fstmx (int base_reg, int count)
XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
tmp = gen_rtx_SET (VOIDmode, tmp = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (DFmode, gen_frame_mem (DFmode,
gen_rtx_PLUS (SImode, gen_rtx_PLUS (SImode,
stack_pointer_rtx, stack_pointer_rtx,
GEN_INT (i * 8))), GEN_INT (i * 8))),
...@@ -9851,7 +9828,7 @@ emit_multi_reg_push (unsigned long mask) ...@@ -9851,7 +9828,7 @@ emit_multi_reg_push (unsigned long mask)
XVECEXP (par, 0, 0) XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode, = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (BLKmode, gen_frame_mem (BLKmode,
gen_rtx_PRE_DEC (BLKmode, gen_rtx_PRE_DEC (BLKmode,
stack_pointer_rtx)), stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode, gen_rtx_UNSPEC (BLKmode,
...@@ -9861,7 +9838,7 @@ emit_multi_reg_push (unsigned long mask) ...@@ -9861,7 +9838,7 @@ emit_multi_reg_push (unsigned long mask)
if (i != PC_REGNUM) if (i != PC_REGNUM)
{ {
tmp = gen_rtx_SET (VOIDmode, tmp = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (SImode, stack_pointer_rtx), gen_frame_mem (SImode, stack_pointer_rtx),
reg); reg);
RTX_FRAME_RELATED_P (tmp) = 1; RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, dwarf_par_index) = tmp; XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
...@@ -9882,8 +9859,9 @@ emit_multi_reg_push (unsigned long mask) ...@@ -9882,8 +9859,9 @@ emit_multi_reg_push (unsigned long mask)
if (i != PC_REGNUM) if (i != PC_REGNUM)
{ {
tmp = gen_rtx_SET (VOIDmode, tmp
gen_rtx_MEM (SImode, = gen_rtx_SET (VOIDmode,
gen_frame_mem (SImode,
plus_constant (stack_pointer_rtx, plus_constant (stack_pointer_rtx,
4 * j)), 4 * j)),
reg); reg);
...@@ -9939,13 +9917,14 @@ emit_sfm (int base_reg, int count) ...@@ -9939,13 +9917,14 @@ emit_sfm (int base_reg, int count)
XVECEXP (par, 0, 0) XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode, = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (BLKmode, gen_frame_mem (BLKmode,
gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), gen_rtx_PRE_DEC (BLKmode,
stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode, gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg), gen_rtvec (1, reg),
UNSPEC_PUSH_MULT)); UNSPEC_PUSH_MULT));
tmp = gen_rtx_SET (VOIDmode, tmp = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (XFmode, stack_pointer_rtx), reg); gen_frame_mem (XFmode, stack_pointer_rtx), reg);
RTX_FRAME_RELATED_P (tmp) = 1; RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, 1) = tmp; XVECEXP (dwarf, 0, 1) = tmp;
...@@ -9955,7 +9934,7 @@ emit_sfm (int base_reg, int count) ...@@ -9955,7 +9934,7 @@ emit_sfm (int base_reg, int count)
XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
tmp = gen_rtx_SET (VOIDmode, tmp = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (XFmode, gen_frame_mem (XFmode,
plus_constant (stack_pointer_rtx, plus_constant (stack_pointer_rtx,
i * 12)), i * 12)),
reg); reg);
...@@ -10309,7 +10288,7 @@ arm_expand_prologue (void) ...@@ -10309,7 +10288,7 @@ arm_expand_prologue (void)
{ {
rtx dwarf; rtx dwarf;
insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
insn = gen_rtx_MEM (SImode, insn); insn = gen_frame_mem (SImode, insn);
insn = gen_rtx_SET (VOIDmode, insn, ip_rtx); insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
insn = emit_insn (insn); insn = emit_insn (insn);
...@@ -10398,7 +10377,7 @@ arm_expand_prologue (void) ...@@ -10398,7 +10377,7 @@ arm_expand_prologue (void)
if (regs_ever_live[reg] && ! call_used_regs [reg]) if (regs_ever_live[reg] && ! call_used_regs [reg])
{ {
insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
insn = gen_rtx_MEM (V2SImode, insn); insn = gen_frame_mem (V2SImode, insn);
insn = emit_insn (gen_rtx_SET (VOIDmode, insn, insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
gen_rtx_REG (V2SImode, reg))); gen_rtx_REG (V2SImode, reg)));
RTX_FRAME_RELATED_P (insn) = 1; RTX_FRAME_RELATED_P (insn) = 1;
...@@ -10417,7 +10396,7 @@ arm_expand_prologue (void) ...@@ -10417,7 +10396,7 @@ arm_expand_prologue (void)
if (regs_ever_live[reg] && !call_used_regs[reg]) if (regs_ever_live[reg] && !call_used_regs[reg])
{ {
insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
insn = gen_rtx_MEM (XFmode, insn); insn = gen_frame_mem (XFmode, insn);
insn = emit_insn (gen_rtx_SET (VOIDmode, insn, insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
gen_rtx_REG (XFmode, reg))); gen_rtx_REG (XFmode, reg)));
RTX_FRAME_RELATED_P (insn) = 1; RTX_FRAME_RELATED_P (insn) = 1;
...@@ -10497,7 +10476,7 @@ arm_expand_prologue (void) ...@@ -10497,7 +10476,7 @@ arm_expand_prologue (void)
{ {
insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
GEN_INT (4)); GEN_INT (4));
insn = gen_rtx_MEM (SImode, insn); insn = gen_frame_mem (SImode, insn);
} }
emit_insn (gen_rtx_SET (SImode, ip_rtx, insn)); emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
...@@ -13716,8 +13695,7 @@ thumb_load_double_from_address (rtx *operands) ...@@ -13716,8 +13695,7 @@ thumb_load_double_from_address (rtx *operands)
switch (GET_CODE (addr)) switch (GET_CODE (addr))
{ {
case REG: case REG:
operands[2] = gen_rtx_MEM (SImode, operands[2] = adjust_address (operands[1], SImode, 4);
plus_constant (XEXP (operands[1], 0), 4));
if (REGNO (operands[0]) == REGNO (addr)) if (REGNO (operands[0]) == REGNO (addr))
{ {
...@@ -13733,8 +13711,7 @@ thumb_load_double_from_address (rtx *operands) ...@@ -13733,8 +13711,7 @@ thumb_load_double_from_address (rtx *operands)
case CONST: case CONST:
/* Compute <address> + 4 for the high order load. */ /* Compute <address> + 4 for the high order load. */
operands[2] = gen_rtx_MEM (SImode, operands[2] = adjust_address (operands[1], SImode, 4);
plus_constant (XEXP (operands[1], 0), 4));
output_asm_insn ("ldr\t%0, %1", operands); output_asm_insn ("ldr\t%0, %1", operands);
output_asm_insn ("ldr\t%H0, %2", operands); output_asm_insn ("ldr\t%H0, %2", operands);
...@@ -13776,8 +13753,8 @@ thumb_load_double_from_address (rtx *operands) ...@@ -13776,8 +13753,8 @@ thumb_load_double_from_address (rtx *operands)
else else
{ {
/* Compute <address> + 4 for the high order load. */ /* Compute <address> + 4 for the high order load. */
operands[2] = gen_rtx_MEM (SImode, operands[2] = adjust_address (operands[1], SImode, 4);
plus_constant (XEXP (operands[1], 0), 4));
/* If the computed address is held in the low order register /* If the computed address is held in the low order register
then load the high order register first, otherwise always then load the high order register first, otherwise always
...@@ -13798,8 +13775,7 @@ thumb_load_double_from_address (rtx *operands) ...@@ -13798,8 +13775,7 @@ thumb_load_double_from_address (rtx *operands)
case LABEL_REF: case LABEL_REF:
/* With no registers to worry about we can just load the value /* With no registers to worry about we can just load the value
directly. */ directly. */
operands[2] = gen_rtx_MEM (SImode, operands[2] = adjust_address (operands[1], SImode, 4);
plus_constant (XEXP (operands[1], 0), 4));
output_asm_insn ("ldr\t%H0, %2", operands); output_asm_insn ("ldr\t%H0, %2", operands);
output_asm_insn ("ldr\t%0, %1", operands); output_asm_insn ("ldr\t%0, %1", operands);
...@@ -14694,7 +14670,7 @@ arm_set_return_address (rtx source, rtx scratch) ...@@ -14694,7 +14670,7 @@ arm_set_return_address (rtx source, rtx scratch)
addr = plus_constant (addr, delta); addr = plus_constant (addr, delta);
} }
emit_move_insn (gen_rtx_MEM (Pmode, addr), source); emit_move_insn (gen_frame_mem (Pmode, addr), source);
} }
} }
...@@ -14744,7 +14720,7 @@ thumb_set_return_address (rtx source, rtx scratch) ...@@ -14744,7 +14720,7 @@ thumb_set_return_address (rtx source, rtx scratch)
else else
addr = plus_constant (addr, delta); addr = plus_constant (addr, delta);
emit_move_insn (gen_rtx_MEM (Pmode, addr), source); emit_move_insn (gen_frame_mem (Pmode, addr), source);
} }
else else
emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
......
gcc/config/arm/arm.md
...@@ -3390,36 +3390,6 @@ ...@@ -3390,36 +3390,6 @@
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (match_operand:HI 1 "alignable_memory_operand" "")))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
"TARGET_ARM && (!arm_arch4)"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (lshiftrt:SI (match_dup 2) (const_int 16)))]
"
if ((operands[1] = arm_gen_rotated_half_load (operands[1])) == NULL)
FAIL;
"
)
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(match_operator:SI 3 "shiftable_operator"
[(zero_extend:SI (match_operand:HI 1 "alignable_memory_operand" ""))
(match_operand:SI 4 "s_register_operand" "")]))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
"TARGET_ARM && (!arm_arch4)"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0)
(match_op_dup 3
[(lshiftrt:SI (match_dup 2) (const_int 16)) (match_dup 4)]))]
"
if ((operands[1] = arm_gen_rotated_half_load (operands[1])) == NULL)
FAIL;
"
)
(define_expand "zero_extendqisi2" (define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "s_register_operand" "") [(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
...@@ -3721,10 +3691,8 @@ ...@@ -3721,10 +3691,8 @@
rtx mem1, mem2; rtx mem1, mem2;
rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
mem1 = gen_rtx_MEM (QImode, addr); mem1 = change_address (operands[1], QImode, addr);
MEM_COPY_ATTRIBUTES (mem1, operands[1]); mem2 = change_address (operands[1], QImode, plus_constant (addr, 1));
mem2 = gen_rtx_MEM (QImode, plus_constant (addr, 1));
MEM_COPY_ATTRIBUTES (mem2, operands[1]);
operands[0] = gen_lowpart (SImode, operands[0]); operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = mem1; operands[1] = mem1;
operands[2] = gen_reg_rtx (SImode); operands[2] = gen_reg_rtx (SImode);
...@@ -3777,35 +3745,6 @@ ...@@ -3777,35 +3745,6 @@
"sxtah%?\\t%0, %2, %1" "sxtah%?\\t%0, %2, %1"
) )
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(sign_extend:SI (match_operand:HI 1 "alignable_memory_operand" "")))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
"TARGET_ARM && (!arm_arch4)"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (ashiftrt:SI (match_dup 2) (const_int 16)))]
"
if ((operands[1] = arm_gen_rotated_half_load (operands[1])) == NULL)
FAIL;
"
)
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(match_operator:SI 3 "shiftable_operator"
[(sign_extend:SI (match_operand:HI 1 "alignable_memory_operand" ""))
(match_operand:SI 4 "s_register_operand" "")]))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
"TARGET_ARM && (!arm_arch4)"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0)
(match_op_dup 3
[(ashiftrt:SI (match_dup 2) (const_int 16)) (match_dup 4)]))]
"if ((operands[1] = arm_gen_rotated_half_load (operands[1])) == NULL)
FAIL;
"
)
(define_expand "extendqihi2" (define_expand "extendqihi2"
[(set (match_dup 2) [(set (match_dup 2)
(ashift:SI (match_operand:QI 1 "general_operand" "") (ashift:SI (match_operand:QI 1 "general_operand" "")
...@@ -4750,12 +4689,11 @@ ...@@ -4750,12 +4689,11 @@
&& GET_CODE (base = XEXP (base, 0)) == REG)) && GET_CODE (base = XEXP (base, 0)) == REG))
&& REGNO_POINTER_ALIGN (REGNO (base)) >= 32) && REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
{ {
HOST_WIDE_INT new_offset = INTVAL (offset) & ~3;
rtx new; rtx new;
new = gen_rtx_MEM (SImode, new = widen_memory_access (operands[1], SImode,
plus_constant (base, new_offset)); ((INTVAL (offset) & ~3)
MEM_COPY_ATTRIBUTES (new, operands[1]); - INTVAL (offset)));
emit_insn (gen_movsi (reg, new)); emit_insn (gen_movsi (reg, new));
if (((INTVAL (offset) & 2) != 0) if (((INTVAL (offset) & 2) != 0)
^ (BYTES_BIG_ENDIAN ? 1 : 0)) ^ (BYTES_BIG_ENDIAN ? 1 : 0))
...@@ -4882,10 +4820,8 @@ ...@@ -4882,10 +4820,8 @@
rtx mem1, mem2; rtx mem1, mem2;
rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
mem1 = gen_rtx_MEM (QImode, addr); mem1 = change_address (operands[1], QImode, addr);
MEM_COPY_ATTRIBUTES (mem1, operands[1]); mem2 = change_address (operands[1], QImode, plus_constant (addr, 1));
mem2 = gen_rtx_MEM (QImode, plus_constant (addr, 1));
MEM_COPY_ATTRIBUTES (mem2, operands[1]);
operands[0] = gen_lowpart (SImode, operands[0]); operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = mem1; operands[1] = mem1;
operands[2] = gen_reg_rtx (SImode); operands[2] = gen_reg_rtx (SImode);
...@@ -5233,7 +5169,8 @@ ...@@ -5233,7 +5169,8 @@
emit_insn (gen_addsi3 (operands[2], XEXP (XEXP (operands[0], 0), 0), emit_insn (gen_addsi3 (operands[2], XEXP (XEXP (operands[0], 0), 0),
XEXP (XEXP (operands[0], 0), 1))); XEXP (XEXP (operands[0], 0), 1)));
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (DFmode, operands[2]), emit_insn (gen_rtx_SET (VOIDmode,
replace_equiv_address (operands[0], operands[2]),
operands[1])); operands[1]));
if (code == POST_DEC) if (code == POST_DEC)
......
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