Add FR30 port.

From-SVN: r29549

gcc/ChangeLog

+Tue Sep 21 14:13:27 1999  Nick Clifton  <nickc@cygnus.com>
+
+	* configure.in: Add fr30 target.
+	* configure: Regenerate.
+	* config/fr30: New directory.
+	* config/fr30/crti.asm: New file.
+	* config/fr30/fr30.c: New file.
+	* config/fr30/crtn.asm: New file.
+	* config/fr30/fr30.h: New file.
+	* config/fr30/fr30.md: New file.
+	* config/fr30/lib1funcs.asm: New file.
+	* config/fr30/t-fr30: New file.
+	* config/fr30/xm-fr30.h: New file.
+
 Tue Sep 21 06:45:31 1999  Jeffrey A Law  (law@cygnus.com)
 
 	* flow.c (merge_blocks_move_successor_nojumps): Delete the

gcc/config/fr30/crti.asm

+# crti.s for ELF
+
+#   Copyright (C) 1992, 1998, 1999 Free Software Foundation, Inc.
+#   Written By David Vinayak Henkel-Wallace, June 1992
+# 
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 2, or (at your option) any
+# later version.
+# 
+# In addition to the permissions in the GNU General Public License, the
+# Free Software Foundation gives you unlimited permission to link the
+# compiled version of this file with other programs, and to distribute
+# those programs without any restriction coming from the use of this
+# file.  (The General Public License restrictions do apply in other
+# respects; for example, they cover modification of the file, and
+# distribution when not linked into another program.)
+# 
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING.  If not, write to
+# the Free Software Foundation, 59 Temple Place - Suite 330,
+# Boston, MA 02111-1307, USA.
+# 
+#    As a special exception, if you link this library with files
+#    compiled with GCC to produce an executable, this does not cause
+#    the resulting executable to be covered by the GNU General Public License.
+#    This exception does not however invalidate any other reasons why
+#    the executable file might be covered by the GNU General Public License.
+# 
+
+# This file just make a stack frame for the contents of the .fini and
+# .init sections.  Users may put any desired instructions in those
+# sections.
+
+	.file		"crti.asm"
+
+	.section	".init"
+	.global	_init
+	.type	_init,#function
+	.align	4
+_init:
+	st	rp, @-r15
+	enter	#4
+
+	# These nops are here to align the end of this code with a 16 byte
+	# boundary.  The linker will start inserting code into the .init
+	# section at such a boundary.
+	
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	
+	.section	".fini"
+	.global	_fini
+	.type	_fini,#function
+	.align	4
+_fini:
+	st	rp, @-r15
+	enter	#4
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop

gcc/config/fr30/crtn.asm

+# crtn.asm for ELF 
+
+#   Copyright (C) 1992, 1999 Free Software Foundation, Inc.
+#   Written By David Vinayak Henkel-Wallace, June 1992
+# 
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 2, or (at your option) any
+# later version.
+# 
+# In addition to the permissions in the GNU General Public License, the
+# Free Software Foundation gives you unlimited permission to link the
+# compiled version of this file with other programs, and to distribute
+# those programs without any restriction coming from the use of this
+# file.  (The General Public License restrictions do apply in other
+# respects; for example, they cover modification of the file, and
+# distribution when not linked into another program.)
+# 
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING.  If not, write to
+# the Free Software Foundation, 59 Temple Place - Suite 330,
+# Boston, MA 02111-1307, USA.
+# 
+#    As a special exception, if you link this library with files
+#    compiled with GCC to produce an executable, this does not cause
+#    the resulting executable to be covered by the GNU General Public License.
+#    This exception does not however invalidate any other reasons why
+#    the executable file might be covered by the GNU General Public License.
+# 
+
+# This file just makes sure that the .fini and .init sections do in
+# fact return.  Users may put any desired instructions in those sections.
+# This file is the last thing linked into any executable.
+
+	.file		"crtn.s"
+
+	.section	".init"
+	.align		4
+
+	leave
+	ld @r15+,rp
+	ret
+
+	
+	.section	".fini"
+	.align		4
+
+	leave
+	ld @r15+,rp
+	ret
+
+# Th-th-th-that is all folks!

gcc/config/fr30/fr30.c

+/*{{{  Introduction */ 
+
+/* FR30 specific functions.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/*}}}*/
+/*{{{  Includes */ 
+
+#include <stdio.h>
+#include <ctype.h>
+#include <sys/param.h> /* so that MIn and MAX are defined before machmode.h */
+#include "config.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "tree.h"
+#include "expr.h"
+#include "obstack.h"
+#include "except.h"
+#include "function.h"
+
+/*}}}*/
+/*{{{  Function Prologues & Epilogues */ 
+
+/* Define the information needed to generate branch and scc insns.  This is
+   stored from the compare operation.  */
+
+struct rtx_def * fr30_compare_op0;
+struct rtx_def * fr30_compare_op1;
+
+/* The FR30 stack looks like this:
+
+             Before call                       After call
+   FP ->|                       |       |                       |
+        +-----------------------+       +-----------------------+       high 
+        |                       |       |                       |       memory
+        |  local variables,     |       |  local variables,     |
+        |  reg save area, etc.  |       |  reg save area, etc.  |
+        |                       |       |                       |
+        +-----------------------+       +-----------------------+
+        |                       |       |                       |
+        | args to the func that |       |  args to this func.   |
+        | is being called that  |       |                       |
+   SP ->| do not fit in regs    |       |                       |
+        +-----------------------+       +-----------------------+
+                                        |  args that used to be |  \
+                                        | in regs; only created |   |  pretend_size 
+                                   AP-> |   for vararg funcs    |  /  
+                                        +-----------------------+    
+                                        |                       |  \  
+                                        |  register save area   |   |
+                                        |                       |   |
+					+-----------------------+   |  reg_size
+                                        |    return address     |   | 
+					+-----------------------+   |
+                                   FP ->|   previous frame ptr  |  /
+                                        +-----------------------+    
+                                        |                       |  \   
+                                        |  local variables      |   |  var_size 
+                                        |                       |  /  
+                                        +-----------------------+    
+                                        |                       |  \       
+     low                                |  room for args to     |   |
+     memory                             |  other funcs called   |   |  args_size     
+                                        |  from this one        |   |
+                                   SP ->|                       |  /  
+                                        +-----------------------+    
+   
+   Note, AP is a fake hard register.  It will be eliminated in favour of
+   SP or FP as appropriate.
+
+   Note, Some or all of the stack sections above may be omitted if they 
+   are not needed.  */
+
+/* Structure to be filled in by fr30_compute_frame_size() with register
+   save masks, and offsets for the current function.  */
+struct fr30_frame_info
+{
+  unsigned int total_size;	/* # Bytes that the entire frame takes up. */
+  unsigned int pretend_size;	/* # Bytes we push and pretend caller did. */
+  unsigned int args_size;	/* # Bytes that outgoing arguments take up. */
+  unsigned int reg_size;	/* # Bytes needed to store regs. */
+  unsigned int var_size;	/* # Bytes that variables take up. */
+  unsigned int frame_size;      /* # Bytes in current frame.  */
+  unsigned int gmask;		/* Mask of saved registers. */
+  unsigned int save_fp;		/* Nonzero if frame pointer must be saved. */
+  unsigned int save_rp;		/* Nonzero if return popinter must be saved. */
+  int          initialised;	/* Nonzero if frame size already calculated. */
+};
+
+/* Current frame information calculated by fr30_compute_frame_size().  */
+static struct fr30_frame_info 	current_frame_info;
+
+/* Zero structure to initialize current_frame_info.  */
+static struct fr30_frame_info 	zero_frame_info;
+
+#define FRAME_POINTER_MASK 	(1 << (FRAME_POINTER_REGNUM))
+#define RETURN_POINTER_MASK 	(1 << (RETURN_POINTER_REGNUM))
+
+/* Tell prologue and epilogue if register REGNO should be saved / restored.
+   The return address and frame pointer are treated separately.
+   Don't consider them here.  */
+#define MUST_SAVE_REGISTER(regno)      \
+  (   (regno) != RETURN_POINTER_REGNUM \
+   && (regno) != FRAME_POINTER_REGNUM  \
+   &&   regs_ever_live [regno]         \
+   && ! call_used_regs [regno]         )
+
+#define MUST_SAVE_FRAME_POINTER	 (regs_ever_live [FRAME_POINTER_REGNUM]  || frame_pointer_needed)
+#define MUST_SAVE_RETURN_POINTER (regs_ever_live [RETURN_POINTER_REGNUM] || profile_flag)
+
+#if UNITS_PER_WORD == 4
+#define WORD_ALIGN(SIZE) (((SIZE) + 3) & ~3)
+#endif
+     
+/* Returns the number of bytes offset between FROM_REG and TO_REG
+   for the current function.  As a side effect it fills in the 
+   current_frame_info structure, if the data is available.  */
+unsigned int
+fr30_compute_frame_size (from_reg, to_reg)
+     int from_reg;
+     int to_reg;
+{
+  int 		regno;
+  unsigned int 	return_value;
+  unsigned int	var_size;
+  unsigned int	args_size;
+  unsigned int	pretend_size;
+  unsigned int 	reg_size;
+  unsigned int 	gmask;
+
+  var_size	= WORD_ALIGN (get_frame_size ());
+  args_size	= WORD_ALIGN (current_function_outgoing_args_size);
+  pretend_size	= current_function_pretend_args_size;
+
+  reg_size	= 0;
+  gmask		= 0;
+
+  /* Calculate space needed for registers.  */
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
+    {
+      if (MUST_SAVE_REGISTER (regno))
+	{
+	  reg_size += UNITS_PER_WORD;
+	  gmask |= 1 << regno;
+	}
+    }
+
+  current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
+  current_frame_info.save_rp = MUST_SAVE_RETURN_POINTER;
+
+  reg_size += (current_frame_info.save_fp + current_frame_info.save_rp)
+	       * UNITS_PER_WORD;
+
+  /* Save computed information.  */
+  current_frame_info.pretend_size = pretend_size;
+  current_frame_info.var_size     = var_size;
+  current_frame_info.args_size    = args_size;
+  current_frame_info.reg_size	  = reg_size;
+  current_frame_info.frame_size   = args_size + var_size;
+  current_frame_info.total_size   = args_size + var_size + reg_size + pretend_size;
+  current_frame_info.gmask	  = gmask;
+  current_frame_info.initialised  = reload_completed;
+
+  /* Calculate the required distance.  */
+  return_value = 0;
+  
+  if (to_reg == STACK_POINTER_REGNUM)
+    return_value += args_size + var_size;
+  
+  if (from_reg == ARG_POINTER_REGNUM)
+    return_value += reg_size;
+
+  return return_value;
+}
+
+/* Called after register allocation to add any instructions needed for the
+   prologue.  Using a prologue insn is favored compared to putting all of the
+   instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
+   to intermix instructions with the saves of the caller saved registers.  In
+   some cases, it might be necessary to emit a barrier instruction as the last
+   insn to prevent such scheduling.  */
+
+void
+fr30_expand_prologue ()
+{
+  int regno;
+  rtx insn;
+
+  if (! current_frame_info.initialised)
+    fr30_compute_frame_size (0, 0);
+
+  /* This cases shouldn't happen.  Catch it now.  */
+  if (current_frame_info.total_size == 0
+      && current_frame_info.gmask)
+    abort ();
+
+  /* Allocate space for register arguments if this is a variadic function.  */
+  if (current_frame_info.pretend_size)
+    {
+      int regs_to_save = current_frame_info.pretend_size / UNITS_PER_WORD;
+      
+      /* Push argument registers into the pretend arg area.  */
+      for (regno = FIRST_ARG_REGNUM + FR30_NUM_ARG_REGS; regno --, regs_to_save --;)
+        {
+	  insn = emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, regno)));
+	  RTX_FRAME_RELATED_P (insn) = 1;
+	}
+    }
+
+  if (current_frame_info.gmask)
+    {
+      /* Save any needed call-saved regs.  */
+      for (regno = STACK_POINTER_REGNUM; regno--;)
+	{
+	  if ((current_frame_info.gmask & (1 << regno)) != 0)
+	    {
+	      insn = emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, regno)));
+	      RTX_FRAME_RELATED_P (insn) = 1;
+	    }
+	}
+    }
+
+  /* Save return address if necessary.  */
+  if (current_frame_info.save_rp)
+    {
+      insn = emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, 
+      						     RETURN_POINTER_REGNUM)));
+      RTX_FRAME_RELATED_P (insn) = 1;
+    }
+
+  /* Save old frame pointer and create new one, if necessary.  */
+  if (current_frame_info.save_fp)
+    {
+      if (current_frame_info.frame_size < ((1 << 10) - UNITS_PER_WORD))
+        {
+	  int enter_size = current_frame_info.frame_size + UNITS_PER_WORD;
+	  rtx pattern;
+	  
+	  insn = emit_insn (gen_enter_func (GEN_INT (enter_size)));
+          RTX_FRAME_RELATED_P (insn) = 1;
+	  
+	  pattern = PATTERN (insn);
+	  
+	  /* Also mark all 3 subexpressions as RTX_FRAME_RELATED_P. */
+          if (GET_CODE (pattern) == PARALLEL)
+            {
+              int x;
+              for (x = XVECLEN (pattern, 0); x--;)
+		{
+		  rtx part = XVECEXP (pattern, 0, x);
+		  
+		  /* One of the insns in the ENTER pattern updates the
+		     frame pointer.  If we do not actually need the frame
+		     pointer in this function then this is a side effect
+		     rather than a desired effect, so we do not mark that
+		     insn as being related to the frame set up.  Doing this
+		     allows us to compile the crash66.C test file in the
+		     G++ testsuite.  */
+		  if (! frame_pointer_needed
+		      && GET_CODE (part) == SET
+		      && REGNO (SET_DEST (part)) == HARD_FRAME_POINTER_REGNUM)
+		    RTX_FRAME_RELATED_P (part) = 0;
+		  else
+		    RTX_FRAME_RELATED_P (part) = 1;
+		}
+            }
+	}
+      else
+	{
+	  insn = emit_insn (gen_movsi_push (frame_pointer_rtx));
+          RTX_FRAME_RELATED_P (insn) = 1;
+
+	  if (frame_pointer_needed)
+	    {
+	      insn = emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
+	      RTX_FRAME_RELATED_P (insn) = 1;
+	    }
+	}
+    }
+
+  /* Allocate the stack frame.  */
+  if (current_frame_info.frame_size == 0)
+    ; /* Nothing to do.  */
+  else if (current_frame_info.save_fp
+	   && current_frame_info.frame_size < ((1 << 10) - UNITS_PER_WORD))
+    ; /* Nothing to do.  */
+  else if (current_frame_info.frame_size <= 512)
+    {
+      insn = emit_insn (gen_add_to_stack (GEN_INT (- current_frame_info.frame_size)));
+      RTX_FRAME_RELATED_P (insn) = 1;
+    }
+  else
+    {
+      rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
+      insn = emit_insn (gen_movsi (tmp, GEN_INT (current_frame_info.frame_size)));
+      RTX_FRAME_RELATED_P (insn) = 1;
+      insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
+      RTX_FRAME_RELATED_P (insn) = 1;
+    }
+
+  if (profile_flag || profile_block_flag)
+    emit_insn (gen_blockage ());
+}
+
+/* Called after register allocation to add any instructions needed for the
+   epilogue.  Using a epilogue insn is favored compared to putting all of the
+   instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
+   to intermix instructions with the restores of the caller saved registers.
+   In some cases, it might be necessary to emit a barrier instruction as the
+   first insn to prevent such scheduling.  */
+void
+fr30_expand_epilogue ()
+{
+  int regno;
+
+  /* Perform the inversion operations of the prologue.  */
+  if (! current_frame_info.initialised)
+    abort ();
+
+  /* Pop local variables and arguments off the stack.
+     If frame_pointer_needed is TRUE then the frame pointer register
+     has actually been used as a frame pointer, and we can recover
+     the stack pointer from it, otherwise we must unwind the stack
+     manually.  */
+  if (current_frame_info.frame_size > 0)
+    {
+      if (current_frame_info.save_fp && frame_pointer_needed)
+	{
+	  emit_insn (gen_leave_func ());
+	  current_frame_info.save_fp = 0;
+	}
+      else if (current_frame_info.frame_size <= 508)
+	emit_insn (gen_add_to_stack
+		   (GEN_INT (current_frame_info.frame_size)));
+      else
+	{
+	  rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
+	  emit_insn (gen_movsi (tmp, GEN_INT (current_frame_info.frame_size)));
+	  emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
+	}
+    }
+  
+  if (current_frame_info.save_fp)
+    emit_insn (gen_movsi_pop (frame_pointer_rtx));
+  
+  /* Pop all the registers that were pushed.  */
+  if (current_frame_info.save_rp)
+    emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, RETURN_POINTER_REGNUM)));
+    
+  for (regno = 0; regno < STACK_POINTER_REGNUM; regno ++)
+    if (current_frame_info.gmask & (1 << regno))
+      emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno)));
+  
+  if (current_frame_info.pretend_size)
+    emit_insn (gen_add_to_stack (GEN_INT (current_frame_info.pretend_size)));
+
+  /* Reset state info for each function.  */
+  current_frame_info = zero_frame_info;
+
+  emit_insn (gen_return_from_func ());
+}
+
+/* Do any needed setup for a variadic function.  We must create a register
+   parameter block, and then copy any anonymous arguments, plus the last
+   named argument, from registers into memory.  * copying actually done in
+   fr30_expand_prologue().
+
+   ARG_REGS_USED_SO_FAR has *not* been updated for the last named argument
+   which has type TYPE and mode MODE, and we rely on this fact.  */
+void
+fr30_setup_incoming_varargs (arg_regs_used_so_far, int_mode, type, pretend_size)
+     CUMULATIVE_ARGS arg_regs_used_so_far;
+     int             int_mode;
+     tree            type;
+     int *           pretend_size;
+{
+  enum machine_mode mode = (enum machine_mode)int_mode;
+  int               size;
+
+  
+  /* All BLKmode values are passed by reference.  */
+  if (mode == BLKmode)
+    abort ();
+
+#if STRICT_ARGUMENT_NAMING
+  /* We must treat `__builtin_va_alist' as an anonymous arg.
+     But otherwise if STRICT_ARGUMENT_NAMING is true then the
+     last named arg must not be treated as an anonymous arg. */
+  if (! current_function_varargs)
+    arg_regs_used_so_far += fr30_num_arg_regs (int_mode, type);
+#endif
+  
+  size = FR30_NUM_ARG_REGS - arg_regs_used_so_far;
+
+  if (size <= 0)
+    return;
+
+  * pretend_size = (size * UNITS_PER_WORD);
+}
+
+/*}}}*/
+/*{{{  Printing operands */ 
+
+/* Print a memory address as an operand to reference that memory location.  */
+
+void
+fr30_print_operand_address (stream, address)
+     FILE * stream;
+     rtx    address;
+{
+  switch (GET_CODE (address))
+    {
+    case SYMBOL_REF:
+      output_addr_const (stream, address);
+      break;
+      
+    default:
+      fprintf (stderr, "code = %x\n", GET_CODE (address));
+      debug_rtx (address);
+      output_operand_lossage ("fr30_print_operand_address: unhandled address");
+      break;
+    }
+}
+
+/* Print an operand.  */
+
+void
+fr30_print_operand (file, x, code)
+     FILE * file;
+     rtx    x;
+     int    code;
+{
+  rtx x0;
+  
+  switch (code)
+    {
+    case '#':
+      /* Output a :D if this instruction is delayed.  */
+      if (dbr_sequence_length () != 0)
+	fputs (":D", file);
+      return;
+      
+    case 'p':
+      /* Compute the register name of the second register in a hi/lo
+	 register pair.  */
+      if (GET_CODE (x) != REG)
+	output_operand_lossage ("fr30_print_operand: unrecognised %p code");
+      else
+	fprintf (file, "r%d", REGNO (x) + 1);
+      return;
+      
+    case 'b':
+      /* Convert GCC's comparison operators into FR30 comparison codes.  */
+      switch (GET_CODE (x))
+	{
+	case EQ:  fprintf (file, "eq"); break;
+	case NE:  fprintf (file, "ne"); break;
+	case LT:  fprintf (file, "lt"); break;
+	case LE:  fprintf (file, "le"); break;
+	case GT:  fprintf (file, "gt"); break;
+	case GE:  fprintf (file, "ge"); break;
+	case LTU: fprintf (file, "c"); break;
+	case LEU: fprintf (file, "ls"); break;
+	case GTU: fprintf (file, "hi"); break;
+	case GEU: fprintf (file, "nc");  break;
+	default:
+	  output_operand_lossage ("fr30_print_operand: unrecognised %b code");
+	  break;
+	}
+      return;
+      
+    case 'B':
+      /* Convert GCC's comparison operators into the complimentary FR30
+	 comparison codes.  */
+      switch (GET_CODE (x))
+	{
+	case EQ:  fprintf (file, "ne"); break;
+	case NE:  fprintf (file, "eq"); break;
+	case LT:  fprintf (file, "ge"); break;
+	case LE:  fprintf (file, "gt"); break;
+	case GT:  fprintf (file, "le"); break;
+	case GE:  fprintf (file, "lt"); break;
+	case LTU: fprintf (file, "nc"); break;
+	case LEU: fprintf (file, "hi"); break;
+	case GTU: fprintf (file, "ls"); break;
+	case GEU: fprintf (file, "c"); break;
+	default:
+	  output_operand_lossage ("fr30_print_operand: unrecognised %B code");
+	  break;
+	}
+      return;
+
+    case 'A':
+      /* Print a signed byte value as an unsigned value.  */
+      if (GET_CODE (x) != CONST_INT)
+	output_operand_lossage ("fr30_print_operand: invalid operand to %A code");
+      else
+	{
+	  HOST_WIDE_INT val;
+	  
+	  val = INTVAL (x);
+
+	  val &= 0xff;
+
+	  fprintf (file, "%d", val);
+	}
+      return;
+      
+    case 'x':
+      if (GET_CODE (x) != CONST_INT
+	  || INTVAL (x) < 16
+	  || INTVAL (x) > 32)
+	output_operand_lossage ("fr30_print_operand: invalid %x code");
+      else
+	fprintf (file, "%d", INTVAL (x) - 16);
+      return;
+
+    case 'F':
+      if (GET_CODE (x) != CONST_DOUBLE)
+	output_operand_lossage ("fr30_print_operand: invalid %F code");
+      else
+	{
+	  REAL_VALUE_TYPE d;
+
+	  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
+	  fprintf (file, "%.8f", d);
+	}
+      return;
+      
+    case 0:
+      /* Handled below.  */
+      break;
+      
+    default:
+      fprintf (stderr, "unknown code = %x\n", code);
+      output_operand_lossage ("fr30_print_operand: unknown code");
+      return;
+    }
+
+  switch (GET_CODE (x))
+    {
+    case REG:
+      fputs (reg_names [REGNO (x)], file);
+      break;
+
+    case MEM:
+      x0 = XEXP (x,0);
+      
+      switch (GET_CODE (x0))
+	{
+	case REG:
+	  if (REGNO (x0) >= (sizeof (reg_names) / sizeof (reg_names[0])))
+	    abort ();
+	  fprintf (file, "@%s", reg_names [REGNO (x0)]);
+	  break;
+
+	case PLUS:
+	  if (GET_CODE (XEXP (x0, 0)) != REG
+	      || REGNO (XEXP (x0, 0)) < FRAME_POINTER_REGNUM
+	      || REGNO (XEXP (x0, 0)) > STACK_POINTER_REGNUM
+	      || GET_CODE (XEXP (x0, 1)) != CONST_INT)
+	    {
+	      fprintf (stderr, "bad INDEXed address:");
+	      debug_rtx (x);
+	      output_operand_lossage ("fr30_print_operand: unhandled MEM");
+	    }
+	  else if (REGNO (XEXP (x0, 0)) == FRAME_POINTER_REGNUM)
+	    {
+	      HOST_WIDE_INT val = INTVAL (XEXP (x0, 1));
+	      if (val < -(1 << 9) || val > ((1 << 9) - 4))
+		{
+		  fprintf (stderr, "frame INDEX out of range:");
+		  debug_rtx (x);
+		  output_operand_lossage ("fr30_print_operand: unhandled MEM");
+		}
+	      fprintf (file, "@(r14, #%d)", val);
+	    }
+	  else
+	    {
+	      HOST_WIDE_INT val = INTVAL (XEXP (x0, 1));
+	      if (val < 0 || val > ((1 << 6) - 4))
+		{
+		  fprintf (stderr, "stack INDEX out of range:");
+		  debug_rtx (x);
+		  output_operand_lossage ("fr30_print_operand: unhandled MEM");
+		}
+	      fprintf (file, "@(r15, #%d)", val);
+	    }
+	  break;
+	  
+	case SYMBOL_REF:
+	  output_address (x0);
+	  break;
+	  
+	default:
+	  fprintf (stderr, "bad MEM code = %x\n", GET_CODE (x0));
+	  debug_rtx (x);
+	  output_operand_lossage ("fr30_print_operand: unhandled MEM");
+	  break;
+	}
+      break;
+      
+    case CONST_DOUBLE :
+      /* We handle SFmode constants here as output_addr_const doesn't.  */
+      if (GET_MODE (x) == SFmode)
+	{
+	  REAL_VALUE_TYPE d;
+	  long l;
+
+	  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
+	  REAL_VALUE_TO_TARGET_SINGLE (d, l);
+	  fprintf (file, "0x%08lx", l);
+	  break;
+	}
+
+      /* Fall through.  Let output_addr_const deal with it.  */
+    default:
+      output_addr_const (file, x);
+      break;
+    }
+
+  return;
+}
+
+/*}}}*/
+/*{{{  Function arguments */ 
+
+/* Compute the number of word sized registers needed to hold a
+   function argument of mode INT_MODE and tree type TYPE.  */
+int
+fr30_num_arg_regs (int_mode, type)
+     int int_mode;
+     tree type;
+{
+  enum machine_mode mode = (enum machine_mode) int_mode;
+  int size;
+
+  if (MUST_PASS_IN_STACK (mode, type))
+    return 0;
+
+  if (type && mode == BLKmode)
+    size = int_size_in_bytes (type);
+  else
+    size = GET_MODE_SIZE (mode);
+
+  return (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+}
+
+/* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
+   Returns the number of argument registers required to hold *part* of
+   a parameter of machine mode MODE and tree type TYPE (which may be
+   NULL if the type is not known).  If the argument fits entirly in
+   the argument registers, or entirely on the stack, then 0 is returned.
+   CUM is the number of argument registers already used by earlier
+   parameters to the function.  */
+
+int
+fr30_function_arg_partial_nregs (cum, int_mode, type, named)
+     CUMULATIVE_ARGS cum;
+     int int_mode;
+     tree type;
+     int named;
+{
+  /* Unnamed arguments, ie those that are prototyped as ...
+     are always passed on the stack.
+     Also check here to see if all the argument registers are full.  */
+  if (named == 0 || cum >= FR30_NUM_ARG_REGS)
+    return 0;
+
+  /* Work out how many argument registers would be needed if this
+     parameter were to be passed entirely in registers.  If there
+     are sufficient argument registers available (or if no registers
+     are needed because the parameter must be passed on the stack)
+     then return zero, as this parameter does not require partial
+     register, partial stack stack space.  */
+  if (cum + fr30_num_arg_regs (int_mode, type) <= FR30_NUM_ARG_REGS)
+    return 0;
+  
+  /* Otherwise return the number of registers that would be used.  */
+  return FR30_NUM_ARG_REGS - cum;
+}
+
+static rtx
+fr30_pass_by_reference (valist, type)
+     tree valist;
+     tree type;
+{
+  tree type_ptr;
+  tree type_ptr_ptr;
+  tree t;
+  
+  type_ptr     = build_pointer_type (type);
+  type_ptr_ptr = build_pointer_type (type_ptr);
+  
+  t = build (POSTINCREMENT_EXPR, va_list_type_node, valist, build_int_2 (UNITS_PER_WORD, 0));
+  TREE_SIDE_EFFECTS (t) = 1;
+  t = build1 (NOP_EXPR, type_ptr_ptr, t);
+  TREE_SIDE_EFFECTS (t) = 1;
+  t = build1 (INDIRECT_REF, type_ptr, t);
+  
+  return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
+}
+
+static rtx
+fr30_pass_by_value (valist, type)
+     tree valist;
+     tree type;
+{
+  HOST_WIDE_INT size = int_size_in_bytes (type);
+  HOST_WIDE_INT rsize;
+  rtx addr_rtx;
+  tree t;
+
+  if ((size % UNITS_PER_WORD) == 0)
+    {
+      t = build (POSTINCREMENT_EXPR, va_list_type_node, valist, build_int_2 (size, 0));
+      TREE_SIDE_EFFECTS (t) = 1;
+      
+      return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
+    }
+
+  rsize = (size + UNITS_PER_WORD - 1) & - UNITS_PER_WORD;
+      
+  /* Care for bigendian correction on the aligned address.  */
+  t = build (PLUS_EXPR, ptr_type_node, valist, build_int_2 (rsize - size, 0));
+  addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
+  addr_rtx = copy_to_reg (addr_rtx);
+      
+  /* Increment AP.  */
+  t = build (PLUS_EXPR, va_list_type_node, valist, build_int_2 (rsize, 0));
+  t = build (MODIFY_EXPR, va_list_type_node, valist, t);
+  TREE_SIDE_EFFECTS (t) = 1;
+  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+  
+  return addr_rtx;
+}
+
+/* Implement `va_arg'.  */
+
+rtx
+fr30_va_arg (valist, type)
+     tree valist;
+     tree type;
+{
+  HOST_WIDE_INT size;
+  
+  if (AGGREGATE_TYPE_P (type))
+    return fr30_pass_by_reference (valist, type);
+  
+  size = int_size_in_bytes (type);
+
+  if ((size % sizeof (int)) == 0
+      || size < 4)
+    return fr30_pass_by_value (valist, type);
+
+  return fr30_pass_by_reference (valist, type);
+}
+
+/*}}}*/
+/*{{{  Operand predicates */ 
+
+/* Returns true if OPERAND is an integer value suitable for use in
+   an ADDSP instruction.  */
+int
+stack_add_operand (operand, mode)
+     rtx operand;
+     Mmode mode ATTRIBUTE_UNUSED;
+{
+  return
+    (GET_CODE (operand) == CONST_INT
+     && INTVAL (operand) >= -512
+     && INTVAL (operand) <=  508
+     && ((INTVAL (operand) & 3) == 0));
+}
+
+/* Returns true if OPERAND is an integer value suitable for use in
+   an ADD por ADD2 instruction, or if it is a register.  */
+int
+add_immediate_operand (operand, mode)
+     rtx operand;
+     Mmode mode ATTRIBUTE_UNUSED;
+{
+  return
+    (GET_CODE (operand) == REG
+     || (GET_CODE (operand) == CONST_INT
+	 && INTVAL (operand) >= -16
+	 && INTVAL (operand) <=  15));
+}
+
+/* Returns true if OPERAND is hard register in the range 8 - 15.  */
+int
+high_register_operand (operand, mode)
+     rtx operand;
+     Mmode mode ATTRIBUTE_UNUSED;
+{
+  return
+    (GET_CODE (operand) == REG
+     && REGNO (operand) <= 15
+     && REGNO (operand) >= 8);
+}
+
+/* Returns true if OPERAND is hard register in the range 0 - 7.  */
+int
+low_register_operand (operand, mode)
+     rtx operand;
+     Mmode mode ATTRIBUTE_UNUSED;
+{
+  return
+    (GET_CODE (operand) == REG
+     && REGNO (operand) <= 7
+     && REGNO (operand) >= 0);
+}
+
+/* Returns true if OPERAND is suitable for use in a CALL insn.  */
+int
+call_operand (operand, mode)
+     rtx operand;
+     Mmode mode;
+{
+  return nonimmediate_operand (operand, mode)
+    || (GET_CODE (operand) == MEM
+	&& GET_CODE (XEXP (operand, 0)) == SYMBOL_REF);
+}
+
+/* Returns true iff all the registers in the operands array
+   are in descending or ascending order.  */
+int
+fr30_check_multiple_regs (operands, num_operands, descending)
+     rtx * operands;
+     int   num_operands;
+     int   descending;
+{
+  if (descending)
+    {
+      int prev_regno = -1;
+      
+      while (num_operands--)
+	{
+	  if (GET_CODE (operands [num_operands]) != REG)
+	    return 0;
+	  
+	  if (REGNO (operands [num_operands]) < prev_regno)
+	    return 0;
+	  
+	  prev_regno = REGNO (operands [num_operands]);
+	}
+    }
+  else
+    {
+      int prev_regno = CONDITION_CODE_REGNUM;
+      
+      while (num_operands--)
+	{
+	  if (GET_CODE (operands [num_operands]) != REG)
+	    return 0;
+	  
+	  if (REGNO (operands [num_operands]) > prev_regno)
+	    return 0;
+	  
+	  prev_regno = REGNO (operands [num_operands]);
+	}
+    }
+
+  return 1;
+}
+
+/*}}}*/
+
+/* Local Variables: */
+/* folded-file: t   */
+/* End:		    */
+

gcc/config/fr30/fr30.md

+;;{{{ Comment 
+
+;; FR30 machine description.
+;; Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+;; Contributed by Cygnus Solutions.
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;;}}} 
+;;{{{ Attributes 
+
+(define_attr "length" "" (const_int 2))
+
+;; Used to distinguish between small memory model targets and big mode targets.
+
+(define_attr "size" "small,big"
+  (const (if_then_else (symbol_ref "TARGET_SMALL_MODEL")
+		       (const_string "small")
+		       (const_string "big"))))
+
+
+;; Define an attribute to be used by the delay slot code.
+;; An instruction by default is considered to be 'delyabable'
+;; that is, it can be placed into a delay slot, but it is not
+;; itself an delyaed branch type instruction.  An instruction
+;; whoes type is 'delayed' is one which has a delay slot, and
+;; an instruction whoes delay_type is 'other' is one which does
+;; not have a delay slot, nor can it be placed into a delay slot.
+
+(define_attr "delay_type" "delayable,delayed,other" (const_string "delayable"))
+
+;;}}} 
+;;{{{ Delay Slot Specifications 
+
+(define_delay (eq_attr "delay_type" "delayed")
+  [(and (eq_attr "delay_type" "delayable")
+	(eq_attr "length" "2"))
+   (nil)
+   (nil)]
+)
+
+;;}}}
+;;{{{ Moves 
+
+;;{{{ Comment 
+
+;; Wrap moves in define_expand to prevent memory->memory moves from being
+;; generated at the RTL level, which generates better code for most machines
+;; which can't do mem->mem moves.
+
+;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
+;; than M, the effect of this instruction is to store the specified value in
+;; the part of the register that corresponds to mode M.  The effect on the rest
+;; of the register is undefined.
+
+;; This class of patterns is special in several ways.  First of all, each of
+;; these names *must* be defined, because there is no other way to copy a datum
+;; from one place to another.
+
+;; Second, these patterns are not used solely in the RTL generation pass.  Even
+;; the reload pass can generate move insns to copy values from stack slots into
+;; temporary registers.  When it does so, one of the operands is a hard
+;; register and the other is an operand that can need to be reloaded into a
+;; register.
+
+;; Therefore, when given such a pair of operands, the pattern must
+;; generate RTL which needs no reloading and needs no temporary
+;; registers--no registers other than the operands.  For example, if
+;; you support the pattern with a `define_expand', then in such a
+;; case the `define_expand' mustn't call `force_reg' or any other such
+;; function which might generate new pseudo registers.
+
+;; This requirement exists even for subword modes on a RISC machine
+;; where fetching those modes from memory normally requires several
+;; insns and some temporary registers.  Look in `spur.md' to see how
+;; the requirement can be satisfied.
+
+;; During reload a memory reference with an invalid address may be passed as an
+;; operand.  Such an address will be replaced with a valid address later in the
+;; reload pass.  In this case, nothing may be done with the address except to
+;; use it as it stands.  If it is copied, it will not be replaced with a valid
+;; address.  No attempt should be made to make such an address into a valid
+;; address and no routine (such as `change_address') that will do so may be
+;; called.  Note that `general_operand' will fail when applied to such an
+;; address.
+;;
+;; The global variable `reload_in_progress' (which must be explicitly declared
+;; if required) can be used to determine whether such special handling is
+;; required.
+;;
+;; The variety of operands that have reloads depends on the rest of
+;; the machine description, but typically on a RISC machine these can
+;; only be pseudo registers that did not get hard registers, while on
+;; other machines explicit memory references will get optional
+;; reloads.
+;;
+;; If a scratch register is required to move an object to or from memory, it
+;; can be allocated using `gen_reg_rtx' prior to reload.  But this is
+;; impossible during and after reload.  If there are cases needing scratch
+;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
+;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
+;; patterns `reload_inM' or `reload_outM' to handle them.
+
+;; The constraints on a `moveM' must permit moving any hard register to any
+;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
+;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
+;; value of 2.
+
+;; It is obligatory to support floating point `moveM' instructions
+;; into and out of any registers that can hold fixed point values,
+;; because unions and structures (which have modes `SImode' or
+;; `DImode') can be in those registers and they may have floating
+;; point members.
+
+;; There may also be a need to support fixed point `moveM' instructions in and
+;; out of floating point registers.  Unfortunately, I have forgotten why this
+;; was so, and I don't know whether it is still true.  If `HARD_REGNO_MODE_OK'
+;; rejects fixed point values in floating point registers, then the constraints
+;; of the fixed point `moveM' instructions must be designed to avoid ever
+;; trying to reload into a floating point register.
+
+;;}}}
+;;{{{ Push and Pop  
+
+;; Push a register onto the stack
+(define_insn "movsi_push"
+  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "register_operand" "a"))]
+  ""
+  "st	%0, @-r15"
+)
+
+;; Pop a register off the stack
+(define_insn "movsi_pop"
+  [(set:SI (match_operand:SI 0 "register_operand" "a")
+	(mem:SI (post_inc:SI (reg:SI 15))))]
+  ""
+  "ld	@r15+, %0"
+)
+
+;;}}}
+;;{{{ 1 Byte Moves 
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (!reload_in_progress
+      && !reload_completed
+      && GET_CODE (operands[0]) == MEM
+      && (GET_CODE (operands[1]) == MEM
+         || immediate_operand (operands[1], QImode)))
+    operands[1] = copy_to_mode_reg (QImode, operands[1]);
+}")
+
+(define_insn "movqi_unsigned_register_load"
+  [(set (match_operand:SI 0 "register_operand"              "=r")
+	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+  ""
+  "ldub	%1, %0"
+)
+
+(define_expand "movqi_signed_register_load"
+  [(set (match_operand:SI 0 "register_operand"               "")
+	(sign_extend:SI (match_operand:QI 1 "memory_operand" "")))]
+  ""
+  "
+  emit_insn (gen_movqi_unsigned_register_load (operands[0], operands[1]));
+  emit_insn (gen_extendqisi2 (operands[0], operands[0]));
+  DONE;
+  "
+)
+
+(define_insn "*movqi_internal"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,red,m,r")
+	(match_operand:QI 1 "general_operand"       "i,red,r,rm"))]
+  ""
+  "@
+   ldi:8\\t#%A1, %0
+   mov  \\t%1, %0
+   stb  \\t%1, %0
+   ldub \\t%1, %0"
+)
+
+;;}}}
+;;{{{ 2 Byte Moves 
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (!reload_in_progress
+      && !reload_completed
+      && GET_CODE (operands[0]) == MEM
+      && (GET_CODE (operands[1]) == MEM
+	 || immediate_operand (operands[1], HImode)))
+    operands[1] = copy_to_mode_reg (HImode, operands[1]);
+}")
+
+(define_insn "movhi_unsigned_register_load"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
+  ""
+  "lduh	%1, %0"
+)
+
+(define_expand "movhi_signed_register_load"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI (match_operand:HI 1 "memory_operand" "")))]
+  ""
+  "
+  emit_insn (gen_movhi_unsigned_register_load (operands[0], operands[1]));
+  emit_insn (gen_extendhisi2 (operands[0], operands[0]));
+  DONE;
+  "
+)
+
+(define_insn "*movhi_internal"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,red,m,r")
+	(match_operand:HI 1 "general_operand"       "L,M,n,red,r,rm"))]
+  ""
+  "@
+   ldi:8 \\t#%1, %0
+   ldi:20\\t#%1, %0
+   ldi:32\\t#%1, %0
+   mov   \\t%1, %0
+   sth   \\t%1, %0
+   lduh  \\t%1, %0"
+  [(set_attr "length" "*,4,6,*,*,*")]
+)
+
+;;}}}
+;;{{{ 4 Byte Moves 
+
+;; If the destination is a MEM and the source is a
+;; MEM or an CONST_INT move the source into a register.
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+  "{
+  if (!reload_in_progress
+      && !reload_completed
+      && GET_CODE(operands[0]) == MEM
+      && (GET_CODE (operands[1]) == MEM
+	  || immediate_operand (operands[1], SImode)))
+     operands[1] = copy_to_mode_reg (SImode, operands[1]);
+  }"
+)
+
+;; We can do some clever tricks when loading certain immediate
+;; values.  We implement these tricks as define_splits, rather
+;; than putting the code into the define_expand "movsi" above,
+;; because if we put them there, they will be evaluated at RTL
+;; generation time and then the combiner pass will come along
+;; and replace the multiple insns that have been generated with
+;; the original, slower, load insns.  (The combiner pass only
+;; cares about reducing the number of instructions, it does not
+;; care about instruction lengths or speeds).  Splits are
+;; evaluated after the combine pass and before the scheduling
+;; passes, so that they are the perfect place to put this
+;; intelligence.
+;;
+;; XXX we probably ought to implement these for QI and HI mode
+;; loads as well.
+
+;; If we are loading a small negative constant we can save space
+;; and time by loading the positive value and then sign extending it.
+(define_split
+  [(set (match_operand:SI 0 "register_operand"  "r")
+	(match_operand:SI 1 "immediate_operand" "i"))]
+   "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128"
+   [(set:SI (match_dup 0) (match_dup 2))
+    (set:SI (match_dup 0) (sign_extend:SI (subreg:QI (match_dup 0) 0)))]
+   "{
+   operands[2] = GEN_INT (INTVAL (operands[1]) & 0xff);
+   }"
+)
+
+;; If we are loading a large negative constant, one which does
+;; not have any of its bottom 24 bit set, then we can save time
+;; and space by loading the byte value and shifting it into place.
+(define_split
+  [(set (match_operand:SI 0 "register_operand"  "r")
+	(match_operand:SI 1 "immediate_operand" "i"))]
+   "(INTVAL (operands[1]) < 0) && (INTVAL (operands[1]) & 0x00ffffff == 0)"
+   [(set:SI (match_dup 0) (match_dup 2))
+    (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
+	       (clobber (reg:CC 16))])]
+   "{
+   HOST_WIDE_INT val = INTVAL (operands[1]);
+   operands[2] = GEN_INT (val >> 24);
+   }"
+)
+
+;; If we are loading a large positive constant, one which has bits
+;; in the top byte set, but whoes set bits all lie within an 8 bit
+;; range, then we can save time and space by loading the byte value
+;; and shifting it into place.
+(define_split
+  [(set (match_operand:SI 0 "register_operand"  "r")
+	(match_operand:SI 1 "immediate_operand" "i"))]
+   "(INTVAL (operands[1]) > 0x00ffffff)
+   && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)"
+   [(set:SI (match_dup 0) (match_dup 2))
+    (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
+	       (clobber (reg:CC 16))])]
+   "{
+   HOST_WIDE_INT val = INTVAL (operands[1]);
+   int shift = exact_log2 (val & ( - val));
+   operands[2] = GEN_INT (val >> shift);
+   operands[3] = GEN_INT (shift);
+   }"
+)
+
+;; When TARGET_SMALL_MODEL is defined we assume that all symbolic
+;; values are addresses which will fit in 20 bits.
+
+(define_insn "movsi_internal"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,m,r")
+	(match_operand:SI 1 "general_operand"       "L,M,n,i,rde,r,rm"))]
+  ""
+  "*
+  {
+    switch (which_alternative)
+    {
+    case 0: return   \"ldi:8 \\t#%1, %0\";
+    case 1: return   \"ldi:20\\t#%1, %0\";
+    case 2: return   \"ldi:32\\t#%1, %0\";
+    case 3: if (TARGET_SMALL_MODEL)
+	      return \"ldi:20\\t%1, %0\";
+            else
+	      return \"ldi:32\\t%1, %0\";
+    case 4: return   \"mov   \\t%1, %0\";
+    case 5: return   \"st    \\t%1, %0\";
+    case 6: return   \"ld    \\t%1, %0\";
+    default: abort ();	       
+    }
+  }"
+  [(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 4)
+			       (eq_attr "alternative" "2") (const_int 6)
+			       (eq_attr "alternative" "3") 
+			                (if_then_else (eq_attr "size" "small")
+						      (const_int 4)
+						      (const_int 6))]
+			      (const_int 2)))]
+)
+
+;;}}}
+;;{{{ Load & Store Multiple Registers 
+
+;; The load multiple and store multiple patterns are implemented
+;; as peepholes because the only time they are expected to occur
+;; is during function prologues and epilogues.
+
+(define_peephole
+  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+	   (match_operand:SI 0 "high_register_operand" "h"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 1 "high_register_operand" "h"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 2 "high_register_operand" "h"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 3 "high_register_operand" "h"))]
+  "fr30_check_multiple_regs (operands, 4, 1)"
+  "stm1	(%0, %1, %2, %3)"
+  [(set_attr "delay_type" "other")]
+)
+
+(define_peephole
+  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+	   (match_operand:SI 0 "high_register_operand" "h"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 1 "high_register_operand" "h"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 2 "high_register_operand" "h"))]
+  "fr30_check_multiple_regs (operands, 3, 1)"
+  "stm1	(%0, %1, %2)"
+  [(set_attr "delay_type" "other")]
+)
+
+(define_peephole
+  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+	   (match_operand:SI 0 "high_register_operand" "h"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 1 "high_register_operand" "h"))]
+  "fr30_check_multiple_regs (operands, 2, 1)"
+  "stm1	(%0, %1)"
+  [(set_attr "delay_type" "other")]
+)
+
+(define_peephole
+  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))
+   (set:SI (match_operand:SI 1 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))
+   (set:SI (match_operand:SI 2 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))
+   (set:SI (match_operand:SI 3 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))]
+  "fr30_check_multiple_regs (operands, 4, 0)"
+  "ldm1	(%0, %1, %2, %3)"
+  [(set_attr "delay_type" "other")]
+)
+
+(define_peephole
+  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))
+   (set:SI (match_operand:SI 1 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))
+   (set:SI (match_operand:SI 2 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))]
+  "fr30_check_multiple_regs (operands, 3, 0)"
+  "ldm1	(%0, %1, %2)"
+  [(set_attr "delay_type" "other")]
+)
+
+(define_peephole
+  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))
+   (set:SI (match_operand:SI 1 "high_register_operand" "h")
+           (mem:SI (post_inc:SI (reg:SI 15))))]
+  "fr30_check_multiple_regs (operands, 2, 0)"
+  "ldm1	(%0, %1)"
+  [(set_attr "delay_type" "other")]
+)
+
+(define_peephole
+  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+	   (match_operand:SI 0 "low_register_operand" "l"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 1 "low_register_operand" "l"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 2 "low_register_operand" "l"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 3 "low_register_operand" "l"))]
+  "fr30_check_multiple_regs (operands, 4, 1)"
+  "stm0	(%0, %1, %2, %3)"
+  [(set_attr "delay_type" "other")]
+)
+
+(define_peephole
+  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+	   (match_operand:SI 0 "low_register_operand" "l"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 1 "low_register_operand" "l"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 2 "low_register_operand" "l"))]
+  "fr30_check_multiple_regs (operands, 3, 1)"
+  "stm0	(%0, %1, %2)"
+  [(set_attr "delay_type" "other")]
+)
+
+(define_peephole
+  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+	   (match_operand:SI 0 "low_register_operand" "l"))
+   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+           (match_operand:SI 1 "low_register_operand" "l"))]
+  "fr30_check_multiple_regs (operands, 2, 1)"
+  "stm0	(%0, %1)"
+  [(set_attr "delay_type" "other")]
+)
+
+;;}}}
+;;{{{ Floating Point Moves 
+
+;; Note - Patterns for SF mode moves are compulsory, but
+;; patterns for DF are optional, as GCC can synthesise them.
+
+(define_expand "movsf"
+  [(set (match_operand:SF 0 "general_operand" "")
+	(match_operand:SF 1 "general_operand" ""))]
+  ""
+  "{
+  if (!reload_in_progress && !reload_completed
+      && memory_operand (operands[0], SFmode)
+      && memory_operand (operands[1], SFmode))
+    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
+  }"
+)
+
+(define_insn "*movsf_internal"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,red,m,r")
+	(match_operand:SF 1 "general_operand"      "Fn,i,rde,r,rm"))]
+  ""
+  "*
+  {
+    switch (which_alternative)
+    {
+    case 0: return   \"ldi:32\\t%1, %0\";
+    case 1: if (TARGET_SMALL_MODEL)
+	      return \"ldi:20\\t%1, %0\";
+            else
+	      return \"ldi:32\\t%1, %0\";
+    case 2: return   \"mov   \\t%1, %0\";
+    case 3: return   \"st    \\t%1, %0\";
+    case 4: return   \"ld    \\t%1, %0\";
+    default: abort ();	       
+    }
+  }"
+  [(set (attr "length") (cond [(eq_attr "alternative" "0") (const_int 6)
+			       (eq_attr "alternative" "1") 
+			                (if_then_else (eq_attr "size" "small")
+						      (const_int 4)
+						      (const_int 6))]
+			      (const_int 2)))]
+)
+
+(define_insn "*movsf_constant_store"
+  [(set (match_operand:SF 0 "memory_operand"    "m")
+	(match_operand:SF 1 "immediate_operand" "F"))]
+  ""
+  "*
+  {
+  char *         ldi_instr;
+  char *          tmp_reg;
+  static char     buffer[100];
+  REAL_VALUE_TYPE d;
+
+  REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
+  
+  if (REAL_VALUES_EQUAL (d, dconst0))
+    ldi_instr = \"ldi:8\";
+  else
+    ldi_instr = \"ldi:32\";
+
+  tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
+  
+  sprintf (buffer, \"%s\\t#%%1, %s\\t;\\n\\tst\\t%s, %%0\\t; Created by movsf_constant_store\",
+    ldi_instr, tmp_reg, tmp_reg);
+
+  return buffer;
+  }"
+  [(set_attr "length" "8")]
+)
+
+;;}}}
+
+;;}}} 
+;;{{{ Conversions 
+
+;; Signed conversions from a smaller integer to a larger integer
+
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand"                "=r")
+	(sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
+  ""
+  "extsb	%0"
+)
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand"                "=r")
+	(sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
+  ""
+  "extsh	%0"
+)
+
+;; Unsigned conversions from a smaller integer to a larger integer
+
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand"                "=r")
+	(zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
+  ""
+  "extub	%0"
+)
+
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand"                "=r")
+	(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
+  ""
+  "extuh	%0"
+)
+
+;;}}} 
+;;{{{ Arithmetic 
+
+;;{{{ Addition 
+
+;; This is a special pattern just for adjusting the stack size.
+(define_insn "add_to_stack"
+  [(set (reg:SI 15)
+	(plus:SI (reg:SI 15)
+		 (match_operand:SI 0 "stack_add_operand" "i")))]
+  ""
+  "addsp	%0"
+)
+
+;; We need some trickery to be able to handle the addition of
+;; large (ie outside +/- 16) constants.  We need to be able to
+;; handle this because reload assumes that it can generate add
+;; instructions with arbitary sized constants.
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "register_operand"           "")
+	(plus:SI (match_operand:SI 1 "register_operand"  "")
+		 (match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "{
+  if (   GET_CODE (operands[2]) == REG
+      || GET_CODE (operands[2]) == SUBREG)
+    emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
+  else if (GET_CODE (operands[2]) != CONST_INT)
+    emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
+  else if ((INTVAL (operands[2]) >= -16) && (INTVAL (operands[2]) <= 15))
+    emit_insn (gen_addsi_small_int (operands[0], operands[1], operands[2]));
+  else
+    emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
+  DONE;
+  }"
+)
+
+(define_insn "addsi_regs"
+  [(set (match_operand:SI 0 "register_operand"          "=r")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0")
+		 (match_operand:SI 2 "register_operand"  "r")))]
+  ""
+  "addn	%2, %0"
+)
+
+(define_insn "addsi_small_int"
+  [(set (match_operand:SI 0 "register_operand"              "=r,r")
+	(plus:SI (match_operand:SI 1 "register_operand"      "0,0")
+		 (match_operand:SI 2 "add_immediate_operand" "I,J")))]
+  ""
+  "@
+   addn	%2, %0
+   addn2	%2, %0"
+)
+
+(define_expand "addsi_big_int"
+  [(set (match_operand:SI 0 "register_operand"           "")
+	(plus:SI (match_operand:SI 1 "register_operand"  "")
+		 (match_operand:SI 2 "immediate_operand" "")))]
+  ""
+  "{
+  /* Cope with the possibility that ops 0 and 1 are the same register.  */
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    {
+      if (reload_in_progress || reload_completed)
+        {
+	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
+	  
+	  emit_insn (gen_movsi (reg, operands[2]));
+	  emit_insn (gen_addsi_regs (operands[0], operands[0], reg));
+	}
+      else
+	{
+	  operands[2] = force_reg (SImode, operands[2]);
+	  emit_insn (gen_addsi_regs (operands[0], operands[0], operands[2]));
+	}
+    }
+  else
+    {
+      emit_insn (gen_movsi (operands[0], operands[2]));
+      emit_insn (gen_addsi_regs (operands[0], operands[0], operands[1]));
+    }
+  DONE;
+  }"
+)
+
+(define_insn "*addsi_for_reload"
+  [(set (match_operand:SI 0 "register_operand"         "=&r,r,r")
+	(plus:SI (match_operand:SI 1 "register_operand"  "r,r,r")
+		 (match_operand:SI 2 "immediate_operand" "L,M,n")))]
+  "reload_in_progress || reload_completed"
+  "@
+  ldi:8\\t#%2, %0  \\n\\taddn\\t%1, %0
+  ldi:20\\t#%2, %0 \\n\\taddn\\t%1, %0
+  ldi:32\\t#%2, %0 \\n\\taddn\\t%1, %0"
+  [(set_attr "length" "4,6,8")]
+)
+
+;;}}}
+;;{{{ Subtraction 
+
+(define_insn "subsi3"
+  [(set (match_operand:SI 0 "register_operand"       "=r")
+	(minus (match_operand:SI 1 "register_operand" "0")
+	       (match_operand:SI 2 "register_operand" "r")))]
+  ""
+  "subn	%2, %0"
+)
+
+;;}}}
+;;{{{ Multiplication 
+
+;; Signed multiplication producing 64 bit results from 32 bit inputs
+(define_insn "mulsidi3"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	   (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
+		    (sign_extend:DI (match_operand:SI 2 "register_operand"  "r"))))
+   (clobber (reg:CC 16))]
+  ""
+  "mul	%2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
+  [(set_attr "length" "6")]
+)
+
+;; Unsigned multiplication producing 64 bit results from 32 bit inputs
+(define_insn "umulsidi3"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
+		    (zero_extend:DI (match_operand:SI 2 "register_operand"  "r"))))
+   (clobber (reg:CC 16))]
+  ""
+  "mulu	%2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
+  [(set_attr "length" "6")]
+)
+
+;; Signed multiplication producing 32 bit result from 16 bit inputs
+(define_insn "mulhisi3"
+  [(set (match_operand:SI 0 "register_operand"                             "=r")
+	   (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
+		    (sign_extend:SI (match_operand:HI 2 "register_operand"  "r"))))
+   (clobber (reg:CC 16))]
+  ""
+  "mulh	%2, %1\\n\\tmov\\tmdl, %0"
+  [(set_attr "length" "4")]
+)
+
+;; Unsigned multiplication producing 32 bit result from 16 bit inputs
+(define_insn "umulhisi3"
+  [(set (match_operand:SI 0 "register_operand"                             "=r")
+	   (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r"))
+		    (zero_extend:SI (match_operand:HI 2 "register_operand"  "r"))))
+   (clobber (reg:CC 16))]
+  ""
+  "muluh	%2, %1\\n\\tmov\\tmdl, %0"
+  [(set_attr "length" "4")]
+)
+
+;; Signed multiplication producing 32 bit result from 32 bit inputs
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "register_operand"             "=r")
+	   (mult:SI (match_operand:SI 1 "register_operand" "%r")
+		    (match_operand:SI 2 "register_operand"  "r")))
+   (clobber (reg:CC 16))]
+  ""
+  "mul	%2, %1\\n\\tmov\\tmdl, %0"
+  [(set_attr "length" "4")]
+)
+
+;;}}}
+;;{{{ Negation 
+
+(define_expand "negsi2"
+  [(set (match_operand:SI 0 "register_operand"         "")
+	(neg:SI (match_operand:SI 1 "register_operand" "")))]
+  ""
+  "{
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    {
+      if (reload_in_progress || reload_completed)
+        {
+	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
+	  
+	  emit_insn (gen_movsi (reg, GEN_INT (0)));
+	  emit_insn (gen_subsi3 (reg, reg, operands[0]));
+	  emit_insn (gen_movsi (operands[0], reg));
+	}
+      else
+	{
+	  rtx reg = gen_reg_rtx (SImode);
+	
+	  emit_insn (gen_movsi (reg, GEN_INT (0)));
+	  emit_insn (gen_subsi3 (reg, reg, operands[0]));
+	  emit_insn (gen_movsi (operands[0], reg));
+	}
+    }
+  else
+    {
+      emit_insn (gen_movsi_internal (operands[0], GEN_INT (0)));
+      emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
+    }
+  DONE;
+  }"
+)
+
+;;}}}
+
+;;}}} 
+;;{{{ Shifts 
+
+;; Arithmetic Shift Left
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand"            "=r,r,r")
+	(ashift:SI (match_operand:SI 1 "register_operand"  "0,0,0")
+		   (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
+   (clobber (reg:CC 16))]
+  ""
+  "@
+  lsl	%2, %0
+  lsl	%2, %0
+  lsl2	%x2, %0"
+)
+
+;; Arithmetic Shift Right
+(define_insn "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand"              "=r,r,r")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,0")
+		     (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
+   (clobber (reg:CC 16))]
+  ""
+  "@
+  asr	%2, %0
+  asr	%2, %0
+  asr2	%x2, %0"
+)
+
+;; Logical Shift Right
+(define_insn "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand"              "=r,r,r")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,0")
+		     (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
+   (clobber (reg:CC 16))]
+  ""
+  "@
+  lsr	%2, %0
+  lsr	%2, %0
+  lsr2	%x2, %0"
+)
+
+;;}}} 
+;;{{{ Logical Operations 
+
+;; Logical AND, 32 bit integers
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "register_operand"         "=r")
+	(and:SI (match_operand:SI 1 "register_operand" "%r")
+		(match_operand:SI 2 "register_operand"  "0")))
+   (clobber (reg:CC 16))]
+  ""
+  "and	%1, %0"
+)
+
+;; Inclusive OR, 32 bit integers
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "register_operand"         "=r")
+	(ior:SI (match_operand:SI 1 "register_operand" "%r")
+		(match_operand:SI 2 "register_operand"  "0")))
+   (clobber (reg:CC 16))]
+  ""
+  "or	%1, %0"
+)
+
+;; Exclusive OR, 32 bit integers
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "register_operand"         "=r")
+	(xor:SI (match_operand:SI 1 "register_operand" "%r")
+		(match_operand:SI 2 "register_operand"  "0")))
+   (clobber (reg:CC 16))]
+  ""
+  "eor	%1, %0"
+)
+
+;; One's complement, 32 bit integers
+(define_expand "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand"         "")
+	(not:SI (match_operand:SI 1 "register_operand" "")))]
+  ""
+  "{
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    {
+      if (reload_in_progress || reload_completed)
+        {
+	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
+	  
+	  emit_insn (gen_movsi (reg, GEN_INT (-1)));
+	  emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
+	}
+      else
+	{
+	  rtx reg = gen_reg_rtx (SImode);
+	
+	  emit_insn (gen_movsi (reg, GEN_INT (-1)));
+	  emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
+	}
+    }
+  else
+    {
+      emit_insn (gen_movsi_internal (operands[0], GEN_INT (-1)));
+      emit_insn (gen_xorsi3 (operands[0], operands[1], operands[0]));
+    }
+  DONE;
+  }"
+)
+
+;;}}} 
+;;{{{ Comparisons 
+
+;; Note, we store the operands in the comparison insns, and use them later
+;; when generating the branch or scc operation.
+
+;; First the routines called by the machine independent part of the compiler
+(define_expand "cmpsi"
+  [(set (reg:CC 16)
+        (compare:CC (match_operand:SI 0 "register_operand"  "")
+		    (match_operand:SI 1 "nonmemory_operand" "")))]
+  ""
+  "{
+  fr30_compare_op0 = operands[0];
+  fr30_compare_op1 = operands[1];
+  DONE;
+  }"
+)
+
+;; Now, the actual comparisons, generated by the branch and/or scc operations
+
+(define_insn "*cmpsi_internal"
+  [(set (reg:CC 16)
+	(compare:CC (match_operand:SI 0 "register_operand"  "r,r,r")
+		    (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
+  ""
+  "@
+  cmp	%1, %0
+  cmp	%1, %0
+  cmp2	%1, %0"
+)
+
+;;}}} 
+;;{{{ Branches 
+
+;; Define_expands called by the machine independent part of the compiler
+;; to allocate a new comparison register
+
+(define_expand "beq"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq:CC (reg:CC 16)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "bne"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (ne:CC (reg:CC 16)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "blt"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (lt:CC (reg:CC 16)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "ble"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (le:CC (reg:CC 16)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "bgt"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (gt:CC (reg:CC 16)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "bge"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (ge:CC (reg:CC 16)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "bltu"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (ltu:CC (reg:CC 16)
+			      (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "bleu"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (leu:CC (reg:CC 16)
+			      (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "bgtu"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (gtu:CC (reg:CC 16)
+			      (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+(define_expand "bgeu"
+  [(set (reg:CC 16)
+	(compare:CC (match_dup 1)
+		    (match_dup 2)))
+   (set (pc)
+	(if_then_else (geu:CC (reg:CC 16)
+			      (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "{
+  operands[1] = fr30_compare_op0;
+  operands[2] = fr30_compare_op1;
+  }"
+)
+
+;; Actual branches.  We must allow for the (label_ref) and the (pc) to be
+;; swapped.  If they are swapped, it reverses the sense of the branch.
+
+;; This pattern matches the (branch-if-true) branches generated above.
+;; It generates two different instruction sequences depending upon how
+;; far away the destination is.
+
+;; The calculation for the instruction length is derived as follows:
+;; The branch instruction has a 9 bit signed displacement so we have
+;; this inequality for the displacement:
+;;
+;;               -256 <= pc < 256
+;; or
+;;	   -256 + 256 <= pc + 256 < 256 + 256
+;; ie
+;;		    0 <= pc + 256 < 512 
+;;
+;; if we consider the displacement as an unsigned value, then negative
+;; displacements become very large positive displacements, and the
+;; inequality becomes:
+;;
+;;		pc + 256 < 512
+;;
+;; In order to allow for the fact that the real branch instruction works
+;; from pc + 2, we increase the offset to 258.
+;;
+;; Note - we do not have to worry about whether the branch is delayed or
+;; not, as branch shortening happens after delay slot reorganisation.
+
+(define_insn "*branch_true"
+  [(set (pc)
+	(if_then_else (match_operator:CC 0 "comparison_operator"
+					 [(reg:CC 16)
+					  (const_int 0)])
+		      (label_ref (match_operand 1 "" ""))
+		      (pc)))]
+  ""
+  "*
+  {
+    if (get_attr_length (insn) == 2)
+      return \"b%b0%#\\t%l1\";
+    else
+      {
+        static char buffer [100];
+	char *      tmp_reg; 
+	char *      ldi_insn;
+	
+        tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
+	
+	ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
+
+	/* The code produced here is, for say the EQ case:
+
+	       Bne  1f
+	       LDI  <label>, r0
+	       JMP  r0
+	     1:                                         */
+	     
+	sprintf (buffer,
+	  \"b%%B0\\t1f\\t;\\n\\t%s\\t%%l1, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\\n1:\",
+	  ldi_insn, tmp_reg, tmp_reg);
+ 
+        return buffer;
+    }
+  }"
+  [(set (attr "length") (if_then_else
+			  (ltu
+			    (plus
+			      (minus
+			        (match_dup 1)
+				(pc))
+			      (const_int 254))
+			    (const_int 506))
+			  (const_int 2)
+			  (if_then_else (eq_attr "size" "small")
+					(const_int 8)
+					(const_int 10))))
+   (set_attr "delay_type" "delayed")]
+)
+
+
+;; This pattern is a duplicate of the previous one, except that the
+;; branch occurs if the test is false, so the %B operator is used.
+(define_insn "*branch_false"
+  [(set (pc)
+	(if_then_else (match_operator:CC 0 "comparison_operator"
+					 [(reg:CC 16)
+					  (const_int 0)])
+		      (pc)
+		      (label_ref (match_operand 1 "" ""))))]
+  ""
+  "*
+  {
+    if (get_attr_length (insn) == 2)
+      return \"b%B0%#\\t%l1 \";
+    else
+      {
+        static char buffer [100];
+	char *      tmp_reg; 
+	char *      ldi_insn;
+	
+        tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
+	
+	ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
+
+	sprintf (buffer,
+	  \"b%%b0\\t1f\\t;\\n\\t%s\\t%%l1, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\\n1:\",
+	  ldi_insn, tmp_reg, tmp_reg);
+ 
+        return buffer;
+      }
+  }"
+  [(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 1) (pc))
+						 (const_int 254))
+					   (const_int 506))
+				      (const_int 2)
+				      (if_then_else (eq_attr "size" "small")
+						    (const_int 8)
+						    (const_int 10))))
+   (set_attr "delay_type" "delayed")]
+)
+
+;;}}} 
+;;{{{ Calls & Jumps 
+
+;; Subroutine call instruction returning no value.  Operand 0 is the function
+;; to call; operand 1 is the number of bytes of arguments pushed (in mode
+;; `SImode', except it is normally a `const_int'); operand 2 is the number of
+;; registers used as operands.
+
+(define_insn "call"
+  [(call (match_operand 0 "call_operand" "Qrm")
+	 (match_operand 1 ""             "g"))
+   (clobber (reg:SI 17))]
+  ""
+  "call%#\\t%0"
+  [(set_attr "delay_type" "delayed")]
+)
+
+;; Subroutine call instruction returning a value.  Operand 0 is the hard
+;; register in which the value is returned.  There are three more operands, the
+;; same as the three operands of the `call' instruction (but with numbers
+;; increased by one).
+
+;; Subroutines that return `BLKmode' objects use the `call' insn.
+
+(define_insn "call_value"
+  [(set (match_operand 0 "register_operand"  "=r")
+	(call (match_operand 1 "call_operand" "Qrm")
+	      (match_operand 2 ""             "g")))
+   (clobber (reg:SI 17))]
+  ""
+  "call%#\\t%1"
+  [(set_attr "delay_type" "delayed")]
+)
+
+;; Normal unconditional jump.
+;; For a description of the computation of the length 
+;; attribute see the branch patterns above.
+(define_insn "jump"
+  [(set (pc) (label_ref (match_operand 0 "" "")))]
+  ""
+  "*
+  {
+    if (get_attr_length (insn) == 2)
+       return \"bra%#\\t%0\";
+    else
+      {
+        static char buffer [100];
+	char *      tmp_reg; 
+	char *      ldi_insn;
+	
+        tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
+
+	ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
+
+	sprintf (buffer, \"%s\\t%%0, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\",
+	  ldi_insn, tmp_reg, tmp_reg);
+ 
+        return buffer;
+      }
+  }"
+  [(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
+						(const_int 254))
+					  (const_int 506))
+				     (const_int 2)
+				     (if_then_else (eq_attr "size" "small")
+						   (const_int 6)
+						   (const_int 8))))
+   (set_attr "delay_type" "delayed")]
+)
+
+;; Indirect jump through a register
+(define_insn "indirect_jump"
+  [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "r"))]
+  "GET_CODE (operands[0]) != MEM || GET_CODE (XEXP (operands[0], 0)) != PLUS"
+  "jmp%#\\t@%0"
+  [(set_attr "delay_type" "delayed")]
+)
+
+(define_insn "tablejump"
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jmp%#\\t@%0"
+  [(set_attr "delay_type" "delayed")]
+)
+
+;;}}} 
+;;{{{ Function Prologues and Epilogues 
+
+;; Called after register allocation to add any instructions needed for the
+;; prologue.  Using a prologue insn is favored compared to putting all of the
+;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
+;; to intermix instructions with the saves of the caller saved registers.  In
+;; some cases, it might be necessary to emit a barrier instruction as the last
+;; insn to prevent such scheduling.
+(define_expand "prologue"
+  [(const_int 0)]
+  ""
+  "{
+  fr30_expand_prologue ();
+  DONE;
+  }"
+)
+
+;; Called after register allocation to add any instructions needed for the
+;; epilogue.  Using a epilogue insn is favored compared to putting all of the
+;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
+;; to intermix instructions with the restores of the caller saved registers.
+;; In some cases, it might be necessary to emit a barrier instruction as the
+;; first insn to prevent such scheduling.
+(define_expand "epilogue"
+  [(return)]
+  ""
+  "{
+  fr30_expand_epilogue ();
+  DONE;
+  }"
+)
+
+(define_insn "return_from_func"
+  [(return)
+   (use (reg:SI 17))]
+  "reload_completed"
+  "ret%#"
+  [(set_attr "delay_type" "delayed")]
+)
+
+(define_insn "leave_func"
+  [(set (reg:SI 15) (reg:SI 14))
+   (set (reg:SI 14) (mem:SI (post_inc:SI (reg:SI 15))))]
+  "reload_completed"
+  "leave"
+)
+
+(define_insn "enter_func"
+  [(set:SI (mem:SI (minus:SI (reg:SI 15)
+			     (const_int 4)))
+	   (reg:SI 14))
+   (set:SI (reg:SI 14)
+	   (minus:SI (reg:SI 15)
+		     (const_int 4)))
+   (set:SI (reg:SI 15)
+	   (minus:SI (reg:SI 15)
+		     (match_operand 0 "immediate_operand" "i")))]
+  "reload_completed"
+  "enter	#%0"
+  [(set_attr "delay_type" "other")]
+)
+
+;;}}} 
+;;{{{ Miscellaneous 
+
+;; No operation, needed in case the user uses -g but not -O.
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop"
+)
+
+;; Pseudo instruction that prevents the scheduler from moving code above this
+;; point.
+(define_insn "blockage"
+  [(unspec_volatile [(const_int 0)] 0)]
+  ""
+  ""
+  [(set_attr "length" "0")]
+)
+  
+;; Local Variables:
+;; mode: md
+;; folded-file: t
+;; End:
+
+;;}}} 

gcc/config/fr30/lib1funcs.asm

+/* libgcc1 routines for the FR30.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this library with files
+   compiled with GCC to produce an executable, this does not cause
+   the resulting executable to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.  */
+	
+
+	.macro FUNC_START name
+	.text
+	.globl __\name
+	.type  __\name, @function
+__\name:
+	.endm
+
+	.macro FUNC_END name
+	.size  __\name, . - __\name
+	.endm
+
+	.macro DIV_BODY reg number
+	.if \number
+	DIV_BODY  \reg, "\number - 1"
+	div1	\reg
+	.endif
+	.endm
+	
+#ifdef L_udivsi3
+FUNC_START udivsi3
+	;; Perform an unsiged division of r4 / r5 and place the result in r4.
+	;; Does not handle overflow yet...
+	mov	r4, mdl
+	div0u	r5
+	DIV_BODY r5 32
+	mov	mdl, r4
+	ret
+FUNC_END udivsi3
+#endif /* L_udivsi3 */
+
+#ifdef L_divsi3
+FUNC_START divsi3
+	;; Perform a siged division of r4 / r5 and place the result in r4.
+	;; Does not handle overflow yet...
+	mov	r4, mdl
+	div0s	r5
+	DIV_BODY r5 32
+	div2    r5
+	div3
+	div4s
+	mov	mdl, r4
+	ret
+FUNC_END divsi3
+#endif /* L_divsi3 */
+
+#ifdef L_umodsi3
+FUNC_START umodsi3
+	;; Perform an unsiged division of r4 / r5 and places the remainder in r4.
+	;; Does not handle overflow yet...
+	mov	r4, mdl
+	div0u	r5
+	DIV_BODY r5 32
+	mov	mdh, r4
+	ret
+FUNC_END umodsi3
+#endif /* L_umodsi3 */
+
+#ifdef L_modsi3
+FUNC_START modsi3
+	;; Perform a siged division of r4 / r5 and place the remainder in r4.
+	;; Does not handle overflow yet...
+	mov	r4, mdl
+	div0s	r5
+	DIV_BODY r5 32
+	div2    r5
+	div3
+	div4s
+	mov	mdh, r4
+	ret
+FUNC_END modsi3
+#endif /* L_modsi3 */
+
+#ifdef L_negsi2
+FUNC_START negsi2
+	ldi:8	#0, r0
+	sub	r4, r0
+	mov	r0, r4
+	ret
+FUNC_END negsi2
+#endif /* L_negsi2 */
+
+#ifdef L_one_cmplsi2
+FUNC_START one_cmplsi2
+	ldi:8	#0xff, r0
+	extsb	r0
+	eor	r0, r4
+	ret
+FUNC_END one_cmplsi2
+#endif /* L_one_cmplsi2 */
+
+

gcc/config/fr30/t-fr30

+
+# Name of assembly file containing libgcc1 functions.
+# This entry must be present, but it can be empty if the target does
+# not need any assembler functions to support its code generation.
+# CROSS_LIBGCC1 =
+#
+# Alternatively if assembler functions *are* needed then define the
+# entries below:
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC    = fr30/lib1funcs.asm
+LIB1ASMFUNCS  = _udivsi3 _divsi3 _umodsi3 _modsi3
+
+# Assemble startup files.
+crti.o: $(srcdir)/config/fr30/crti.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) -c -o crti.o -x assembler $(srcdir)/config/fr30/crti.asm
+
+crtn.o: $(srcdir)/config/fr30/crtn.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) -c -o crtn.o -x assembler $(srcdir)/config/fr30/crtn.asm
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so...
+
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+# If any special flags are necessary when building libgcc2 put them here.
+#
+# TARGET_LIBGCC2_CFLAGS
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+# Enable the following if multilibs are needed.
+# See gcc/genmultilib, gcc/gcc.texi and gcc/tm.texi for a
+# description of the options and their values.
+#
+# MULTILIB_OPTIONS    = 
+# MULTILIB_DIRNAMES   = 
+# MULTILIB_MATCHES    =
+# MULTILIB_EXCEPTIONS =
+# MULTILIB_EXTRA_OPTS = 
+#
+# LIBGCC = stmp-multilib
+# INSTALL_LIBGCC = install-multilib

gcc/config/fr30/xm-fr30.h

+/* Definitions of FR30 target.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* #defines that need visibility everywhere.  */
+#define	FALSE	0
+#define	TRUE	1
+
+/* A C expression for the status code to be returned when the compiler exits
+   after serious errors.  */
+#define FATAL_EXIT_CODE 33
+
+/* A C expression for the status code to be returned when the compiler exits
+   without serious errors.  */
+#define SUCCESS_EXIT_CODE 0
+
+/* Defined if the host machine stores words of multi-word values in big-endian
+   order.  (GNU CC does not depend on the host byte ordering within a word.)  */
+/* #define HOST_WORDS_BIG_ENDIAN 1 */
+
+/* In addition, configuration files for system V define `bcopy', `bzero' and
+   `bcmp' as aliases.  Some files define `alloca' as a macro when compiled with
+   GNU CC, in order to take advantage of the benefit of GNU CC's built-in
+   `alloca'.  */
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+#include "tm.h"
+
+/* end of xm-fr30.h */

gcc/configure

@@ -3392,6 +3392,11 @@ for machine in $build $host $target; do
 	elxsi-elxsi-*)
 		use_collect2=yes
 		;;
+	fr30-*-elf)
+		tm_file="fr30/fr30.h"
+		tmake_file=fr30/t-fr30
+		extra_parts="crti.o crtn.o crtbegin.o crtend.o"
+		;;
 # This hasn't been upgraded to GCC 2.
 #	fx80-alliant-*)			# Alliant FX/80
 #		;;

gcc/configure.in

@@ -865,6 +865,11 @@ changequote([,])dnl
 	elxsi-elxsi-*)
 		use_collect2=yes
 		;;
+	fr30-*-elf)
+		tm_file="fr30/fr30.h"
+		tmake_file=fr30/t-fr30
+		extra_parts="crti.o crtn.o crtbegin.o crtend.o"
+		;;
 # This hasn't been upgraded to GCC 2.
 #	fx80-alliant-*)			# Alliant FX/80
 #		;;