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riscv-gcc-1
Commit 2f95ebc2 by Torbjorn Granlund
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(iorscc): New recognizer. 

2 new recognizers for sub;subb.  1 new recognizer for addi;subb.
(movstrsi): Remove predicates.  Set inline threshold to 8.
(umulsidi3): Change predicates to nonimmediate_operand.
New recognizer for multiply-by-immediate.
(andsi3): Add `!' for register alternative.
(vdepi_ior, vdepi_and): New recognizers.
(vextru rx,1,ry, vextrs rx,1,ry): New recognizers.
(call, call_value): If PIC, emit USE for for
PIC_OFFSET_TABLE_REGNUM.  Use PIC_OFFSET_TABLE_REGNUM rather than 19.

From-SVN: r6294
parent 5a1c10de
Showing with 122 additions and 11 deletions
gcc/config/pa/pa.md
......@@ -88,7 +88,6 @@
(const_string "false")))
;; Unconditional branch, call, and millicode call delay slot description.
(define_delay (eq_attr "type" "uncond_branch,branch,call,milli")
[(eq_attr "in_call_delay" "true") (nil) (nil)])
......@@ -385,6 +384,19 @@
[(set_attr "type" "binary")
(set_attr "length" "8")])
(define_insn "iorscc"
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (match_operator:SI 3 "comparison_operator"
[(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith11_operand" "rI")])
(match_operator:SI 6 "comparison_operator"
[(match_operand:SI 4 "register_operand" "r")
(match_operand:SI 5 "arith11_operand" "rI")])))]
""
"com%I2clr,%S3 %2,%1,0\;com%I2clr,%B6 %5,%4,%0\;ldi 1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
;; Combiner patterns for common operations performed with the output
;; from an scc insn (negscc and incscc).
(define_insn "negscc"
......@@ -461,6 +473,17 @@
[(set_attr "type" "binary")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
(gtu:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "arith11_operand" "rI")))
(match_operand:SI 4 "register_operand" "r")))]
""
"sub%I3 %3,%2,0\;subb %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
; This need only accept registers for op3, since canonicalization
; replaces ltu with leu when op3 is an integer.
(define_insn ""
......@@ -473,6 +496,17 @@
[(set_attr "type" "binary")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
(ltu:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "register_operand" "r")))
(match_operand:SI 4 "register_operand" "r")))]
""
"sub %2,%3,0\;subb %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
; Match only integers for op3 here. This is used as canonical form of the
; ltu pattern when op3 is an integer. Don't match registers since we can't
; make better code than the general incscc pattern.
......@@ -486,6 +520,17 @@
[(set_attr "type" "binary")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
(leu:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "int11_operand" "I")))
(match_operand:SI 4 "register_operand" "r")))]
""
"addi %k3,%2,0\;subb %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
(define_insn "decscc"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(minus:SI (match_operand:SI 1 "register_operand" "0,?r")
......@@ -1096,7 +1141,7 @@
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=a")
(high:SI (match_operand 1 "" "")))]
"symbolic_operand(operands[1], Pmode)
"symbolic_operand (operands[1], Pmode)
&& ! function_label_operand (operands[1])
&& ! read_only_operand (operands[1])"
"@
......@@ -1323,8 +1368,8 @@
;; that anything generated as this insn will be recognized as one
;; and that it will not successfully combine with anything.
(define_expand "movstrsi"
[(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
(mem:BLK (match_operand:BLK 1 "general_operand" "")))
[(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
(mem:BLK (match_operand:BLK 1 "" "")))
(clobber (match_dup 0))
(clobber (match_dup 1))
(clobber (match_dup 4))
......@@ -1340,7 +1385,7 @@
runtime and make the optimal decisions. */
if (INTVAL (operands[3]) < 4
&& (GET_CODE (operands[2]) != CONST_INT
|| (INTVAL (operands[2]) / INTVAL (operands[3]) > 16)))
|| (INTVAL (operands[2]) / INTVAL (operands[3]) > 8)))
FAIL;
operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
......@@ -2037,14 +2082,22 @@
}")
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=x")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "x"))
(zero_extend:DI (match_operand:SI 2 "register_operand" "x"))))]
[(set (match_operand:DI 0 "nonimmediate_operand" "=x")
(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "x"))
(zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "x"))))]
"TARGET_SNAKE && ! TARGET_DISABLE_FPREGS"
"xmpyu %1,%2,%0"
[(set_attr "type" "fpmul")])
(define_insn ""
[(set (match_operand:DI 0 "nonimmediate_operand" "=x")
(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "x"))
(match_operand:DI 2 "uint32_operand" "x")))]
"TARGET_SNAKE && ! TARGET_DISABLE_FPREGS"
"xmpyu %1,%R2,%0"
[(set_attr "type" "fpmul")])
(define_insn ""
[(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
(clobber (reg:SI 26))
......@@ -2252,9 +2305,11 @@
"and %1,%2,%0\;and %R1,%R2,%R0"
[(set_attr "length" "8")])
; The ! for op1 makes reload prefer zdepi instead of loading a huge
; constant with ldil;ldo.
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(and:SI (match_operand:SI 1 "register_operand" "%r,0")
(and:SI (match_operand:SI 1 "register_operand" "%!r,0")
(match_operand:SI 2 "and_operand" "rO,P")))]
""
"* return output_and (operands); "
......@@ -2607,6 +2662,36 @@
return \"zvdepi %1,%2,%0\";
}")
(define_insn "vdepi_ior"
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
(minus:SI (const_int 31)
(match_operand:SI 2 "register_operand" "q")))
(match_operand:SI 3 "register_operand" "0")))]
; accept ...0001...1, can this be generalized?
"exact_log2 (INTVAL (operands[1]) + 1) >= 0"
"*
{
int x = INTVAL (operands[1]);
operands[2] = GEN_INT (exact_log2 (x + 1));
return \"vdepi -1,%2,%0\";
}")
(define_insn "vdepi_and"
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
(minus:SI (const_int 31)
(match_operand:SI 2 "register_operand" "q")))
(match_operand:SI 3 "register_operand" "0")))]
; this can be generalized...!
"INTVAL (operands[1]) == -2"
"*
{
int x = INTVAL (operands[1]);
operands[2] = GEN_INT (exact_log2 ((~x) + 1));
return \"vdepi 0,%2,%0\";
}")
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
......@@ -2868,6 +2953,10 @@
{
rtx op;
if (flag_pic)
emit_insn (gen_rtx (USE, VOIDmode,
gen_rtx (REG, Pmode, PIC_OFFSET_TABLE_REGNUM)));
if (TARGET_LONG_CALLS)
op = force_reg (SImode, XEXP (operands[0], 0));
else
......@@ -2888,7 +2977,8 @@
if (!hppa_save_pic_table_rtx)
hppa_save_pic_table_rtx = gen_reg_rtx (Pmode);
emit_insn (gen_rtx (SET, VOIDmode,
gen_rtx (REG, Pmode, 19), hppa_save_pic_table_rtx));
gen_rtx (REG, Pmode, PIC_OFFSET_TABLE_REGNUM),
hppa_save_pic_table_rtx));
}
DONE;
}")
......@@ -2928,6 +3018,10 @@
{
rtx op;
if (flag_pic)
emit_insn (gen_rtx (USE, VOIDmode,
gen_rtx (REG, Pmode, PIC_OFFSET_TABLE_REGNUM)));
if (TARGET_LONG_CALLS)
op = force_reg (SImode, XEXP (operands[1], 0));
else
......@@ -2949,7 +3043,8 @@
if (!hppa_save_pic_table_rtx)
hppa_save_pic_table_rtx = gen_reg_rtx (Pmode);
emit_insn (gen_rtx (SET, VOIDmode,
gen_rtx (REG, Pmode, 19), hppa_save_pic_table_rtx));
gen_rtx (REG, Pmode, PIC_OFFSET_TABLE_REGNUM),
hppa_save_pic_table_rtx));
}
DONE;
}")
......@@ -3030,6 +3125,14 @@
""
"extru %1,%3+%2-1,%2,%0")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
(match_operand:SI 3 "register_operand" "q")))]
""
"vextru %1,1,%0")
(define_insn "extv"
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
......@@ -3038,6 +3141,14 @@
""
"extrs %1,%3+%2-1,%2,%0")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
(match_operand:SI 3 "register_operand" "q")))]
""
"vextrs %1,1,%0")
(define_insn "insv"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
(match_operand:SI 1 "uint5_operand" "")
......
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