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riscv-gcc-1
Commit 2f7e5a0d by Eric Christopher Committed by Eric Christopher
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s390.c (s390_emit_prologue): Call unspec tpf prologue insn instead of setting up call. 

2004-05-03  Eric Christopher  <echristo@redhat.com>

        * config/s390/s390.c (s390_emit_prologue): Call unspec tpf
        prologue insn instead of setting up call.
        (s390_emit_epilogue): Ditto.
        * config/s390/s390.md (prologue_tpf, epilogue_tpf): New patterns.
        (define_constants): Add numbers for above patterns.

From-SVN: r81466
parent 38899e29
Showing with 92 additions and 69 deletions
gcc/ChangeLog
2004-05-03 Eric Christopher <echristo@redhat.com> 2004-05-03 Eric Christopher <echristo@redhat.com>
* config/s390/s390.c (s390_emit_prologue): Call unspec tpf
prologue insn instead of setting up call.
(s390_emit_epilogue): Ditto.
* config/s390/s390.md (prologue_tpf, epilogue_tpf): New patterns.
(define_constants): Add numbers for above patterns.
2004-05-03 Eric Christopher <echristo@redhat.com>
* config/s390/s390.h (CONDITIONAL_REGISTER_USAGE): Move body... * config/s390/s390.h (CONDITIONAL_REGISTER_USAGE): Move body...
* config/s390/s390.c (s390_conditional_register_usage): ...here. * config/s390/s390.c (s390_conditional_register_usage): ...here.
* config/s390/s390-protos.h: Prototype. * config/s390/s390-protos.h: Prototype.
......
gcc/config/s390/s390.c
...@@ -5683,11 +5683,8 @@ s390_emit_prologue (void) ...@@ -5683,11 +5683,8 @@ s390_emit_prologue (void)
{ {
/* Generate a BAS instruction to serve as a function /* Generate a BAS instruction to serve as a function
entry intercept to facilitate the use of tracing entry intercept to facilitate the use of tracing
algorithms located at the branch target. algorithms located at the branch target. */
emit_insn (gen_prologue_tpf ());
This must use register 1. */
s390_emit_call (GEN_INT (0xfe0), NULL_RTX, NULL_RTX,
gen_rtx_REG (Pmode, 1));
/* Emit a blockage here so that all code /* Emit a blockage here so that all code
lies between the profiling mechanisms. */ lies between the profiling mechanisms. */
...@@ -5710,16 +5707,13 @@ s390_emit_epilogue (bool sibcall) ...@@ -5710,16 +5707,13 @@ s390_emit_epilogue (bool sibcall)
/* Generate a BAS instruction to serve as a function /* Generate a BAS instruction to serve as a function
entry intercept to facilitate the use of tracing entry intercept to facilitate the use of tracing
algorithms located at the branch target. algorithms located at the branch target. */
This must use register 1. */
/* Emit a blockage here so that all code /* Emit a blockage here so that all code
lies between the profiling mechanisms. */ lies between the profiling mechanisms. */
emit_insn (gen_blockage ()); emit_insn (gen_blockage ());
s390_emit_call (GEN_INT (0xfe6), NULL_RTX, NULL_RTX, emit_insn (gen_epilogue_tpf ());
gen_rtx_REG (Pmode, 1));
} }
/* Check whether to use frame or stack pointer for restore. */ /* Check whether to use frame or stack pointer for restore. */
......
gcc/config/s390/s390.md
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
;; I -- An 8-bit constant (0..255). ;; I -- An 8-bit constant (0..255).
;; J -- A 12-bit constant (0..4095). ;; J -- A 12-bit constant (0..4095).
;; K -- A 16-bit constant (-32768..32767). ;; K -- A 16-bit constant (-32768..32767).
;; L -- Value appropriate as displacement. ;; L -- Value appropriate as displacement.
;; (0..4095) for short displacement ;; (0..4095) for short displacement
;; (-524288..524287) for long displacement ;; (-524288..524287) for long displacement
;; M -- Constant integer with a value of 0x7fffffff. ;; M -- Constant integer with a value of 0x7fffffff.
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
;; H,Q: mode of the part ;; H,Q: mode of the part
;; D,S,H: mode of the containing operand ;; D,S,H: mode of the containing operand
;; 0,F: value of the other parts (F - all bits set) ;; 0,F: value of the other parts (F - all bits set)
;; ;;
;; The constraint matches if the specified part of a constant ;; The constraint matches if the specified part of a constant
;; has a value different from its other parts. ;; has a value different from its other parts.
;; Q -- Memory reference without index register and with short displacement. ;; Q -- Memory reference without index register and with short displacement.
...@@ -118,6 +118,10 @@ ...@@ -118,6 +118,10 @@
[; Blockage [; Blockage
(UNSPECV_BLOCKAGE 0) (UNSPECV_BLOCKAGE 0)
; TPF Support
(UNSPECV_TPF_PROLOGUE 20)
(UNSPECV_TPF_EPILOGUE 21)
; Literal pool ; Literal pool
(UNSPECV_POOL 200) (UNSPECV_POOL 200)
(UNSPECV_POOL_START 201) (UNSPECV_POOL_START 201)
...@@ -537,7 +541,7 @@ ...@@ -537,7 +541,7 @@
(define_insn "*tmdi_reg" (define_insn "*tmdi_reg"
[(set (reg 33) [(set (reg 33)
(compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
(match_operand:DI 1 "immediate_operand" (match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0")) "N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))] (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
"TARGET_64BIT "TARGET_64BIT
...@@ -1082,9 +1086,9 @@ ...@@ -1082,9 +1086,9 @@
(set_attr "type" "larl")]) (set_attr "type" "larl")])
(define_insn "*movdi_64" (define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" [(set (match_operand:DI 0 "nonimmediate_operand"
"=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q") "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q")
(match_operand:DI 1 "general_operand" (match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))] "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
...@@ -1281,9 +1285,9 @@ ...@@ -1281,9 +1285,9 @@
(set_attr "type" "larl")]) (set_attr "type" "larl")])
(define_insn "*movsi_zarch" (define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand" [(set (match_operand:SI 0 "nonimmediate_operand"
"=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
(match_operand:SI 1 "general_operand" (match_operand:SI 1 "general_operand"
"K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))] "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
...@@ -1423,7 +1427,7 @@ ...@@ -1423,7 +1427,7 @@
(match_operand:HI 1 "general_operand" ""))] (match_operand:HI 1 "general_operand" ""))]
"" ""
{ {
/* Make it explicit that loading a register from memory /* Make it explicit that loading a register from memory
always sign-extends (at least) to SImode. */ always sign-extends (at least) to SImode. */
if (optimize && !no_new_pseudos if (optimize && !no_new_pseudos
&& register_operand (operands[0], VOIDmode) && register_operand (operands[0], VOIDmode)
...@@ -1893,7 +1897,7 @@ ...@@ -1893,7 +1897,7 @@
(define_expand "strlendi" (define_expand "strlendi"
[(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
(parallel (parallel
[(set (match_dup 4) [(set (match_dup 4)
(unspec:DI [(const_int 0) (unspec:DI [(const_int 0)
(match_operand:BLK 1 "memory_operand" "") (match_operand:BLK 1 "memory_operand" "")
...@@ -1929,7 +1933,7 @@ ...@@ -1929,7 +1933,7 @@
(define_expand "strlensi" (define_expand "strlensi"
[(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
(parallel (parallel
[(set (match_dup 4) [(set (match_dup 4)
(unspec:SI [(const_int 0) (unspec:SI [(const_int 0)
(match_operand:BLK 1 "memory_operand" "") (match_operand:BLK 1 "memory_operand" "")
...@@ -1956,7 +1960,7 @@ ...@@ -1956,7 +1960,7 @@
(reg:QI 0) (reg:QI 0)
(match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
(clobber (match_scratch:SI 1 "=a")) (clobber (match_scratch:SI 1 "=a"))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"!TARGET_64BIT" "!TARGET_64BIT"
"srst\t%0,%1\;jo\t.-4" "srst\t%0,%1\;jo\t.-4"
[(set_attr "op_type" "NN") [(set_attr "op_type" "NN")
...@@ -2746,14 +2750,14 @@ ...@@ -2746,14 +2750,14 @@
(define_insn_and_split "*llgt_sidi_split" (define_insn_and_split "*llgt_sidi_split"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
(const_int 2147483647))) (const_int 2147483647)))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_64BIT" "TARGET_64BIT"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(and:DI (subreg:DI (match_dup 1) 0) (and:DI (subreg:DI (match_dup 1) 0)
(const_int 2147483647)))] (const_int 2147483647)))]
"") "")
...@@ -4282,7 +4286,7 @@ ...@@ -4282,7 +4286,7 @@
; ;
(define_insn "*adddi3_alc_cc" (define_insn "*adddi3_alc_cc"
[(set (reg 33) [(set (reg 33)
(compare (compare
(plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m")) (match_operand:DI 2 "general_operand" "d,m"))
...@@ -4290,7 +4294,7 @@ ...@@ -4290,7 +4294,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@ "@
alcgr\\t%0,%2 alcgr\\t%0,%2
alcg\\t%0,%2" alcg\\t%0,%2"
...@@ -4301,15 +4305,15 @@ ...@@ -4301,15 +4305,15 @@
(plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m")) (match_operand:DI 2 "general_operand" "d,m"))
(match_operand:DI 3 "s390_alc_comparison" ""))) (match_operand:DI 3 "s390_alc_comparison" "")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
alcgr\\t%0,%2 alcgr\\t%0,%2
alcg\\t%0,%2" alcg\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_slb_cc" (define_insn "*subdi3_slb_cc"
[(set (reg 33) [(set (reg 33)
(compare (compare
(minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")) (match_operand:DI 2 "general_operand" "d,m"))
...@@ -4317,7 +4321,7 @@ ...@@ -4317,7 +4321,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@ "@
slbgr\\t%0,%2 slbgr\\t%0,%2
slbg\\t%0,%2" slbg\\t%0,%2"
...@@ -4328,8 +4332,8 @@ ...@@ -4328,8 +4332,8 @@
(minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")) (match_operand:DI 2 "general_operand" "d,m"))
(match_operand:DI 3 "s390_slb_comparison" ""))) (match_operand:DI 3 "s390_slb_comparison" "")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
slbgr\\t%0,%2 slbgr\\t%0,%2
slbg\\t%0,%2" slbg\\t%0,%2"
...@@ -4340,7 +4344,7 @@ ...@@ -4340,7 +4344,7 @@
; ;
(define_insn "*addsi3_alc_cc" (define_insn "*addsi3_alc_cc"
[(set (reg 33) [(set (reg 33)
(compare (compare
(plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,m"))
...@@ -4348,7 +4352,7 @@ ...@@ -4348,7 +4352,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@ "@
alcr\\t%0,%2 alcr\\t%0,%2
alc\\t%0,%2" alc\\t%0,%2"
...@@ -4360,14 +4364,14 @@ ...@@ -4360,14 +4364,14 @@
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:SI 3 "s390_alc_comparison" ""))) (match_operand:SI 3 "s390_alc_comparison" "")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_CPU_ZARCH" "TARGET_CPU_ZARCH"
"@ "@
alcr\\t%0,%2 alcr\\t%0,%2
alc\\t%0,%2" alc\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subsi3_slb_cc" (define_insn "*subsi3_slb_cc"
[(set (reg 33) [(set (reg 33)
(compare (compare
(minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,m"))
...@@ -4375,7 +4379,7 @@ ...@@ -4375,7 +4379,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@ "@
slbr\\t%0,%2 slbr\\t%0,%2
slb\\t%0,%2" slb\\t%0,%2"
...@@ -4386,8 +4390,8 @@ ...@@ -4386,8 +4390,8 @@
(minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:SI 3 "s390_slb_comparison" ""))) (match_operand:SI 3 "s390_slb_comparison" "")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_CPU_ZARCH" "TARGET_CPU_ZARCH"
"@ "@
slbr\\t%0,%2 slbr\\t%0,%2
slb\\t%0,%2" slb\\t%0,%2"
...@@ -4657,7 +4661,7 @@ ...@@ -4657,7 +4661,7 @@
(ashift:TI (ashift:TI
(zero_extend:TI (zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0") (mod:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,m")))) (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
(const_int 64)) (const_int 64))
(zero_extend:TI (zero_extend:TI
...@@ -4713,12 +4717,12 @@ ...@@ -4713,12 +4717,12 @@
(define_insn "udivmodtidi3" (define_insn "udivmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d") [(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI (ior:TI
(ashift:TI (ashift:TI
(zero_extend:TI (zero_extend:TI
(truncate:DI (truncate:DI
(umod:TI (match_operand:TI 1 "register_operand" "0,0") (umod:TI (match_operand:TI 1 "register_operand" "0,0")
(zero_extend:TI (zero_extend:TI
(match_operand:DI 2 "nonimmediate_operand" "d,m"))))) (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
(const_int 64)) (const_int 64))
(zero_extend:TI (zero_extend:TI
...@@ -4773,12 +4777,12 @@ ...@@ -4773,12 +4777,12 @@
(define_insn "divmoddisi3" (define_insn "divmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(ior:DI (ior:DI
(ashift:DI (ashift:DI
(zero_extend:DI (zero_extend:DI
(truncate:SI (truncate:SI
(mod:DI (match_operand:DI 1 "register_operand" "0,0") (mod:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R"))))) (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
(const_int 32)) (const_int 32))
(zero_extend:DI (zero_extend:DI
...@@ -4835,12 +4839,12 @@ ...@@ -4835,12 +4839,12 @@
(define_insn "udivmoddisi3" (define_insn "udivmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(ior:DI (ior:DI
(ashift:DI (ashift:DI
(zero_extend:DI (zero_extend:DI
(truncate:SI (truncate:SI
(umod:DI (match_operand:DI 1 "register_operand" "0,0") (umod:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,m"))))) (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
(const_int 32)) (const_int 32))
(zero_extend:DI (zero_extend:DI
...@@ -5138,7 +5142,7 @@ ...@@ -5138,7 +5142,7 @@
(define_insn "anddi3" (define_insn "anddi3"
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d,d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o,0,0,0,0,0,0") (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o,0,0,0,0,0,0")
(match_operand:DI 2 "general_operand" (match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m"))) "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_64BIT" "TARGET_64BIT"
...@@ -5203,7 +5207,7 @@ ...@@ -5203,7 +5207,7 @@
[(set_attr "op_type" "RR,RX,RXY")]) [(set_attr "op_type" "RR,RX,RXY")])
(define_expand "andsi3" (define_expand "andsi3"
[(parallel [(parallel
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "") (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" ""))) (match_operand:SI 2 "general_operand" "")))
...@@ -5221,7 +5225,7 @@ ...@@ -5221,7 +5225,7 @@
# #
# #
nilh\t%0,%j2 nilh\t%0,%j2
nill\t%0,%j2 nill\t%0,%j2
nr\t%0,%2 nr\t%0,%2
n\t%0,%2 n\t%0,%2
ny\t%0,%2" ny\t%0,%2"
...@@ -5445,7 +5449,7 @@ ...@@ -5445,7 +5449,7 @@
[(set_attr "op_type" "RR,RX,RXY")]) [(set_attr "op_type" "RR,RX,RXY")])
(define_expand "iorsi3" (define_expand "iorsi3"
[(parallel [(parallel
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" ""))) (match_operand:SI 2 "general_operand" "")))
...@@ -6986,7 +6990,7 @@ ...@@ -6986,7 +6990,7 @@
(define_insn "*sibcall_br" (define_insn "*sibcall_br"
[(call (mem:QI (reg 1)) [(call (mem:QI (reg 1))
(match_operand 0 "const_int_operand" "n"))] (match_operand 0 "const_int_operand" "n"))]
"SIBLING_CALL_P (insn) "SIBLING_CALL_P (insn)
&& GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
"br\t%%r1" "br\t%%r1"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
...@@ -7027,7 +7031,7 @@ ...@@ -7027,7 +7031,7 @@
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
(call (mem:QI (reg 1)) (call (mem:QI (reg 1))
(match_operand 1 "const_int_operand" "n")))] (match_operand 1 "const_int_operand" "n")))]
"SIBLING_CALL_P (insn) "SIBLING_CALL_P (insn)
&& GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
"br\t%%r1" "br\t%%r1"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
...@@ -7063,7 +7067,7 @@ ...@@ -7063,7 +7067,7 @@
(use (match_operand 2 "" ""))] (use (match_operand 2 "" ""))]
"" ""
{ {
s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
gen_rtx_REG (Pmode, RETURN_REGNUM)); gen_rtx_REG (Pmode, RETURN_REGNUM));
DONE; DONE;
}) })
...@@ -7072,8 +7076,8 @@ ...@@ -7072,8 +7076,8 @@
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
(match_operand 1 "const_int_operand" "n")) (match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))] (clobber (match_operand 2 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn) "!SIBLING_CALL_P (insn)
&& TARGET_SMALL_EXEC && TARGET_SMALL_EXEC
&& GET_MODE (operands[2]) == Pmode" && GET_MODE (operands[2]) == Pmode"
"bras\t%2,%0" "bras\t%2,%0"
[(set_attr "op_type" "RI") [(set_attr "op_type" "RI")
...@@ -7083,8 +7087,8 @@ ...@@ -7083,8 +7087,8 @@
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
(match_operand 1 "const_int_operand" "n")) (match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))] (clobber (match_operand 2 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn) "!SIBLING_CALL_P (insn)
&& TARGET_CPU_ZARCH && TARGET_CPU_ZARCH
&& GET_MODE (operands[2]) == Pmode" && GET_MODE (operands[2]) == Pmode"
"brasl\t%2,%0" "brasl\t%2,%0"
[(set_attr "op_type" "RIL") [(set_attr "op_type" "RIL")
...@@ -7118,7 +7122,7 @@ ...@@ -7118,7 +7122,7 @@
(use (match_operand 3 "" ""))] (use (match_operand 3 "" ""))]
"" ""
{ {
s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
gen_rtx_REG (Pmode, RETURN_REGNUM)); gen_rtx_REG (Pmode, RETURN_REGNUM));
DONE; DONE;
}) })
...@@ -7128,8 +7132,8 @@ ...@@ -7128,8 +7132,8 @@
(call (mem:QI (match_operand 1 "bras_sym_operand" "X")) (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
(match_operand:SI 2 "const_int_operand" "n"))) (match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))] (clobber (match_operand 3 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn) "!SIBLING_CALL_P (insn)
&& TARGET_SMALL_EXEC && TARGET_SMALL_EXEC
&& GET_MODE (operands[3]) == Pmode" && GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1" "bras\t%3,%1"
[(set_attr "op_type" "RI") [(set_attr "op_type" "RI")
...@@ -7140,8 +7144,8 @@ ...@@ -7140,8 +7144,8 @@
(call (mem:QI (match_operand 1 "bras_sym_operand" "X")) (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
(match_operand 2 "const_int_operand" "n"))) (match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))] (clobber (match_operand 3 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn) "!SIBLING_CALL_P (insn)
&& TARGET_CPU_ZARCH && TARGET_CPU_ZARCH
&& GET_MODE (operands[3]) == Pmode" && GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1" "brasl\t%3,%1"
[(set_attr "op_type" "RIL") [(set_attr "op_type" "RIL")
...@@ -7236,8 +7240,8 @@ ...@@ -7236,8 +7240,8 @@
(match_operand 2 "const_int_operand" "n"))) (match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r")) (clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))] (use (match_operand 4 "" ""))]
"!SIBLING_CALL_P (insn) "!SIBLING_CALL_P (insn)
&& TARGET_SMALL_EXEC && TARGET_SMALL_EXEC
&& GET_MODE (operands[3]) == Pmode" && GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1%J4" "bras\t%3,%1%J4"
[(set_attr "op_type" "RI") [(set_attr "op_type" "RI")
...@@ -7249,8 +7253,8 @@ ...@@ -7249,8 +7253,8 @@
(match_operand 2 "const_int_operand" "n"))) (match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r")) (clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))] (use (match_operand 4 "" ""))]
"!SIBLING_CALL_P (insn) "!SIBLING_CALL_P (insn)
&& TARGET_CPU_ZARCH && TARGET_CPU_ZARCH
&& GET_MODE (operands[3]) == Pmode" && GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1%J4" "brasl\t%3,%1%J4"
[(set_attr "op_type" "RIL") [(set_attr "op_type" "RIL")
...@@ -7427,7 +7431,7 @@ ...@@ -7427,7 +7431,7 @@
return ""; return "";
} }
[(set_attr "op_type" "NN") [(set_attr "op_type" "NN")
(set (attr "length") (set (attr "length")
(symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
(define_insn "pool_start_31" (define_insn "pool_start_31"
...@@ -7522,11 +7526,28 @@ ...@@ -7522,11 +7526,28 @@
"" ""
"s390_emit_prologue (); DONE;") "s390_emit_prologue (); DONE;")
(define_insn "prologue_tpf"
[(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
(clobber (reg:DI 1))]
"TARGET_TPF"
"bas\t%%r1,4064"
[(set_attr "type" "jsr")
(set_attr "op_type" "RX")])
(define_expand "epilogue" (define_expand "epilogue"
[(use (const_int 1))] [(use (const_int 1))]
"" ""
"s390_emit_epilogue (false); DONE;") "s390_emit_epilogue (false); DONE;")
(define_insn "epilogue_tpf"
[(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
(clobber (reg:DI 1))]
"TARGET_TPF"
"bas\t%%r1,4070"
[(set_attr "type" "jsr")
(set_attr "op_type" "RX")])
(define_expand "sibcall_epilogue" (define_expand "sibcall_epilogue"
[(use (const_int 0))] [(use (const_int 0))]
"" ""
......
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