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riscv-gcc-1
Commit 2c3bcf47 by Matthew Fortune Committed by Matthew Fortune
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[MIPS] Remove all excess parallel constructs 

gcc/

	* config/mips/micromips.md (*swp): Remove explicit parallel.
	(jraddiusp, *movep<MOVEP1:mode><MOVEP2:mode>): Likewise.
	* config/mips/mips-dsp.md (add<DSPV:mode>3): Likewise.
	(mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>, sub<DSPV:mode>3): Likewise.
	(mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>, mips_addsc): Likewise.
	(mips_addwc, mips_absq_s_<DSPQ:dspfmt2>): Likewise.
	(mips_precrq_rs_ph_w, mips_precrqu_s_qb_ph): Likewise.
	(mips_shll_<DSPV:dspfmt2>, mips_shll_s_<DSPQ:dspfmt2>): Likewise.
	(mips_muleu_s_ph_qbl, mips_muleu_s_ph_qbr): Likewise.
	(mips_mulq_rs_ph, mips_muleq_s_w_phl, mips_muleq_s_w_phr): Likewise.
	(mips_dpaq_s_w_ph, mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph): Likewise.
	(mips_dpaq_sa_l_w, mips_dpsq_sa_l_w, mips_maq_s_w_phl): Likewise.
	(mips_maq_s_w_phr, mips_maq_sa_w_phl, mips_maq_sa_w_phr): Likewise.
	(mips_extr_w, mips_extr_r_w, mips_extr_rs_w): Likewise.
	(mips_extr_s_h, mips_extp, mips_extpdp, mips_mthlip): Likewise.
	(mips_wrdsp): Likewise.
	* config/mips/mips-dspr2.md (mips_absq_s_qb): Remove explicit
	parallel.
	(mips_addu_ph, mips_addu_s_ph, mips_cmpgdu_eq_qb): Likewise.
	(mips_cmpgdu_lt_qb, mips_cmpgdu_le_qb, mulv2hi3): Likewise.
	(mips_mul_s_ph, mips_mulq_rs_w, mips_mulq_s_ph): Likewise.
	(mips_mulq_s_w, mips_subu_ph, mips_subu_s_ph): Likewise.
	(mips_dpaqx_s_w_ph, mips_dpaqx_sa_w_ph): Likewise.
	(mips_dpsqx_s_w_ph, mips_dpsqx_sa_w_ph): Likewise.
	* config/mips/mips-fixed.md (usadd<mode>3): Remove explicit parallel.
	(ssadd<mode>3, ussub<mode>3, sssub<mode>3, ssmul<mode>3): Likewise.
	(ssmaddsqdq4, ssmsubsqdq4): Likewise.

From-SVN: r219639
parent 954bdd58
Showing with 60 additions and 55 deletions
gcc/ChangeLog
2015-01-15 Matthew Fortune <matthew.fortune@imgtec.com>
* config/mips/micromips.md (*swp): Remove explicit parallel.
(jraddiusp, *movep<MOVEP1:mode><MOVEP2:mode>): Likewise.
* config/mips/mips-dsp.md (add<DSPV:mode>3): Likewise.
(mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>, sub<DSPV:mode>3): Likewise.
(mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>, mips_addsc): Likewise.
(mips_addwc, mips_absq_s_<DSPQ:dspfmt2>): Likewise.
(mips_precrq_rs_ph_w, mips_precrqu_s_qb_ph): Likewise.
(mips_shll_<DSPV:dspfmt2>, mips_shll_s_<DSPQ:dspfmt2>): Likewise.
(mips_muleu_s_ph_qbl, mips_muleu_s_ph_qbr): Likewise.
(mips_mulq_rs_ph, mips_muleq_s_w_phl, mips_muleq_s_w_phr): Likewise.
(mips_dpaq_s_w_ph, mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph): Likewise.
(mips_dpaq_sa_l_w, mips_dpsq_sa_l_w, mips_maq_s_w_phl): Likewise.
(mips_maq_s_w_phr, mips_maq_sa_w_phl, mips_maq_sa_w_phr): Likewise.
(mips_extr_w, mips_extr_r_w, mips_extr_rs_w): Likewise.
(mips_extr_s_h, mips_extp, mips_extpdp, mips_mthlip): Likewise.
(mips_wrdsp): Likewise.
* config/mips/mips-dspr2.md (mips_absq_s_qb): Remove explicit
parallel.
(mips_addu_ph, mips_addu_s_ph, mips_cmpgdu_eq_qb): Likewise.
(mips_cmpgdu_lt_qb, mips_cmpgdu_le_qb, mulv2hi3): Likewise.
(mips_mul_s_ph, mips_mulq_rs_w, mips_mulq_s_ph): Likewise.
(mips_mulq_s_w, mips_subu_ph, mips_subu_s_ph): Likewise.
(mips_dpaqx_s_w_ph, mips_dpaqx_sa_w_ph): Likewise.
(mips_dpsqx_s_w_ph, mips_dpsqx_sa_w_ph): Likewise.
* config/mips/mips-fixed.md (usadd<mode>3): Remove explicit parallel.
(ssadd<mode>3, ussub<mode>3, sssub<mode>3, ssmul<mode>3): Likewise.
(ssmaddsqdq4, ssmsubsqdq4): Likewise.
2015-01-14 Matthew Fortune <matthew.fortune@imgtec.com>
* config/mips/mips.c (mips_rtx_costs): Set costs for LSA/DLSA.
......
gcc/config/mips/micromips.md
......@@ -80,11 +80,10 @@
;; The behavior of the SWP insn is undefined if placed in a delay slot.
(define_insn "*swp"
[(parallel [(set (match_operand:SI 0 "non_volatile_mem_operand")
[(set (match_operand:SI 0 "non_volatile_mem_operand")
(match_operand:SI 1 "d_operand"))
(set (match_operand:SI 2 "non_volatile_mem_operand")
(match_operand:SI 3 "d_operand"))])]
(match_operand:SI 3 "d_operand"))]
"TARGET_MICROMIPS
&& umips_load_store_pair_p (false, operands)"
{
......@@ -97,11 +96,11 @@
;; For JRADDIUSP.
(define_insn "jraddiusp"
[(parallel [(return)
[(return)
(use (reg:SI 31))
(set (reg:SI 29)
(plus:SI (reg:SI 29)
(match_operand 0 "uw5_operand")))])]
(match_operand 0 "uw5_operand")))]
"TARGET_MICROMIPS"
"jraddiusp\t%0"
[(set_attr "type" "trap")
......@@ -121,10 +120,10 @@
;; The behavior of the MOVEP insn is undefined if placed in a delay slot.
(define_insn "*movep<MOVEP1:mode><MOVEP2:mode>"
[(parallel [(set (match_operand:MOVEP1 0 "register_operand")
[(set (match_operand:MOVEP1 0 "register_operand")
(match_operand:MOVEP1 1 "movep_src_operand"))
(set (match_operand:MOVEP2 2 "register_operand")
(match_operand:MOVEP2 3 "movep_src_operand"))])]
(match_operand:MOVEP2 3 "movep_src_operand"))]
"TARGET_MICROMIPS
&& umips_movep_target_p (operands[0], operands[2])"
{
......
gcc/config/mips/mips-dspr2.md
......@@ -71,37 +71,34 @@
])
(define_insn "mips_absq_s_qb"
[(parallel
[(set (match_operand:V4QI 0 "register_operand" "=d")
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
UNSPEC_ABSQ_S_QB))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))]
"ISA_HAS_DSPR2"
"absq_s.qb\t%0,%z1"
[(set_attr "type" "dspalusat")
(set_attr "mode" "SI")])
(define_insn "mips_addu_ph"
[(parallel
[(set (match_operand:V2HI 0 "register_operand" "=d")
(plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))]
"ISA_HAS_DSPR2"
"addu.ph\t%0,%z1,%z2"
[(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_addu_s_ph"
[(parallel
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_ADDU_S_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))]
"ISA_HAS_DSPR2"
"addu_s.ph\t%0,%z1,%z2"
[(set_attr "type" "dspalusat")
......@@ -158,7 +155,6 @@
(set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_eq_qb"
[(parallel
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
......@@ -166,14 +162,13 @@
(set (reg:CCDSP CCDSP_CC_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMPGDU_EQ_QB))])]
UNSPEC_CMPGDU_EQ_QB))]
"ISA_HAS_DSPR2"
"cmpgdu.eq.qb\t%0,%z1,%z2"
[(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_lt_qb"
[(parallel
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
......@@ -181,14 +176,13 @@
(set (reg:CCDSP CCDSP_CC_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMPGDU_LT_QB))])]
UNSPEC_CMPGDU_LT_QB))]
"ISA_HAS_DSPR2"
"cmpgdu.lt.qb\t%0,%z1,%z2"
[(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_le_qb"
[(parallel
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
......@@ -196,7 +190,7 @@
(set (reg:CCDSP CCDSP_CC_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMPGDU_LE_QB))])]
UNSPEC_CMPGDU_LE_QB))]
"ISA_HAS_DSPR2"
"cmpgdu.le.qb\t%0,%z1,%z2"
[(set_attr "type" "dspalu")
......@@ -227,69 +221,64 @@
(set_attr "mode" "SI")])
(define_insn "mulv2hi3"
[(parallel
[(set (match_operand:V2HI 0 "register_operand" "=d")
(mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
(clobber (match_scratch:DI 3 "=x"))])]
(clobber (match_scratch:DI 3 "=x"))]
"ISA_HAS_DSPR2"
"mul.ph\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(define_insn "mips_mul_s_ph"
[(parallel
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_MUL_S_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
(clobber (match_scratch:DI 3 "=x"))])]
(clobber (match_scratch:DI 3 "=x"))]
"ISA_HAS_DSPR2"
"mul_s.ph\t%0,%z1,%z2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(define_insn "mips_mulq_rs_w"
[(parallel
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
UNSPEC_MULQ_RS_W))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
(clobber (match_scratch:DI 3 "=x"))])]
(clobber (match_scratch:DI 3 "=x"))]
"ISA_HAS_DSPR2"
"mulq_rs.w\t%0,%z1,%z2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(define_insn "mips_mulq_s_ph"
[(parallel
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_MULQ_S_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
(clobber (match_scratch:DI 3 "=x"))])]
(clobber (match_scratch:DI 3 "=x"))]
"ISA_HAS_DSPR2"
"mulq_s.ph\t%0,%z1,%z2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(define_insn "mips_mulq_s_w"
[(parallel
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
UNSPEC_MULQ_S_W))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
(clobber (match_scratch:DI 3 "=x"))])]
(clobber (match_scratch:DI 3 "=x"))]
"ISA_HAS_DSPR2"
"mulq_s.w\t%0,%z1,%z2"
[(set_attr "type" "imul3")
......@@ -418,26 +407,24 @@
(set_attr "mode" "SI")])
(define_insn "mips_subu_ph"
[(parallel
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_SUBU_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))]
"ISA_HAS_DSPR2"
"subu.ph\t%0,%z1,%z2"
[(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_subu_s_ph"
[(parallel
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_SUBU_S_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))]
"ISA_HAS_DSPR2"
"subu_s.ph\t%0,%z1,%z2"
[(set_attr "type" "dspalusat")
......@@ -568,7 +555,6 @@
(set_attr "mode" "SI")])
(define_insn "mips_dpaqx_s_w_ph"
[(parallel
[(set (match_operand:DI 0 "register_operand" "=a")
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
......@@ -576,7 +562,7 @@
UNSPEC_DPAQX_S_W_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPAQX_S_W_PH))])]
UNSPEC_DPAQX_S_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpaqx_s.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "dspmac")
......@@ -584,7 +570,6 @@
(set_attr "mode" "SI")])
(define_insn "mips_dpaqx_sa_w_ph"
[(parallel
[(set (match_operand:DI 0 "register_operand" "=a")
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
......@@ -592,7 +577,7 @@
UNSPEC_DPAQX_SA_W_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPAQX_SA_W_PH))])]
UNSPEC_DPAQX_SA_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpaqx_sa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "dspmacsat")
......@@ -600,7 +585,6 @@
(set_attr "mode" "SI")])
(define_insn "mips_dpsqx_s_w_ph"
[(parallel
[(set (match_operand:DI 0 "register_operand" "=a")
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
......@@ -608,7 +592,7 @@
UNSPEC_DPSQX_S_W_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPSQX_S_W_PH))])]
UNSPEC_DPSQX_S_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsqx_s.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "dspmac")
......@@ -616,7 +600,6 @@
(set_attr "mode" "SI")])
(define_insn "mips_dpsqx_sa_w_ph"
[(parallel
[(set (match_operand:DI 0 "register_operand" "=a")
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
......@@ -624,7 +607,7 @@
UNSPEC_DPSQX_SA_W_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPSQX_SA_W_PH))])]
UNSPEC_DPSQX_SA_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsqx_sa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "dspmacsat")
......
gcc/config/mips/mips-fixed.md
......@@ -52,24 +52,22 @@
(set_attr "mode" "<IMODE>")])
(define_insn "usadd<mode>3"
[(parallel
[(set (match_operand:UADDSUB 0 "register_operand" "=d")
(us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
(match_operand:UADDSUB 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
""
"addu_s.<uaddsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<IMODE>")])
(define_insn "ssadd<mode>3"
[(parallel
[(set (match_operand:ADDSUB 0 "register_operand" "=d")
(ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
(match_operand:ADDSUB 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
"ISA_HAS_DSP"
"addq_s.<addsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith")
......@@ -85,44 +83,40 @@
(set_attr "mode" "<IMODE>")])
(define_insn "ussub<mode>3"
[(parallel
[(set (match_operand:UADDSUB 0 "register_operand" "=d")
(us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
(match_operand:UADDSUB 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
""
"subu_s.<uaddsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<IMODE>")])
(define_insn "sssub<mode>3"
[(parallel
[(set (match_operand:ADDSUB 0 "register_operand" "=d")
(ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
(match_operand:ADDSUB 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
"ISA_HAS_DSP"
"subq_s.<addsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<IMODE>")])
(define_insn "ssmul<mode>3"
[(parallel
[(set (match_operand:MULQ 0 "register_operand" "=d")
(ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d")
(match_operand:MULQ 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
(clobber (match_scratch:DI 3 "=x"))])]
(clobber (match_scratch:DI 3 "=x"))]
""
"mulq_rs.<mulqfmt>\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "<IMODE>")])
(define_insn "ssmaddsqdq4"
[(parallel
[(set (match_operand:DQ 0 "register_operand" "=a")
(ss_plus:DQ
(ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
......@@ -132,14 +126,13 @@
(match_operand:DQ 3 "register_operand" "0")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPAQ_SA_L_W))])]
UNSPEC_DPAQ_SA_L_W))]
"ISA_HAS_DSP && !TARGET_64BIT"
"dpaq_sa.l.w\t%q0,%1,%2"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(define_insn "ssmsubsqdq4"
[(parallel
[(set (match_operand:DQ 0 "register_operand" "=a")
(ss_minus:DQ
(match_operand:DQ 3 "register_operand" "0")
......@@ -149,7 +142,7 @@
"register_operand" "d")))))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPSQ_SA_L_W))])]
UNSPEC_DPSQ_SA_L_W))]
"ISA_HAS_DSP && !TARGET_64BIT"
"dpsq_sa.l.w\t%q0,%1,%2"
[(set_attr "type" "imadd")
......
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