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riscv-gcc-1
Commit 2c3bcf47 by Matthew Fortune Committed by Matthew Fortune
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[MIPS] Remove all excess parallel constructs 

gcc/

	* config/mips/micromips.md (*swp): Remove explicit parallel.
	(jraddiusp, *movep<MOVEP1:mode><MOVEP2:mode>): Likewise.
	* config/mips/mips-dsp.md (add<DSPV:mode>3): Likewise.
	(mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>, sub<DSPV:mode>3): Likewise.
	(mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>, mips_addsc): Likewise.
	(mips_addwc, mips_absq_s_<DSPQ:dspfmt2>): Likewise.
	(mips_precrq_rs_ph_w, mips_precrqu_s_qb_ph): Likewise.
	(mips_shll_<DSPV:dspfmt2>, mips_shll_s_<DSPQ:dspfmt2>): Likewise.
	(mips_muleu_s_ph_qbl, mips_muleu_s_ph_qbr): Likewise.
	(mips_mulq_rs_ph, mips_muleq_s_w_phl, mips_muleq_s_w_phr): Likewise.
	(mips_dpaq_s_w_ph, mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph): Likewise.
	(mips_dpaq_sa_l_w, mips_dpsq_sa_l_w, mips_maq_s_w_phl): Likewise.
	(mips_maq_s_w_phr, mips_maq_sa_w_phl, mips_maq_sa_w_phr): Likewise.
	(mips_extr_w, mips_extr_r_w, mips_extr_rs_w): Likewise.
	(mips_extr_s_h, mips_extp, mips_extpdp, mips_mthlip): Likewise.
	(mips_wrdsp): Likewise.
	* config/mips/mips-dspr2.md (mips_absq_s_qb): Remove explicit
	parallel.
	(mips_addu_ph, mips_addu_s_ph, mips_cmpgdu_eq_qb): Likewise.
	(mips_cmpgdu_lt_qb, mips_cmpgdu_le_qb, mulv2hi3): Likewise.
	(mips_mul_s_ph, mips_mulq_rs_w, mips_mulq_s_ph): Likewise.
	(mips_mulq_s_w, mips_subu_ph, mips_subu_s_ph): Likewise.
	(mips_dpaqx_s_w_ph, mips_dpaqx_sa_w_ph): Likewise.
	(mips_dpsqx_s_w_ph, mips_dpsqx_sa_w_ph): Likewise.
	* config/mips/mips-fixed.md (usadd<mode>3): Remove explicit parallel.
	(ssadd<mode>3, ussub<mode>3, sssub<mode>3, ssmul<mode>3): Likewise.
	(ssmaddsqdq4, ssmsubsqdq4): Likewise.

From-SVN: r219639
parent 954bdd58
Showing with 443 additions and 471 deletions
gcc/ChangeLog
2015-01-15 Matthew Fortune <matthew.fortune@imgtec.com>
* config/mips/micromips.md (*swp): Remove explicit parallel.
(jraddiusp, *movep<MOVEP1:mode><MOVEP2:mode>): Likewise.
* config/mips/mips-dsp.md (add<DSPV:mode>3): Likewise.
(mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>, sub<DSPV:mode>3): Likewise.
(mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>, mips_addsc): Likewise.
(mips_addwc, mips_absq_s_<DSPQ:dspfmt2>): Likewise.
(mips_precrq_rs_ph_w, mips_precrqu_s_qb_ph): Likewise.
(mips_shll_<DSPV:dspfmt2>, mips_shll_s_<DSPQ:dspfmt2>): Likewise.
(mips_muleu_s_ph_qbl, mips_muleu_s_ph_qbr): Likewise.
(mips_mulq_rs_ph, mips_muleq_s_w_phl, mips_muleq_s_w_phr): Likewise.
(mips_dpaq_s_w_ph, mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph): Likewise.
(mips_dpaq_sa_l_w, mips_dpsq_sa_l_w, mips_maq_s_w_phl): Likewise.
(mips_maq_s_w_phr, mips_maq_sa_w_phl, mips_maq_sa_w_phr): Likewise.
(mips_extr_w, mips_extr_r_w, mips_extr_rs_w): Likewise.
(mips_extr_s_h, mips_extp, mips_extpdp, mips_mthlip): Likewise.
(mips_wrdsp): Likewise.
* config/mips/mips-dspr2.md (mips_absq_s_qb): Remove explicit
parallel.
(mips_addu_ph, mips_addu_s_ph, mips_cmpgdu_eq_qb): Likewise.
(mips_cmpgdu_lt_qb, mips_cmpgdu_le_qb, mulv2hi3): Likewise.
(mips_mul_s_ph, mips_mulq_rs_w, mips_mulq_s_ph): Likewise.
(mips_mulq_s_w, mips_subu_ph, mips_subu_s_ph): Likewise.
(mips_dpaqx_s_w_ph, mips_dpaqx_sa_w_ph): Likewise.
(mips_dpsqx_s_w_ph, mips_dpsqx_sa_w_ph): Likewise.
* config/mips/mips-fixed.md (usadd<mode>3): Remove explicit parallel.
(ssadd<mode>3, ussub<mode>3, sssub<mode>3, ssmul<mode>3): Likewise.
(ssmaddsqdq4, ssmsubsqdq4): Likewise.
2015-01-14 Matthew Fortune <matthew.fortune@imgtec.com> 2015-01-14 Matthew Fortune <matthew.fortune@imgtec.com>
* config/mips/mips.c (mips_rtx_costs): Set costs for LSA/DLSA. * config/mips/mips.c (mips_rtx_costs): Set costs for LSA/DLSA.
......
gcc/config/mips/micromips.md
...@@ -80,11 +80,10 @@ ...@@ -80,11 +80,10 @@
;; The behavior of the SWP insn is undefined if placed in a delay slot. ;; The behavior of the SWP insn is undefined if placed in a delay slot.
(define_insn "*swp" (define_insn "*swp"
[(parallel [(set (match_operand:SI 0 "non_volatile_mem_operand") [(set (match_operand:SI 0 "non_volatile_mem_operand")
(match_operand:SI 1 "d_operand")) (match_operand:SI 1 "d_operand"))
(set (match_operand:SI 2 "non_volatile_mem_operand") (set (match_operand:SI 2 "non_volatile_mem_operand")
(match_operand:SI 3 "d_operand"))])] (match_operand:SI 3 "d_operand"))]
"TARGET_MICROMIPS "TARGET_MICROMIPS
&& umips_load_store_pair_p (false, operands)" && umips_load_store_pair_p (false, operands)"
{ {
...@@ -97,11 +96,11 @@ ...@@ -97,11 +96,11 @@
;; For JRADDIUSP. ;; For JRADDIUSP.
(define_insn "jraddiusp" (define_insn "jraddiusp"
[(parallel [(return) [(return)
(use (reg:SI 31)) (use (reg:SI 31))
(set (reg:SI 29) (set (reg:SI 29)
(plus:SI (reg:SI 29) (plus:SI (reg:SI 29)
(match_operand 0 "uw5_operand")))])] (match_operand 0 "uw5_operand")))]
"TARGET_MICROMIPS" "TARGET_MICROMIPS"
"jraddiusp\t%0" "jraddiusp\t%0"
[(set_attr "type" "trap") [(set_attr "type" "trap")
...@@ -121,10 +120,10 @@ ...@@ -121,10 +120,10 @@
;; The behavior of the MOVEP insn is undefined if placed in a delay slot. ;; The behavior of the MOVEP insn is undefined if placed in a delay slot.
(define_insn "*movep<MOVEP1:mode><MOVEP2:mode>" (define_insn "*movep<MOVEP1:mode><MOVEP2:mode>"
[(parallel [(set (match_operand:MOVEP1 0 "register_operand") [(set (match_operand:MOVEP1 0 "register_operand")
(match_operand:MOVEP1 1 "movep_src_operand")) (match_operand:MOVEP1 1 "movep_src_operand"))
(set (match_operand:MOVEP2 2 "register_operand") (set (match_operand:MOVEP2 2 "register_operand")
(match_operand:MOVEP2 3 "movep_src_operand"))])] (match_operand:MOVEP2 3 "movep_src_operand"))]
"TARGET_MICROMIPS "TARGET_MICROMIPS
&& umips_movep_target_p (operands[0], operands[2])" && umips_movep_target_p (operands[0], operands[2])"
{ {
......
gcc/config/mips/mips-dsp.md
...@@ -126,25 +126,23 @@ ...@@ -126,25 +126,23 @@
;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic ;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic
;; ADDQ* ;; ADDQ*
(define_insn "add<DSPV:mode>3" (define_insn "add<DSPV:mode>3"
[(parallel [(set (match_operand:DSPV 0 "register_operand" "=d")
[(set (match_operand:DSPV 0 "register_operand" "=d") (plus:DSPV (match_operand:DSPV 1 "register_operand" "d")
(plus:DSPV (match_operand:DSPV 1 "register_operand" "d") (match_operand:DSPV 2 "register_operand" "d")))
(match_operand:DSPV 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>" (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>"
[(parallel [(set (match_operand:DSP 0 "register_operand" "=d")
[(set (match_operand:DSP 0 "register_operand" "=d") (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
(unspec:DSP [(match_operand:DSP 1 "register_operand" "d") (match_operand:DSP 2 "register_operand" "d")]
(match_operand:DSP 2 "register_operand" "d")] UNSPEC_ADDQ_S))
UNSPEC_ADDQ_S)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
[(set_attr "type" "dspalusat") [(set_attr "type" "dspalusat")
...@@ -152,25 +150,23 @@ ...@@ -152,25 +150,23 @@
;; SUBQ* ;; SUBQ*
(define_insn "sub<DSPV:mode>3" (define_insn "sub<DSPV:mode>3"
[(parallel [(set (match_operand:DSPV 0 "register_operand" "=d")
[(set (match_operand:DSPV 0 "register_operand" "=d") (minus:DSPV (match_operand:DSPV 1 "register_operand" "d")
(minus:DSPV (match_operand:DSPV 1 "register_operand" "d") (match_operand:DSPV 2 "register_operand" "d")))
(match_operand:DSPV 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>" (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>"
[(parallel [(set (match_operand:DSP 0 "register_operand" "=d")
[(set (match_operand:DSP 0 "register_operand" "=d") (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
(unspec:DSP [(match_operand:DSP 1 "register_operand" "d") (match_operand:DSP 2 "register_operand" "d")]
(match_operand:DSP 2 "register_operand" "d")] UNSPEC_SUBQ_S))
UNSPEC_SUBQ_S)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
[(set_attr "type" "dspalusat") [(set_attr "type" "dspalusat")
...@@ -178,13 +174,12 @@ ...@@ -178,13 +174,12 @@
;; ADDSC ;; ADDSC
(define_insn "mips_addsc" (define_insn "mips_addsc"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:SI 1 "register_operand" "d")
(unspec:SI [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")]
(match_operand:SI 2 "register_operand" "d")] UNSPEC_ADDSC))
UNSPEC_ADDSC)) (set (reg:CCDSP CCDSP_CA_REGNUM)
(set (reg:CCDSP CCDSP_CA_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"addsc\t%0,%1,%2" "addsc\t%0,%1,%2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
...@@ -192,14 +187,13 @@ ...@@ -192,14 +187,13 @@
;; ADDWC ;; ADDWC
(define_insn "mips_addwc" (define_insn "mips_addwc"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:SI 1 "register_operand" "d")
(unspec:SI [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d") (reg:CCDSP CCDSP_CA_REGNUM)]
(reg:CCDSP CCDSP_CA_REGNUM)] UNSPEC_ADDWC))
UNSPEC_ADDWC)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"addwc\t%0,%1,%2" "addwc\t%0,%1,%2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
...@@ -228,12 +222,11 @@ ...@@ -228,12 +222,11 @@
;; ABSQ* ;; ABSQ*
(define_insn "mips_absq_s_<DSPQ:dspfmt2>" (define_insn "mips_absq_s_<DSPQ:dspfmt2>"
[(parallel [(set (match_operand:DSPQ 0 "register_operand" "=d")
[(set (match_operand:DSPQ 0 "register_operand" "=d") (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")]
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")] UNSPEC_ABSQ_S))
UNSPEC_ABSQ_S)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))]
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"absq_s.<DSPQ:dspfmt2>\t%0,%1" "absq_s.<DSPQ:dspfmt2>\t%0,%1"
[(set_attr "type" "dspalusat") [(set_attr "type" "dspalusat")
...@@ -261,14 +254,13 @@ ...@@ -261,14 +254,13 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_precrq_rs_ph_w" (define_insn "mips_precrq_rs_ph_w"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
(unspec:V2HI [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")]
(match_operand:SI 2 "register_operand" "d")] UNSPEC_PRECRQ_RS_PH_W))
UNSPEC_PRECRQ_RS_PH_W)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_PRECRQ_RS_PH_W))]
UNSPEC_PRECRQ_RS_PH_W))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"precrq_rs.ph.w\t%0,%1,%2" "precrq_rs.ph.w\t%0,%1,%2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
...@@ -276,14 +268,13 @@ ...@@ -276,14 +268,13 @@
;; PRECRQU* ;; PRECRQU*
(define_insn "mips_precrqu_s_qb_ph" (define_insn "mips_precrqu_s_qb_ph"
[(parallel [(set (match_operand:V4QI 0 "register_operand" "=d")
[(set (match_operand:V4QI 0 "register_operand" "=d") (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
(unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")]
(match_operand:V2HI 2 "register_operand" "d")] UNSPEC_PRECRQU_S_QB_PH))
UNSPEC_PRECRQU_S_QB_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_PRECRQU_S_QB_PH))]
UNSPEC_PRECRQU_S_QB_PH))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"precrqu_s.qb.ph\t%0,%1,%2" "precrqu_s.qb.ph\t%0,%1,%2"
[(set_attr "type" "dspalusat") [(set_attr "type" "dspalusat")
...@@ -385,13 +376,12 @@ ...@@ -385,13 +376,12 @@
;; Table 2-2. MIPS DSP ASE Instructions: Shift ;; Table 2-2. MIPS DSP ASE Instructions: Shift
;; SHLL* ;; SHLL*
(define_insn "mips_shll_<DSPV:dspfmt2>" (define_insn "mips_shll_<DSPV:dspfmt2>"
[(parallel [(set (match_operand:DSPV 0 "register_operand" "=d,d")
[(set (match_operand:DSPV 0 "register_operand" "=d,d") (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d")
(unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d") (match_operand:SI 2 "arith_operand" "I,d")]
(match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHLL))
UNSPEC_SHLL)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
{ {
if (which_alternative == 0) if (which_alternative == 0)
...@@ -407,13 +397,12 @@ ...@@ -407,13 +397,12 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_shll_s_<DSPQ:dspfmt2>" (define_insn "mips_shll_s_<DSPQ:dspfmt2>"
[(parallel [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
[(set (match_operand:DSPQ 0 "register_operand" "=d,d") (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") (match_operand:SI 2 "arith_operand" "I,d")]
(match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHLL_S))
UNSPEC_SHLL_S)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
{ {
if (which_alternative == 0) if (which_alternative == 0)
...@@ -488,28 +477,26 @@ ...@@ -488,28 +477,26 @@
;; Table 2-3. MIPS DSP ASE Instructions: Multiply ;; Table 2-3. MIPS DSP ASE Instructions: Multiply
;; MULEU* ;; MULEU*
(define_insn "mips_muleu_s_ph_qbl" (define_insn "mips_muleu_s_ph_qbl"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")]
(match_operand:V2HI 2 "register_operand" "d")] UNSPEC_MULEU_S_PH_QBL))
UNSPEC_MULEU_S_PH_QBL)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"muleu_s.ph.qbl\t%0,%1,%2" "muleu_s.ph.qbl\t%0,%1,%2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_muleu_s_ph_qbr" (define_insn "mips_muleu_s_ph_qbr"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")]
(match_operand:V2HI 2 "register_operand" "d")] UNSPEC_MULEU_S_PH_QBR))
UNSPEC_MULEU_S_PH_QBR)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"muleu_s.ph.qbr\t%0,%1,%2" "muleu_s.ph.qbr\t%0,%1,%2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
...@@ -517,14 +504,13 @@ ...@@ -517,14 +504,13 @@
;; MULQ* ;; MULQ*
(define_insn "mips_mulq_rs_ph" (define_insn "mips_mulq_rs_ph"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")]
(match_operand:V2HI 2 "register_operand" "d")] UNSPEC_MULQ_RS_PH))
UNSPEC_MULQ_RS_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"mulq_rs.ph\t%0,%1,%2" "mulq_rs.ph\t%0,%1,%2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
...@@ -532,28 +518,26 @@ ...@@ -532,28 +518,26 @@
;; MULEQ* ;; MULEQ*
(define_insn "mips_muleq_s_w_phl" (define_insn "mips_muleq_s_w_phl"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")]
(match_operand:V2HI 2 "register_operand" "d")] UNSPEC_MULEQ_S_W_PHL))
UNSPEC_MULEQ_S_W_PHL)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"muleq_s.w.phl\t%0,%1,%2" "muleq_s.w.phl\t%0,%1,%2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_muleq_s_w_phr" (define_insn "mips_muleq_s_w_phr"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")]
(match_operand:V2HI 2 "register_operand" "d")] UNSPEC_MULEQ_S_W_PHR))
UNSPEC_MULEQ_S_W_PHR)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"muleq_s.w.phr\t%0,%1,%2" "muleq_s.w.phr\t%0,%1,%2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
...@@ -611,15 +595,14 @@ ...@@ -611,15 +595,14 @@
;; DPAQ* ;; DPAQ*
(define_insn "mips_dpaq_s_w_ph" (define_insn "mips_dpaq_s_w_ph"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d") (match_operand:V2HI 3 "register_operand" "d")]
(match_operand:V2HI 3 "register_operand" "d")] UNSPEC_DPAQ_S_W_PH))
UNSPEC_DPAQ_S_W_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQ_S_W_PH))]
UNSPEC_DPAQ_S_W_PH))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"dpaq_s.w.ph\t%q0,%2,%3" "dpaq_s.w.ph\t%q0,%2,%3"
[(set_attr "type" "dspmac") [(set_attr "type" "dspmac")
...@@ -628,15 +611,14 @@ ...@@ -628,15 +611,14 @@
;; DPSQ* ;; DPSQ*
(define_insn "mips_dpsq_s_w_ph" (define_insn "mips_dpsq_s_w_ph"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d") (match_operand:V2HI 3 "register_operand" "d")]
(match_operand:V2HI 3 "register_operand" "d")] UNSPEC_DPSQ_S_W_PH))
UNSPEC_DPSQ_S_W_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQ_S_W_PH))]
UNSPEC_DPSQ_S_W_PH))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"dpsq_s.w.ph\t%q0,%2,%3" "dpsq_s.w.ph\t%q0,%2,%3"
[(set_attr "type" "dspmac") [(set_attr "type" "dspmac")
...@@ -645,15 +627,14 @@ ...@@ -645,15 +627,14 @@
;; MULSAQ* ;; MULSAQ*
(define_insn "mips_mulsaq_s_w_ph" (define_insn "mips_mulsaq_s_w_ph"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d") (match_operand:V2HI 3 "register_operand" "d")]
(match_operand:V2HI 3 "register_operand" "d")] UNSPEC_MULSAQ_S_W_PH))
UNSPEC_MULSAQ_S_W_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MULSAQ_S_W_PH))]
UNSPEC_MULSAQ_S_W_PH))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"mulsaq_s.w.ph\t%q0,%2,%3" "mulsaq_s.w.ph\t%q0,%2,%3"
[(set_attr "type" "dspmac") [(set_attr "type" "dspmac")
...@@ -662,15 +643,14 @@ ...@@ -662,15 +643,14 @@
;; DPAQ* ;; DPAQ*
(define_insn "mips_dpaq_sa_l_w" (define_insn "mips_dpaq_sa_l_w"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d")]
(match_operand:SI 3 "register_operand" "d")] UNSPEC_DPAQ_SA_L_W))
UNSPEC_DPAQ_SA_L_W)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQ_SA_L_W))]
UNSPEC_DPAQ_SA_L_W))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"dpaq_sa.l.w\t%q0,%2,%3" "dpaq_sa.l.w\t%q0,%2,%3"
[(set_attr "type" "dspmacsat") [(set_attr "type" "dspmacsat")
...@@ -679,15 +659,14 @@ ...@@ -679,15 +659,14 @@
;; DPSQ* ;; DPSQ*
(define_insn "mips_dpsq_sa_l_w" (define_insn "mips_dpsq_sa_l_w"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d")]
(match_operand:SI 3 "register_operand" "d")] UNSPEC_DPSQ_SA_L_W))
UNSPEC_DPSQ_SA_L_W)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQ_SA_L_W))]
UNSPEC_DPSQ_SA_L_W))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"dpsq_sa.l.w\t%q0,%2,%3" "dpsq_sa.l.w\t%q0,%2,%3"
[(set_attr "type" "dspmacsat") [(set_attr "type" "dspmacsat")
...@@ -696,15 +675,14 @@ ...@@ -696,15 +675,14 @@
;; MAQ* ;; MAQ*
(define_insn "mips_maq_s_w_phl" (define_insn "mips_maq_s_w_phl"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d") (match_operand:V2HI 3 "register_operand" "d")]
(match_operand:V2HI 3 "register_operand" "d")] UNSPEC_MAQ_S_W_PHL))
UNSPEC_MAQ_S_W_PHL)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MAQ_S_W_PHL))]
UNSPEC_MAQ_S_W_PHL))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"maq_s.w.phl\t%q0,%2,%3" "maq_s.w.phl\t%q0,%2,%3"
[(set_attr "type" "dspmac") [(set_attr "type" "dspmac")
...@@ -712,15 +690,14 @@ ...@@ -712,15 +690,14 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_maq_s_w_phr" (define_insn "mips_maq_s_w_phr"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d") (match_operand:V2HI 3 "register_operand" "d")]
(match_operand:V2HI 3 "register_operand" "d")] UNSPEC_MAQ_S_W_PHR))
UNSPEC_MAQ_S_W_PHR)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MAQ_S_W_PHR))]
UNSPEC_MAQ_S_W_PHR))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"maq_s.w.phr\t%q0,%2,%3" "maq_s.w.phr\t%q0,%2,%3"
[(set_attr "type" "dspmac") [(set_attr "type" "dspmac")
...@@ -729,15 +706,14 @@ ...@@ -729,15 +706,14 @@
;; MAQ_SA* ;; MAQ_SA*
(define_insn "mips_maq_sa_w_phl" (define_insn "mips_maq_sa_w_phl"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d") (match_operand:V2HI 3 "register_operand" "d")]
(match_operand:V2HI 3 "register_operand" "d")] UNSPEC_MAQ_SA_W_PHL))
UNSPEC_MAQ_SA_W_PHL)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MAQ_SA_W_PHL))]
UNSPEC_MAQ_SA_W_PHL))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"maq_sa.w.phl\t%q0,%2,%3" "maq_sa.w.phl\t%q0,%2,%3"
[(set_attr "type" "dspmacsat") [(set_attr "type" "dspmacsat")
...@@ -745,15 +721,14 @@ ...@@ -745,15 +721,14 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_maq_sa_w_phr" (define_insn "mips_maq_sa_w_phr"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d") (match_operand:V2HI 3 "register_operand" "d")]
(match_operand:V2HI 3 "register_operand" "d")] UNSPEC_MAQ_SA_W_PHR))
UNSPEC_MAQ_SA_W_PHR)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MAQ_SA_W_PHR))]
UNSPEC_MAQ_SA_W_PHR))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"maq_sa.w.phr\t%q0,%2,%3" "maq_sa.w.phr\t%q0,%2,%3"
[(set_attr "type" "dspmacsat") [(set_attr "type" "dspmacsat")
...@@ -904,13 +879,12 @@ ...@@ -904,13 +879,12 @@
;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
;; EXTR* ;; EXTR*
(define_insn "mips_extr_w" (define_insn "mips_extr_w"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d,d")
[(set (match_operand:SI 0 "register_operand" "=d,d") (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a") (match_operand:SI 2 "arith_operand" "I,d")]
(match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_EXTR_W))
UNSPEC_EXTR_W)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
{ {
if (which_alternative == 0) if (which_alternative == 0)
...@@ -925,13 +899,12 @@ ...@@ -925,13 +899,12 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_extr_r_w" (define_insn "mips_extr_r_w"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d,d")
[(set (match_operand:SI 0 "register_operand" "=d,d") (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a") (match_operand:SI 2 "arith_operand" "I,d")]
(match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_EXTR_R_W))
UNSPEC_EXTR_R_W)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
{ {
if (which_alternative == 0) if (which_alternative == 0)
...@@ -946,13 +919,12 @@ ...@@ -946,13 +919,12 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_extr_rs_w" (define_insn "mips_extr_rs_w"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d,d")
[(set (match_operand:SI 0 "register_operand" "=d,d") (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a") (match_operand:SI 2 "arith_operand" "I,d")]
(match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_EXTR_RS_W))
UNSPEC_EXTR_RS_W)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
{ {
if (which_alternative == 0) if (which_alternative == 0)
...@@ -968,13 +940,12 @@ ...@@ -968,13 +940,12 @@
;; EXTR*_S.H ;; EXTR*_S.H
(define_insn "mips_extr_s_h" (define_insn "mips_extr_s_h"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d,d")
[(set (match_operand:SI 0 "register_operand" "=d,d") (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a") (match_operand:SI 2 "arith_operand" "I,d")]
(match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_EXTR_S_H))
UNSPEC_EXTR_S_H)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
{ {
if (which_alternative == 0) if (which_alternative == 0)
...@@ -990,14 +961,13 @@ ...@@ -990,14 +961,13 @@
;; EXTP* ;; EXTP*
(define_insn "mips_extp" (define_insn "mips_extp"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d,d")
[(set (match_operand:SI 0 "register_operand" "=d,d") (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a") (match_operand:SI 2 "arith_operand" "I,d")
(match_operand:SI 2 "arith_operand" "I,d") (reg:CCDSP CCDSP_PO_REGNUM)]
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTP))
UNSPEC_EXTP)) (set (reg:CCDSP CCDSP_EF_REGNUM)
(set (reg:CCDSP CCDSP_EF_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
{ {
if (which_alternative == 0) if (which_alternative == 0)
...@@ -1012,17 +982,16 @@ ...@@ -1012,17 +982,16 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_extpdp" (define_insn "mips_extpdp"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d,d")
[(set (match_operand:SI 0 "register_operand" "=d,d") (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a") (match_operand:SI 2 "arith_operand" "I,d")
(match_operand:SI 2 "arith_operand" "I,d") (reg:CCDSP CCDSP_PO_REGNUM)]
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
UNSPEC_EXTPDP)) (set (reg:CCDSP CCDSP_PO_REGNUM)
(set (reg:CCDSP CCDSP_PO_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP)) (set (reg:CCDSP CCDSP_EF_REGNUM)
(set (reg:CCDSP CCDSP_EF_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
{ {
if (which_alternative == 0) if (which_alternative == 0)
...@@ -1057,15 +1026,14 @@ ...@@ -1057,15 +1026,14 @@
;; MTHLIP* ;; MTHLIP*
(define_insn "mips_mthlip" (define_insn "mips_mthlip"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d") (reg:CCDSP CCDSP_PO_REGNUM)]
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))
UNSPEC_MTHLIP)) (set (reg:CCDSP CCDSP_PO_REGNUM)
(set (reg:CCDSP CCDSP_PO_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))]
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"mthlip\t%2,%q0" "mthlip\t%2,%q0"
[(set_attr "type" "accmod") [(set_attr "type" "accmod")
...@@ -1073,21 +1041,20 @@ ...@@ -1073,21 +1041,20 @@
;; WRDSP ;; WRDSP
(define_insn "mips_wrdsp" (define_insn "mips_wrdsp"
[(parallel [(set (reg:CCDSP CCDSP_PO_REGNUM)
[(set (reg:CCDSP CCDSP_PO_REGNUM) (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d")
(unspec:CCDSP [(match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "const_uimm6_operand" "YA")]
(match_operand:SI 1 "const_uimm6_operand" "YA")] UNSPEC_WRDSP))
UNSPEC_WRDSP)) (set (reg:CCDSP CCDSP_SC_REGNUM)
(set (reg:CCDSP CCDSP_SC_REGNUM) (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) (set (reg:CCDSP CCDSP_CA_REGNUM)
(set (reg:CCDSP CCDSP_CA_REGNUM) (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) (set (reg:CCDSP CCDSP_CC_REGNUM)
(set (reg:CCDSP CCDSP_CC_REGNUM) (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) (set (reg:CCDSP CCDSP_EF_REGNUM)
(set (reg:CCDSP CCDSP_EF_REGNUM) (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))]
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"wrdsp\t%0,%1" "wrdsp\t%0,%1"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
......
gcc/config/mips/mips-dspr2.md
...@@ -71,37 +71,34 @@ ...@@ -71,37 +71,34 @@
]) ])
(define_insn "mips_absq_s_qb" (define_insn "mips_absq_s_qb"
[(parallel [(set (match_operand:V4QI 0 "register_operand" "=d")
[(set (match_operand:V4QI 0 "register_operand" "=d") (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")] UNSPEC_ABSQ_S_QB))
UNSPEC_ABSQ_S_QB)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))]
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"absq_s.qb\t%0,%z1" "absq_s.qb\t%0,%z1"
[(set_attr "type" "dspalusat") [(set_attr "type" "dspalusat")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_addu_ph" (define_insn "mips_addu_ph"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
(match_operand:V2HI 2 "reg_or_0_operand" "dYG"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"addu.ph\t%0,%z1,%z2" "addu.ph\t%0,%z1,%z2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_addu_s_ph" (define_insn "mips_addu_s_ph"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_ADDU_S_PH))
UNSPEC_ADDU_S_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"addu_s.ph\t%0,%z1,%z2" "addu_s.ph\t%0,%z1,%z2"
[(set_attr "type" "dspalusat") [(set_attr "type" "dspalusat")
...@@ -158,45 +155,42 @@ ...@@ -158,45 +155,42 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_eq_qb" (define_insn "mips_cmpgdu_eq_qb"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")] UNSPEC_CMPGDU_EQ_QB))
UNSPEC_CMPGDU_EQ_QB)) (set (reg:CCDSP CCDSP_CC_REGNUM)
(set (reg:CCDSP CCDSP_CC_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_CC_REGNUM)]
(reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMPGDU_EQ_QB))]
UNSPEC_CMPGDU_EQ_QB))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"cmpgdu.eq.qb\t%0,%z1,%z2" "cmpgdu.eq.qb\t%0,%z1,%z2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_lt_qb" (define_insn "mips_cmpgdu_lt_qb"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")] UNSPEC_CMPGDU_LT_QB))
UNSPEC_CMPGDU_LT_QB)) (set (reg:CCDSP CCDSP_CC_REGNUM)
(set (reg:CCDSP CCDSP_CC_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_CC_REGNUM)]
(reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMPGDU_LT_QB))]
UNSPEC_CMPGDU_LT_QB))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"cmpgdu.lt.qb\t%0,%z1,%z2" "cmpgdu.lt.qb\t%0,%z1,%z2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_le_qb" (define_insn "mips_cmpgdu_le_qb"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")] UNSPEC_CMPGDU_LE_QB))
UNSPEC_CMPGDU_LE_QB)) (set (reg:CCDSP CCDSP_CC_REGNUM)
(set (reg:CCDSP CCDSP_CC_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_CC_REGNUM)]
(reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMPGDU_LE_QB))]
UNSPEC_CMPGDU_LE_QB))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"cmpgdu.le.qb\t%0,%z1,%z2" "cmpgdu.le.qb\t%0,%z1,%z2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
...@@ -227,69 +221,64 @@ ...@@ -227,69 +221,64 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mulv2hi3" (define_insn "mulv2hi3"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
(mult:V2HI (match_operand:V2HI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")))
(match_operand:V2HI 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"mul.ph\t%0,%1,%2" "mul.ph\t%0,%1,%2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_mul_s_ph" (define_insn "mips_mul_s_ph"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_MUL_S_PH))
UNSPEC_MUL_S_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"mul_s.ph\t%0,%z1,%z2" "mul_s.ph\t%0,%z1,%z2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_mulq_rs_w" (define_insn "mips_mulq_rs_w"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") (match_operand:SI 2 "reg_or_0_operand" "dJ")]
(match_operand:SI 2 "reg_or_0_operand" "dJ")] UNSPEC_MULQ_RS_W))
UNSPEC_MULQ_RS_W)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"mulq_rs.w\t%0,%z1,%z2" "mulq_rs.w\t%0,%z1,%z2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_mulq_s_ph" (define_insn "mips_mulq_s_ph"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_MULQ_S_PH))
UNSPEC_MULQ_S_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"mulq_s.ph\t%0,%z1,%z2" "mulq_s.ph\t%0,%z1,%z2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_mulq_s_w" (define_insn "mips_mulq_s_w"
[(parallel [(set (match_operand:SI 0 "register_operand" "=d")
[(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") (match_operand:SI 2 "reg_or_0_operand" "dJ")]
(match_operand:SI 2 "reg_or_0_operand" "dJ")] UNSPEC_MULQ_S_W))
UNSPEC_MULQ_S_W)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"mulq_s.w\t%0,%z1,%z2" "mulq_s.w\t%0,%z1,%z2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
...@@ -418,26 +407,24 @@ ...@@ -418,26 +407,24 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_subu_ph" (define_insn "mips_subu_ph"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_SUBU_PH))
UNSPEC_SUBU_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"subu.ph\t%0,%z1,%z2" "subu.ph\t%0,%z1,%z2"
[(set_attr "type" "dspalu") [(set_attr "type" "dspalu")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_subu_s_ph" (define_insn "mips_subu_s_ph"
[(parallel [(set (match_operand:V2HI 0 "register_operand" "=d")
[(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_SUBU_S_PH))
UNSPEC_SUBU_S_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
"ISA_HAS_DSPR2" "ISA_HAS_DSPR2"
"subu_s.ph\t%0,%z1,%z2" "subu_s.ph\t%0,%z1,%z2"
[(set_attr "type" "dspalusat") [(set_attr "type" "dspalusat")
...@@ -568,15 +555,14 @@ ...@@ -568,15 +555,14 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_dpaqx_s_w_ph" (define_insn "mips_dpaqx_s_w_ph"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_DPAQX_S_W_PH))
UNSPEC_DPAQX_S_W_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQX_S_W_PH))]
UNSPEC_DPAQX_S_W_PH))])]
"ISA_HAS_DSPR2 && !TARGET_64BIT" "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpaqx_s.w.ph\t%q0,%z2,%z3" "dpaqx_s.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "dspmac") [(set_attr "type" "dspmac")
...@@ -584,15 +570,14 @@ ...@@ -584,15 +570,14 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_dpaqx_sa_w_ph" (define_insn "mips_dpaqx_sa_w_ph"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_DPAQX_SA_W_PH))
UNSPEC_DPAQX_SA_W_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQX_SA_W_PH))]
UNSPEC_DPAQX_SA_W_PH))])]
"ISA_HAS_DSPR2 && !TARGET_64BIT" "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpaqx_sa.w.ph\t%q0,%z2,%z3" "dpaqx_sa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "dspmacsat") [(set_attr "type" "dspmacsat")
...@@ -600,15 +585,14 @@ ...@@ -600,15 +585,14 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_dpsqx_s_w_ph" (define_insn "mips_dpsqx_s_w_ph"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_DPSQX_S_W_PH))
UNSPEC_DPSQX_S_W_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQX_S_W_PH))]
UNSPEC_DPSQX_S_W_PH))])]
"ISA_HAS_DSPR2 && !TARGET_64BIT" "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsqx_s.w.ph\t%q0,%z2,%z3" "dpsqx_s.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "dspmac") [(set_attr "type" "dspmac")
...@@ -616,15 +600,14 @@ ...@@ -616,15 +600,14 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "mips_dpsqx_sa_w_ph" (define_insn "mips_dpsqx_sa_w_ph"
[(parallel [(set (match_operand:DI 0 "register_operand" "=a")
[(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI [(match_operand:DI 1 "register_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_DPSQX_SA_W_PH))
UNSPEC_DPSQX_SA_W_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQX_SA_W_PH))]
UNSPEC_DPSQX_SA_W_PH))])]
"ISA_HAS_DSPR2 && !TARGET_64BIT" "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsqx_sa.w.ph\t%q0,%z2,%z3" "dpsqx_sa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "dspmacsat") [(set_attr "type" "dspmacsat")
......
gcc/config/mips/mips-fixed.md
...@@ -52,24 +52,22 @@ ...@@ -52,24 +52,22 @@
(set_attr "mode" "<IMODE>")]) (set_attr "mode" "<IMODE>")])
(define_insn "usadd<mode>3" (define_insn "usadd<mode>3"
[(parallel [(set (match_operand:UADDSUB 0 "register_operand" "=d")
[(set (match_operand:UADDSUB 0 "register_operand" "=d") (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
(us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") (match_operand:UADDSUB 2 "register_operand" "d")))
(match_operand:UADDSUB 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
"" ""
"addu_s.<uaddsubfmt>\t%0,%1,%2" "addu_s.<uaddsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith") [(set_attr "type" "arith")
(set_attr "mode" "<IMODE>")]) (set_attr "mode" "<IMODE>")])
(define_insn "ssadd<mode>3" (define_insn "ssadd<mode>3"
[(parallel [(set (match_operand:ADDSUB 0 "register_operand" "=d")
[(set (match_operand:ADDSUB 0 "register_operand" "=d") (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
(ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") (match_operand:ADDSUB 2 "register_operand" "d")))
(match_operand:ADDSUB 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"addq_s.<addsubfmt>\t%0,%1,%2" "addq_s.<addsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith") [(set_attr "type" "arith")
...@@ -85,71 +83,66 @@ ...@@ -85,71 +83,66 @@
(set_attr "mode" "<IMODE>")]) (set_attr "mode" "<IMODE>")])
(define_insn "ussub<mode>3" (define_insn "ussub<mode>3"
[(parallel [(set (match_operand:UADDSUB 0 "register_operand" "=d")
[(set (match_operand:UADDSUB 0 "register_operand" "=d") (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
(us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") (match_operand:UADDSUB 2 "register_operand" "d")))
(match_operand:UADDSUB 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
"" ""
"subu_s.<uaddsubfmt>\t%0,%1,%2" "subu_s.<uaddsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith") [(set_attr "type" "arith")
(set_attr "mode" "<IMODE>")]) (set_attr "mode" "<IMODE>")])
(define_insn "sssub<mode>3" (define_insn "sssub<mode>3"
[(parallel [(set (match_operand:ADDSUB 0 "register_operand" "=d")
[(set (match_operand:ADDSUB 0 "register_operand" "=d") (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
(ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") (match_operand:ADDSUB 2 "register_operand" "d")))
(match_operand:ADDSUB 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
"ISA_HAS_DSP" "ISA_HAS_DSP"
"subq_s.<addsubfmt>\t%0,%1,%2" "subq_s.<addsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith") [(set_attr "type" "arith")
(set_attr "mode" "<IMODE>")]) (set_attr "mode" "<IMODE>")])
(define_insn "ssmul<mode>3" (define_insn "ssmul<mode>3"
[(parallel [(set (match_operand:MULQ 0 "register_operand" "=d")
[(set (match_operand:MULQ 0 "register_operand" "=d") (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d")
(ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d") (match_operand:MULQ 2 "register_operand" "d")))
(match_operand:MULQ 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) (clobber (match_scratch:DI 3 "=x"))]
(clobber (match_scratch:DI 3 "=x"))])]
"" ""
"mulq_rs.<mulqfmt>\t%0,%1,%2" "mulq_rs.<mulqfmt>\t%0,%1,%2"
[(set_attr "type" "imul3") [(set_attr "type" "imul3")
(set_attr "mode" "<IMODE>")]) (set_attr "mode" "<IMODE>")])
(define_insn "ssmaddsqdq4" (define_insn "ssmaddsqdq4"
[(parallel [(set (match_operand:DQ 0 "register_operand" "=a")
[(set (match_operand:DQ 0 "register_operand" "=a") (ss_plus:DQ
(ss_plus:DQ (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
(ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 "register_operand" "d"))
"register_operand" "d")) (sat_fract:DQ (match_operand:SQ 2
(sat_fract:DQ (match_operand:SQ 2 "register_operand" "d")))
"register_operand" "d"))) (match_operand:DQ 3 "register_operand" "0")))
(match_operand:DQ 3 "register_operand" "0"))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQ_SA_L_W))]
UNSPEC_DPAQ_SA_L_W))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"dpaq_sa.l.w\t%q0,%1,%2" "dpaq_sa.l.w\t%q0,%1,%2"
[(set_attr "type" "imadd") [(set_attr "type" "imadd")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "ssmsubsqdq4" (define_insn "ssmsubsqdq4"
[(parallel [(set (match_operand:DQ 0 "register_operand" "=a")
[(set (match_operand:DQ 0 "register_operand" "=a") (ss_minus:DQ
(ss_minus:DQ (match_operand:DQ 3 "register_operand" "0")
(match_operand:DQ 3 "register_operand" "0") (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
(ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 "register_operand" "d"))
"register_operand" "d")) (sat_fract:DQ (match_operand:SQ 2
(sat_fract:DQ (match_operand:SQ 2 "register_operand" "d")))))
"register_operand" "d"))))) (set (reg:CCDSP CCDSP_OU_REGNUM)
(set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQ_SA_L_W))]
UNSPEC_DPSQ_SA_L_W))])]
"ISA_HAS_DSP && !TARGET_64BIT" "ISA_HAS_DSP && !TARGET_64BIT"
"dpsq_sa.l.w\t%q0,%1,%2" "dpsq_sa.l.w\t%q0,%1,%2"
[(set_attr "type" "imadd") [(set_attr "type" "imadd")
......
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