constraints.md: Allow post_inc operand for "Ya" constraint.

2019-10-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* config/msp430/constraints.md: Allow post_inc operand for "Ya"
	constraint.
	* config/msp430/msp430.c (msp430_legitimate_address_p): Handle
	POST_INC.
	(msp430_subreg): Likewise.
	(msp430_split_addsi): Likewise.
	(msp430_print_operand_addr): Likewise.
	* config/msp430/msp430.h (HAVE_POST_INCREMENT): Define.
	(USE_STORE_POST_INCREMENT): Define.
	* config/msp430/msp430.md: Use the msp430_general_dst_operand or
	msp430_general_dst_nonv_operand predicates for the lvalues of insns.
	* config/msp430/predicates.md (msp430_nonpostinc_operand): New.
	(msp430_general_dst_operand): New.
	(msp430_general_dst_nonv_operand): New.
	(msp430_nonsubreg_operand): Remove.
	(msp430_nonsubreg_dst_operand): New.
	(msp430_nonsubreg_or_imm_operand): Allow reg or mem operands in place
	of defunct msp430_nonsubreg_operand.
	(msp430_nonsubregnonpostinc_or_imm_operand): New.

From-SVN: r276995

gcc/ChangeLog

+2019-10-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
+
+	* config/msp430/constraints.md: Allow post_inc operand for "Ya"
+	constraint.
+	* config/msp430/msp430.c (msp430_legitimate_address_p): Handle
+	POST_INC.
+	(msp430_subreg): Likewise.
+	(msp430_split_addsi): Likewise.
+	(msp430_print_operand_addr): Likewise.
+	* config/msp430/msp430.h (HAVE_POST_INCREMENT): Define.
+	(USE_STORE_POST_INCREMENT): Define.
+	* config/msp430/msp430.md: Use the msp430_general_dst_operand or
+	msp430_general_dst_nonv_operand predicates for the lvalues of insns.
+	* config/msp430/predicates.md (msp430_nonpostinc_operand): New.
+	(msp430_general_dst_operand): New.
+	(msp430_general_dst_nonv_operand): New.
+	(msp430_nonsubreg_operand): Remove.
+	(msp430_nonsubreg_dst_operand): New.
+	(msp430_nonsubreg_or_imm_operand): Allow reg or mem operands in place
+	of defunct msp430_nonsubreg_operand.
+	(msp430_nonsubregnonpostinc_or_imm_operand): New.
+
 2019-10-15  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/91929

gcc/config/msp430/constraints.md

@@ -60,6 +60,7 @@
 		 (match_code "reg" "00")
 		 (match_test ("CONST_INT_P (XEXP (XEXP (op, 0), 1))")))
 	    (match_test "CONSTANT_P (XEXP (op, 0))")
+	    (match_code "post_inc" "0")
 	    )))
 
 (define_constraint "Yl"

gcc/config/msp430/msp430.c

@@ -942,12 +942,17 @@ msp430_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED,
       return false;
 
     case PLUS:
+    case POST_INC:
       if (REG_P (XEXP (x, 0)))
 	{
 	  if (GET_MODE (x) != GET_MODE (XEXP (x, 0)))
 	    return false;
 	  if (!reg_ok_for_addr (XEXP (x, 0), strict))
 	    return false;
+	  if (GET_CODE (x) == POST_INC)
+	    /* At this point, if the original rtx was a post_inc, we don't have
+	       anything further to check.  */
+	    return true;
 	  switch (GET_CODE (XEXP (x, 1)))
 	    {
 	    case CONST:
@@ -2810,6 +2815,7 @@ rtx
 msp430_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
 {
   rtx rv;
+  gcc_assert (mode == HImode);
 
   if (GET_CODE (r) == SUBREG
       && SUBREG_BYTE (r) == 0)
@@ -2826,7 +2832,15 @@ msp430_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
 	rv = simplify_gen_subreg (mode, ireg, imode, byte);
     }
   else if (GET_CODE (r) == MEM)
+    {
+      /* When byte == 2, we can be certain that we were already called with an
+	 identical rtx with byte == 0.  So we don't need to do anything to
+	 get a 2 byte offset of a (mem (post_inc)) rtx, since the address has
+	 already been offset by the post_inc itself.  */
+      if (GET_CODE (XEXP (r, 0)) == POST_INC && byte == 2)
+	byte = 0;
       rv = adjust_address (r, mode, byte);
+    }
   else if (GET_CODE (r) == SYMBOL_REF
 	   && (byte == 0 || byte == 2)
 	   && mode == HImode)
@@ -2861,6 +2875,18 @@ msp430_split_addsi (rtx *operands)
 
   if (GET_CODE (operands[5]) == CONST_INT)
     operands[9] = GEN_INT (INTVAL (operands[5]) & 0xffff);
+  /* Handle post_inc, for example:
+     (set (reg:SI)
+	  (plus:SI (reg:SI)
+		   (mem:SI (post_inc:PSI (reg:PSI))))).  */
+  else if (MEM_P (operands[5]) && GET_CODE (XEXP (operands[5], 0)) == POST_INC)
+    {
+      /* Strip out the post_inc from (mem (post_inc (reg))).  */
+      operands[9] = XEXP (XEXP (operands[5], 0), 0);
+      operands[9] = gen_rtx_MEM (HImode, operands[9]);
+      /* Then zero extend as normal.  */
+      operands[9] = gen_rtx_ZERO_EXTEND (SImode, operands[9]);
+    }
   else
     operands[9] = gen_rtx_ZERO_EXTEND (SImode, operands[5]);
   return 0;
@@ -3205,6 +3231,10 @@ msp430_print_operand_addr (FILE * file, machine_mode /*mode*/, rtx addr)
       fprintf (file, "@");
       break;
 
+    case POST_INC:
+      fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
+      return;
+
     case CONST:
     case CONST_INT:
     case SYMBOL_REF:

gcc/config/msp430/msp430.h

@@ -478,6 +478,18 @@ typedef struct
 
 #define ACCUMULATE_OUTGOING_ARGS 1
 
+#define HAVE_POST_INCREMENT 1
+
+/* This (unsurprisingly) improves code size in the vast majority of cases, we
+   want to prevent any instructions using a "store post increment" from being
+   generated.  These will have to later be reloaded since msp430 does not
+   support post inc for the destination operand.  */
+#define USE_STORE_POST_INCREMENT(MODE)  0
+
+/* Many other targets set USE_LOAD_POST_INCREMENT to 0.  For msp430-elf
+   the benefit of disabling it is not clear.  When looking at code size, on
+   average, there is a slight advantage to leaving it enabled.  */
+
 #undef  ASM_DECLARE_FUNCTION_NAME
 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
   msp430_start_function ((FILE), (NAME), (DECL))

gcc/config/msp430/predicates.md

@@ -23,21 +23,50 @@
        (match_test ("memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0), MEM_ADDR_SPACE (op))")))
 )
 
+; TRUE if neither op nor op0 are a post_inc.  We cannot use post_inc for the
+; dst operand so this must be used for any predicates which might allow a mem.
+; Since we check both op and op0, this will be FALSE for both "(post_inc)" and
+; "(mem (post_inc))"
+(define_predicate "msp430_nonpostinc_operand"
+  (not (ior (match_code "post_inc")
+	    (and (ior (match_operand 0 "msp430_volatile_memory_operand")
+		      (match_code "mem"))
+		 (match_code "post_inc" "0")))))
+
 ; TRUE for any valid general operand.  We do this because
 ; general_operand refuses to match volatile memory refs.
-
 (define_predicate "msp430_general_operand"
   (ior (match_operand 0 "general_operand")
        (match_operand 0 "msp430_volatile_memory_operand"))
 )
 
 ; Likewise for nonimmediate_operand.
-
 (define_predicate "msp430_nonimmediate_operand"
   (ior (match_operand 0 "nonimmediate_operand")
        (match_operand 0 "msp430_volatile_memory_operand"))
 )
 
+; Similar to msp430_nonimmediate_operand but disallow post_inc operands
+(define_predicate "msp430_general_dst_operand"
+  (and (match_operand 0 "msp430_nonpostinc_operand")
+       (match_operand 0 "msp430_nonimmediate_operand")))
+
+; Similar to msp430_general_dst_operand but disallow volatile memory references
+; Note that msp430_nonpostinc_operand will allow a volatile mem but nonimmediate
+; will not, so overall this predicate will behave as expected.
+; The heuristic for deciding if we can allow volatile memory appears to be:
+;   "If the number of references to the variable in the source code matches
+;    the number of references to the variable in the assembly template, we can
+;    safely allow a volatile memory reference".
+;      - paraphrasing DJ Delorie here:
+;	 https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00870.html
+; When applied to instruction patterns, this means that we can only allow
+; volatile memory when the output assembler template contains only one
+; instruction which references that volatile address.
+(define_predicate "msp430_general_dst_nonv_operand"
+  (and (match_operand 0 "msp430_nonpostinc_operand")
+       (match_operand 0 "nonimmediate_operand")))
+
 (define_predicate "ubyte_operand"
   (and (match_code "const_int")
        (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
@@ -70,13 +99,20 @@
 		     || INTVAL (op) == ~8
 		     || INTVAL (op) == ~(-1) "))))
 
-(define_predicate "msp430_nonsubreg_operand"
-  (match_code "reg,mem"))
+; See above note on post_inc
+(define_predicate "msp430_nonsubreg_dst_operand"
+  (and (match_operand 0 "msp430_nonpostinc_operand")
+       (match_code "reg,mem")))
 
 (define_predicate "msp430_nonsubreg_or_imm_operand"
-  (ior (match_operand 0 "msp430_nonsubreg_operand")
+  (ior (match_code "reg,mem")
        (match_operand 0 "immediate_operand")))
 
+(define_predicate "msp430_nonsubregnonpostinc_or_imm_operand"
+  (and (match_operand 0 "msp430_nonpostinc_operand")
+       (ior (match_code "reg,mem")
+	    (match_operand 0 "immediate_operand"))))
+
 ; TRUE for constants which are bit positions for zero_extract
 (define_predicate "msp430_bitpos"
   (and (match_code "const_int")