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riscv-gcc-1
Commit 26a89301 by Ulrich Weigand Committed by Ulrich Weigand
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s390.c (s390_select_ccmode): Return CCAPmode for integer NEG and ABS. 

	* config/s390/s390.c (s390_select_ccmode): Return CCAPmode for
	integer NEG and ABS.
	* config/s390/s390.md ("*negdi2_64"): Fix op_type attribute.
	("*negdi2_31"): Reimplement using a splitter.
	("*negdi2_cc", "*negdi2_cconly"): New insns.
	("*negdi2_sign", "*negdi2_sign_cc"): Likewise.
	("*negsi2_cc", "*negsi2_cconly"): Likewise.
	("*negdf2_cc", "*negdf2_cconly"): Likewise.
	("*negsf2_cc", "*negsf2_cconly"): Likewise.
	("*absdi2_cc", "*absdi2_cconly"): New insns.
	("*absdi2_sign", "*absdi2_sign_cc"): Likewise.
	("*abssi2_cc", "*abssi2_cconly"): Likewise.
	("*absdf2_cc", "*absdf2_cconly"): Likewise.
	("*abssf2_cc", "*abssf2_cconly"): Likewise.
	("*negabsdi2_cc", "*negabsdi2_cconly"): New insns.
	("*negabsdi2_sign", "*negabsdi2_sign_cc"): Likewise.
	("*negabssi2_cc", "*negabssi2_cconly"): Likewise.
	("*negabsdf2_cc", "*negabsdf2_cconly"): Likewise.
	("*negabssf2_cc", "*negabssf2_cconly"): Likewise.

From-SVN: r90347
parent 02887425
Showing with 367 additions and 27 deletions
gcc/ChangeLog
2004-11-09 Ulrich Weigand <uweigand@de.ibm.com> 2004-11-09 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.c (s390_select_ccmode): Return CCAPmode for
integer NEG and ABS.
* config/s390/s390.md ("*negdi2_64"): Fix op_type attribute.
("*negdi2_31"): Reimplement using a splitter.
("*negdi2_cc", "*negdi2_cconly"): New insns.
("*negdi2_sign", "*negdi2_sign_cc"): Likewise.
("*negsi2_cc", "*negsi2_cconly"): Likewise.
("*negdf2_cc", "*negdf2_cconly"): Likewise.
("*negsf2_cc", "*negsf2_cconly"): Likewise.
("*absdi2_cc", "*absdi2_cconly"): New insns.
("*absdi2_sign", "*absdi2_sign_cc"): Likewise.
("*abssi2_cc", "*abssi2_cconly"): Likewise.
("*absdf2_cc", "*absdf2_cconly"): Likewise.
("*abssf2_cc", "*abssf2_cconly"): Likewise.
("*negabsdi2_cc", "*negabsdi2_cconly"): New insns.
("*negabsdi2_sign", "*negabsdi2_sign_cc"): Likewise.
("*negabssi2_cc", "*negabssi2_cconly"): Likewise.
("*negabsdf2_cc", "*negabsdf2_cconly"): Likewise.
("*negabssf2_cc", "*negabssf2_cconly"): Likewise.
2004-11-09 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.c (s390_canonicalize_comparison): Reverse condition * config/s390/s390.c (s390_canonicalize_comparison): Reverse condition
when eliminating an UNSPEC_CMPINT. when eliminating an UNSPEC_CMPINT.
(s390_secondary_input_reload_class): Fix test for CC register reload. (s390_secondary_input_reload_class): Fix test for CC register reload.
......
gcc/config/s390/s390.c
...@@ -446,6 +446,9 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) ...@@ -446,6 +446,9 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
{ {
case EQ: case EQ:
case NE: case NE:
if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
&& GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
return CCAPmode;
if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
&& CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'K', "K")) && CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'K', "K"))
return CCAPmode; return CCAPmode;
...@@ -482,6 +485,9 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) ...@@ -482,6 +485,9 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
case LT: case LT:
case GE: case GE:
case GT: case GT:
if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
&& GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
return CCAPmode;
if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
&& CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'K', "K")) && CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'K', "K"))
{ {
...@@ -490,6 +496,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) ...@@ -490,6 +496,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
else else
return CCAPmode; return CCAPmode;
} }
/* Fall through. */
case UNORDERED: case UNORDERED:
case ORDERED: case ORDERED:
case UNEQ: case UNEQ:
......
gcc/config/s390/s390.md
...@@ -6102,36 +6102,104 @@ ...@@ -6102,36 +6102,104 @@
"" ""
"") "")
(define_insn "*negdi2_sign_cc"
[(set (reg 33)
(compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
(match_operand:SI 1 "register_operand" "d") 0)
(const_int 32)) (const_int 32)))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*negdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*negdi2_cc"
[(set (reg 33)
(compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_dup 1)))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lcgr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*negdi2_cconly"
[(set (reg 33)
(compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lcgr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*negdi2_64" (define_insn "*negdi2_64"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d"))) (neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_64BIT" "TARGET_64BIT"
"lcgr\t%0,%1" "lcgr\t%0,%1"
[(set_attr "op_type" "RR")]) [(set_attr "op_type" "RRE")])
(define_insn "*negdi2_31" (define_insn_and_split "*negdi2_31"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d"))) (neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"!TARGET_64BIT" "!TARGET_64BIT"
{ "#"
rtx xop[1]; "&& reload_completed"
xop[0] = gen_label_rtx (); [(parallel
output_asm_insn ("lcr\t%0,%1", operands); [(set (match_dup 2) (neg:SI (match_dup 3)))
output_asm_insn ("lcr\t%N0,%N1", operands); (clobber (reg:CC 33))])
output_asm_insn ("je\t%l0", xop); (parallel
output_asm_insn ("bctr\t%0,0", operands); [(set (reg:CCAP 33)
targetm.asm_out.internal_label (asm_out_file, "L", (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
CODE_LABEL_NUMBER (xop[0])); (set (match_dup 4) (neg:SI (match_dup 5)))])
return ""; (set (pc)
} (if_then_else (ne (reg:CCAP 33) (const_int 0))
[(set_attr "length" "10")]) (pc)
(label_ref (match_dup 6))))
(parallel
[(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
(clobber (reg:CC 33))])
(match_dup 6)]
"operands[2] = operand_subword (operands[0], 0, 0, DImode);
operands[3] = operand_subword (operands[1], 0, 0, DImode);
operands[4] = operand_subword (operands[0], 1, 0, DImode);
operands[5] = operand_subword (operands[1], 1, 0, DImode);
operands[6] = gen_label_rtx ();")
; ;
; negsi2 instruction pattern(s). ; negsi2 instruction pattern(s).
; ;
(define_insn "*negsi2_cc"
[(set (reg 33)
(compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d")
(neg:SI (match_dup 1)))]
"s390_match_ccmode (insn, CCAmode)"
"lcr\t%0,%1"
[(set_attr "op_type" "RR")])
(define_insn "*negsi2_cconly"
[(set (reg 33)
(compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=d"))]
"s390_match_ccmode (insn, CCAmode)"
"lcr\t%0,%1"
[(set_attr "op_type" "RR")])
(define_insn "negsi2" (define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(neg:SI (match_operand:SI 1 "register_operand" "d"))) (neg:SI (match_operand:SI 1 "register_operand" "d")))
...@@ -6152,6 +6220,27 @@ ...@@ -6152,6 +6220,27 @@
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "*negdf2_cc"
[(set (reg 33)
(compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
(match_operand:DF 2 "const0_operand" "")))
(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
(define_insn "*negdf2_cconly"
[(set (reg 33)
(compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
(match_operand:DF 2 "const0_operand" "")))
(clobber (match_scratch:DF 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
(define_insn "*negdf2" (define_insn "*negdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (match_operand:DF 1 "register_operand" "f"))) (neg:DF (match_operand:DF 1 "register_operand" "f")))
...@@ -6182,6 +6271,27 @@ ...@@ -6182,6 +6271,27 @@
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "*negsf2_cc"
[(set (reg 33)
(compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
(match_operand:SF 2 "const0_operand" "")))
(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
(define_insn "*negsf2_cconly"
[(set (reg 33)
(compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
(match_operand:SF 2 "const0_operand" "")))
(clobber (match_scratch:SF 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
(define_insn "*negsf2" (define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (match_operand:SF 1 "register_operand" "f"))) (neg:SF (match_operand:SF 1 "register_operand" "f")))
...@@ -6209,6 +6319,45 @@ ...@@ -6209,6 +6319,45 @@
; absdi2 instruction pattern(s). ; absdi2 instruction pattern(s).
; ;
(define_insn "*absdi2_sign_cc"
[(set (reg 33)
(compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
(match_operand:SI 1 "register_operand" "d") 0)
(const_int 32)) (const_int 32)))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*absdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*absdi2_cc"
[(set (reg 33)
(compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (match_dup 1)))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lpgr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*absdi2_cconly"
[(set (reg 33)
(compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lpgr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "absdi2" (define_insn "absdi2"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (match_operand:DI 1 "register_operand" "d"))) (abs:DI (match_operand:DI 1 "register_operand" "d")))
...@@ -6221,6 +6370,25 @@ ...@@ -6221,6 +6370,25 @@
; abssi2 instruction pattern(s). ; abssi2 instruction pattern(s).
; ;
(define_insn "*abssi2_cc"
[(set (reg 33)
(compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d")
(abs:SI (match_dup 1)))]
"s390_match_ccmode (insn, CCAmode)"
"lpr\t%0,%1"
[(set_attr "op_type" "RR")])
(define_insn "*abssi2_cconly"
[(set (reg 33)
(compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=d"))]
"s390_match_ccmode (insn, CCAmode)"
"lpr\t%0,%1"
[(set_attr "op_type" "RR")])
(define_insn "abssi2" (define_insn "abssi2"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(abs:SI (match_operand:SI 1 "register_operand" "d"))) (abs:SI (match_operand:SI 1 "register_operand" "d")))
...@@ -6241,6 +6409,27 @@ ...@@ -6241,6 +6409,27 @@
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "*absdf2_cc"
[(set (reg 33)
(compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
(match_operand:DF 2 "const0_operand" "")))
(set (match_operand:DF 0 "register_operand" "=f")
(abs:DF (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
(define_insn "*absdf2_cconly"
[(set (reg 33)
(compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
(match_operand:DF 2 "const0_operand" "")))
(clobber (match_scratch:DF 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
(define_insn "*absdf2" (define_insn "*absdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(abs:DF (match_operand:DF 1 "register_operand" "f"))) (abs:DF (match_operand:DF 1 "register_operand" "f")))
...@@ -6271,6 +6460,27 @@ ...@@ -6271,6 +6460,27 @@
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "*abssf2_cc"
[(set (reg 33)
(compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
(match_operand:SF 2 "const0_operand" "")))
(set (match_operand:SF 0 "register_operand" "=f")
(abs:SF (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
(define_insn "*abssf2_cconly"
[(set (reg 33)
(compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
(match_operand:SF 2 "const0_operand" "")))
(clobber (match_scratch:SF 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
(define_insn "*abssf2" (define_insn "*abssf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(abs:SF (match_operand:SF 1 "register_operand" "f"))) (abs:SF (match_operand:SF 1 "register_operand" "f")))
...@@ -6297,13 +6507,45 @@ ...@@ -6297,13 +6507,45 @@
; Integer ; Integer
; ;
(define_insn "*negabssi2" (define_insn "*negabsdi2_sign_cc"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (reg 33)
(neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
(match_operand:SI 1 "register_operand" "d") 0)
(const_int 32)) (const_int 32))))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*negabsdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "d")))))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" "TARGET_64BIT"
"lnr\t%0,%1" "lngfr\t%0,%1"
[(set_attr "op_type" "RR")]) [(set_attr "op_type" "RRE")])
(define_insn "*negabsdi2_cc"
[(set (reg 33)
(compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lngr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*negabsdi2_cconly"
[(set (reg 33)
(compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lngr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*negabsdi2" (define_insn "*negabsdi2"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
...@@ -6313,18 +6555,57 @@ ...@@ -6313,18 +6555,57 @@
"lngr\t%0,%1" "lngr\t%0,%1"
[(set_attr "op_type" "RRE")]) [(set_attr "op_type" "RRE")])
(define_insn "*negabssi2_cc"
[(set (reg 33)
(compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d")
(neg:SI (abs:SI (match_dup 1))))]
"s390_match_ccmode (insn, CCAmode)"
"lnr\t%0,%1"
[(set_attr "op_type" "RR")])
(define_insn "*negabssi2_cconly"
[(set (reg 33)
(compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
(const_int 0)))
(clobber (match_scratch:SI 0 "=d"))]
"s390_match_ccmode (insn, CCAmode)"
"lnr\t%0,%1"
[(set_attr "op_type" "RR")])
(define_insn "*negabssi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC 33))]
""
"lnr\t%0,%1"
[(set_attr "op_type" "RR")])
; ;
; Floating point ; Floating point
; ;
(define_insn "*negabssf2" (define_insn "*negabsdf2_cc"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (reg 33)
(neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
(clobber (reg:CC 33))] (match_operand:DF 2 "const0_operand" "")))
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" (set (match_operand:DF 0 "register_operand" "=f")
"lnebr\t%0,%1" (neg:DF (abs:DF (match_dup 1))))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpd")])
(define_insn "*negabsdf2_cconly"
[(set (reg 33)
(compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
(match_operand:DF 2 "const0_operand" "")))
(clobber (match_scratch:DF 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
(define_insn "*negabsdf2" (define_insn "*negabsdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
...@@ -6335,6 +6616,36 @@ ...@@ -6335,6 +6616,36 @@
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpd")])
(define_insn "*negabssf2_cc"
[(set (reg 33)
(compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
(match_operand:SF 2 "const0_operand" "")))
(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (abs:SF (match_dup 1))))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
(define_insn "*negabssf2_cconly"
[(set (reg 33)
(compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
(match_operand:SF 2 "const0_operand" "")))
(clobber (match_scratch:SF 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
(define_insn "*negabssf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
;; ;;
;;- Square root instructions. ;;- Square root instructions.
;; ;;
......
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