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riscv-gcc-1
Commit 24697ca0 by David S. Miller Committed by David S. Miller
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Simplify length insn attribute and make more judicious use of insn attribute defaulting. 

2001-09-04  David S. Miller  <davem@redhat.com>

	Simplify length insn attribute and make more judicious use
	of insn attribute defaulting.
	* config/sparc/sparc.md (all insns with length > one): Mark as
	insn type multi if real instructions, else use default if
	it is a forced splitter.
	(all insns with length == one): Use default insn length.
	(all insns of type ialu): Use default insn type.

	Fix erroneous insn attribute settings.
	(addx): Set insn type to misc.
	(mulsidi3_sp64, const_mulsidi3_sp64, umulsidi3_sp64,
	const_umulsidi3_sp64): Set insn type to imul.

	Track SFmode vs DFmode insns according to UltraSPARC
	scheduling rules.
	* config/sparc/sparc.md ("fptype"): New attribute, default
	to "single".
	(all DFmode single insns): Mark as fptype "double".

From-SVN: r45377
parent da86f08f
Showing with 418 additions and 563 deletions
gcc/ChangeLog
...@@ -24,6 +24,25 @@ ...@@ -24,6 +24,25 @@
references. Replace TYPE_{UNARY,BINARY,MOVE} references with references. Replace TYPE_{UNARY,BINARY,MOVE} references with
TYPE_IALU. TYPE_IALU.
Simplify length insn attribute and make more judicious use
of insn attribute defaulting.
* config/sparc/sparc.md (all insns with length > one): Mark as
insn type multi if real instructions, else use default if
it is a forced splitter.
(all insns with length == one): Use default insn length.
(all insns of type ialu): Use default insn type.
Fix erroneous insn attribute settings.
(addx): Set insn type to misc.
(mulsidi3_sp64, const_mulsidi3_sp64, umulsidi3_sp64,
const_umulsidi3_sp64): Set insn type to imul.
Track SFmode vs DFmode insns according to UltraSPARC
scheduling rules.
* config/sparc/sparc.md ("fptype"): New attribute, default
to "single".
(all DFmode single insns): Mark as fptype "double".
2001-09-03 Jakub Jelinek <jakub@redhat.com> 2001-09-03 Jakub Jelinek <jakub@redhat.com>
* loop.c (express_from_1): Fix CONSTANT_P(a) case. * loop.c (express_from_1): Fix CONSTANT_P(a) case.
......
gcc/config/sparc/sparc.md
...@@ -83,35 +83,17 @@ ...@@ -83,35 +83,17 @@
;; Insn type. ;; Insn type.
(define_attr "type" (define_attr "type"
"ialu,compare,shift,load,sload,store,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc" "ialu,compare,shift,load,sload,store,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,imul,idiv,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc"
(const_string "ialu")) (const_string "ialu"))
;; Length (in # of insns). ;; Length (in # of insns).
(define_attr "length" "" (define_attr "length" "" (const_int 1))
(cond [(eq_attr "type" "load,sload,fpload")
(if_then_else (match_operand 1 "symbolic_memory_operand" "")
(const_int 2) (const_int 1))
(eq_attr "type" "store,fpstore") ;; FP precision.
(if_then_else (match_operand 0 "symbolic_memory_operand" "") (define_attr "fptype" "single,double" (const_string "single"))
(const_int 2) (const_int 1))
(eq_attr "type" "ialu")
(if_then_else (ior (match_operand 2 "arith_operand" "")
(match_operand 2 "arith_double_operand" ""))
(const_int 1) (const_int 3))
(eq_attr "type" "multi") (const_int 2)
(eq_attr "type" "ialu")
(if_then_else (ior (match_operand 1 "arith_operand" "")
(match_operand 1 "arith_double_operand" ""))
(const_int 1) (const_int 2))]
(const_int 1)))
(define_asm_attributes (define_asm_attributes
[(set_attr "length" "1") [(set_attr "length" "2")
(set_attr "type" "multi")]) (set_attr "type" "multi")])
;; Attributes for instruction and branch scheduling ;; Attributes for instruction and branch scheduling
...@@ -654,7 +636,8 @@ ...@@ -654,7 +636,8 @@
return \"fcmped\\t%0, %1, %2\"; return \"fcmped\\t%0, %1, %2\";
return \"fcmped\\t%1, %2\"; return \"fcmped\\t%1, %2\";
}" }"
[(set_attr "type" "fpcmp")]) [(set_attr "type" "fpcmp")
(set_attr "fptype" "double")])
(define_insn "*cmptf_fpe" (define_insn "*cmptf_fpe"
[(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c") [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
...@@ -693,7 +676,8 @@ ...@@ -693,7 +676,8 @@
return \"fcmpd\\t%0, %1, %2\"; return \"fcmpd\\t%0, %1, %2\";
return \"fcmpd\\t%1, %2\"; return \"fcmpd\\t%1, %2\";
}" }"
[(set_attr "type" "fpcmp")]) [(set_attr "type" "fpcmp")
(set_attr "fptype" "double")])
(define_insn "*cmptf_fp" (define_insn "*cmptf_fp"
[(set (match_operand:CCFP 0 "fcc_reg_operand" "=c") [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
...@@ -1158,8 +1142,7 @@ ...@@ -1158,8 +1142,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"#" "#"
[(set_attr "type" "cmove") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -1180,8 +1163,7 @@ ...@@ -1180,8 +1163,7 @@
(const_int 0))))] (const_int 0))))]
"TARGET_ARCH64" "TARGET_ARCH64"
"#" "#"
[(set_attr "type" "cmove") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -1202,8 +1184,7 @@ ...@@ -1202,8 +1184,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"#" "#"
[(set_attr "type" "cmove") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -1287,8 +1268,7 @@ ...@@ -1287,8 +1268,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"#" "#"
[(set_attr "type" "cmove") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -1309,8 +1289,7 @@ ...@@ -1309,8 +1289,7 @@
(const_int 0))))] (const_int 0))))]
"TARGET_ARCH64" "TARGET_ARCH64"
"#" "#"
[(set_attr "type" "cmove") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -1331,8 +1310,7 @@ ...@@ -1331,8 +1310,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"#" "#"
[(set_attr "type" "cmove") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -1452,16 +1430,14 @@ ...@@ -1452,16 +1430,14 @@
(ltu:SI (reg:CC 100) (const_int 0)))] (ltu:SI (reg:CC 100) (const_int 0)))]
"" ""
"addx\\t%%g0, 0, %0" "addx\\t%%g0, 0, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*neg_sltu_insn" (define_insn "*neg_sltu_insn"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
"" ""
"subx\\t%%g0, 0, %0" "subx\\t%%g0, 0, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
;; ??? Combine should canonicalize these next two to the same pattern. ;; ??? Combine should canonicalize these next two to the same pattern.
(define_insn "*neg_sltu_minus_x" (define_insn "*neg_sltu_minus_x"
...@@ -1470,8 +1446,7 @@ ...@@ -1470,8 +1446,7 @@
(match_operand:SI 1 "arith_operand" "rI")))] (match_operand:SI 1 "arith_operand" "rI")))]
"" ""
"subx\\t%%g0, %1, %0" "subx\\t%%g0, %1, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*neg_sltu_plus_x" (define_insn "*neg_sltu_plus_x"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -1479,24 +1454,21 @@ ...@@ -1479,24 +1454,21 @@
(match_operand:SI 1 "arith_operand" "rI"))))] (match_operand:SI 1 "arith_operand" "rI"))))]
"" ""
"subx\\t%%g0, %1, %0" "subx\\t%%g0, %1, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*sgeu_insn" (define_insn "*sgeu_insn"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(geu:SI (reg:CC 100) (const_int 0)))] (geu:SI (reg:CC 100) (const_int 0)))]
"" ""
"subx\\t%%g0, -1, %0" "subx\\t%%g0, -1, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*neg_sgeu_insn" (define_insn "*neg_sgeu_insn"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (geu:SI (reg:CC 100) (const_int 0))))] (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
"" ""
"addx\\t%%g0, -1, %0" "addx\\t%%g0, -1, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in. ;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in.
;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
...@@ -1508,8 +1480,7 @@ ...@@ -1508,8 +1480,7 @@
(match_operand:SI 1 "arith_operand" "rI")))] (match_operand:SI 1 "arith_operand" "rI")))]
"" ""
"addx\\t%%g0, %1, %0" "addx\\t%%g0, %1, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*sltu_plus_x_plus_y" (define_insn "*sltu_plus_x_plus_y"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -1518,8 +1489,7 @@ ...@@ -1518,8 +1489,7 @@
(match_operand:SI 2 "arith_operand" "rI"))))] (match_operand:SI 2 "arith_operand" "rI"))))]
"" ""
"addx\\t%1, %2, %0" "addx\\t%1, %2, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*x_minus_sltu" (define_insn "*x_minus_sltu"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -1527,8 +1497,7 @@ ...@@ -1527,8 +1497,7 @@
(ltu:SI (reg:CC 100) (const_int 0))))] (ltu:SI (reg:CC 100) (const_int 0))))]
"" ""
"subx\\t%1, 0, %0" "subx\\t%1, 0, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
;; ??? Combine should canonicalize these next two to the same pattern. ;; ??? Combine should canonicalize these next two to the same pattern.
(define_insn "*x_minus_y_minus_sltu" (define_insn "*x_minus_y_minus_sltu"
...@@ -1538,8 +1507,7 @@ ...@@ -1538,8 +1507,7 @@
(ltu:SI (reg:CC 100) (const_int 0))))] (ltu:SI (reg:CC 100) (const_int 0))))]
"" ""
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*x_minus_sltu_plus_y" (define_insn "*x_minus_sltu_plus_y"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -1548,8 +1516,7 @@ ...@@ -1548,8 +1516,7 @@
(match_operand:SI 2 "arith_operand" "rI"))))] (match_operand:SI 2 "arith_operand" "rI"))))]
"" ""
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*sgeu_plus_x" (define_insn "*sgeu_plus_x"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -1557,8 +1524,7 @@ ...@@ -1557,8 +1524,7 @@
(match_operand:SI 1 "register_operand" "r")))] (match_operand:SI 1 "register_operand" "r")))]
"" ""
"subx\\t%1, -1, %0" "subx\\t%1, -1, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*x_minus_sgeu" (define_insn "*x_minus_sgeu"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -1566,8 +1532,7 @@ ...@@ -1566,8 +1532,7 @@
(geu:SI (reg:CC 100) (const_int 0))))] (geu:SI (reg:CC 100) (const_int 0))))]
"" ""
"addx\\t%1, -1, %0" "addx\\t%1, -1, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -2064,7 +2029,8 @@ ...@@ -2064,7 +2029,8 @@
(unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))] (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))]
"flag_pic && REGNO (operands[0]) == 23" "flag_pic && REGNO (operands[0]) == 23"
"sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0" "sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0"
[(set_attr "length" "3")]) [(set_attr "type" "multi")
(set_attr "length" "3")])
;; Currently unused... ;; Currently unused...
;; (define_insn "get_pc_via_rdpc" ;; (define_insn "get_pc_via_rdpc"
...@@ -2142,8 +2108,7 @@ ...@@ -2142,8 +2108,7 @@
mov\\t%1, %0 mov\\t%1, %0
ldub\\t%1, %0 ldub\\t%1, %0
stb\\t%r1, %0" stb\\t%r1, %0"
[(set_attr "type" "*,load,store") [(set_attr "type" "*,load,store")])
(set_attr "length" "1")])
(define_expand "movhi" (define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "") [(set (match_operand:HI 0 "general_operand" "")
...@@ -2205,8 +2170,7 @@ ...@@ -2205,8 +2170,7 @@
[(set (match_operand:HI 0 "register_operand" "=r") [(set (match_operand:HI 0 "register_operand" "=r")
(match_operand:HI 1 "const64_high_operand" ""))] (match_operand:HI 1 "const64_high_operand" ""))]
"TARGET_ARCH64" "TARGET_ARCH64"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "*movhi_insn" (define_insn "*movhi_insn"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
...@@ -2218,8 +2182,7 @@ ...@@ -2218,8 +2182,7 @@
sethi\\t%%hi(%a1), %0 sethi\\t%%hi(%a1), %0
lduh\\t%1, %0 lduh\\t%1, %0
sth\\t%r1, %0" sth\\t%r1, %0"
[(set_attr "type" "*,*,load,store") [(set_attr "type" "*,*,load,store")])
(set_attr "length" "1")])
;; We always work with constants here. ;; We always work with constants here.
(define_insn "*movhi_lo_sum" (define_insn "*movhi_lo_sum"
...@@ -2227,9 +2190,7 @@ ...@@ -2227,9 +2190,7 @@
(ior:HI (match_operand:HI 1 "arith_operand" "%r") (ior:HI (match_operand:HI 1 "arith_operand" "%r")
(match_operand:HI 2 "arith_operand" "I")))] (match_operand:HI 2 "arith_operand" "I")))]
"" ""
"or\\t%1, %2, %0" "or\\t%1, %2, %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_expand "movsi" (define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "") [(set (match_operand:SI 0 "general_operand" "")
...@@ -2309,8 +2270,7 @@ ...@@ -2309,8 +2270,7 @@
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "const64_high_operand" ""))] (match_operand:SI 1 "const64_high_operand" ""))]
"TARGET_ARCH64" "TARGET_ARCH64"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "*movsi_insn" (define_insn "*movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d") [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
...@@ -2327,24 +2287,20 @@ ...@@ -2327,24 +2287,20 @@
st\\t%r1, %0 st\\t%r1, %0
st\\t%1, %0 st\\t%1, %0
fzeros\\t%0" fzeros\\t%0"
[(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove") [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")])
(set_attr "length" "1")])
(define_insn "*movsi_lo_sum" (define_insn "*movsi_lo_sum"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "in")))] (match_operand:SI 2 "immediate_operand" "in")))]
"" ""
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "*movsi_high" (define_insn "*movsi_high"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(high:SI (match_operand:SI 1 "immediate_operand" "in")))] (high:SI (match_operand:SI 1 "immediate_operand" "in")))]
"" ""
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
;; so that CSE won't optimize the address computation away. ;; so that CSE won't optimize the address computation away.
...@@ -2353,16 +2309,13 @@ ...@@ -2353,16 +2309,13 @@
(lo_sum:SI (match_operand:SI 1 "register_operand" "r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))] (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
"flag_pic" "flag_pic"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "movsi_high_pic" (define_insn "movsi_high_pic"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(high:SI (unspec:SI [(match_operand 1 "" "")] 0)))] (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
"flag_pic && check_pic (1)" "flag_pic && check_pic (1)"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_expand "movsi_pic_label_ref" (define_expand "movsi_pic_label_ref"
[(set (match_dup 3) (high:SI [(set (match_dup 3) (high:SI
...@@ -2396,8 +2349,7 @@ ...@@ -2396,8 +2349,7 @@
(unspec:SI [(match_operand:SI 1 "label_ref_operand" "") (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
(match_operand:SI 2 "" "")] 5)))] (match_operand:SI 2 "" "")] 5)))]
"flag_pic" "flag_pic"
"sethi\\t%%hi(%a2-(%a1-.)), %0" "sethi\\t%%hi(%a2-(%a1-.)), %0")
[(set_attr "length" "1")])
(define_insn "*movsi_lo_sum_pic_label_ref" (define_insn "*movsi_lo_sum_pic_label_ref"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -2405,9 +2357,7 @@ ...@@ -2405,9 +2357,7 @@
(unspec:SI [(match_operand:SI 2 "label_ref_operand" "") (unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
(match_operand:SI 3 "" "")] 5)))] (match_operand:SI 3 "" "")] 5)))]
"flag_pic" "flag_pic"
"or\\t%1, %%lo(%a3-(%a2-.)), %0" "or\\t%1, %%lo(%a3-(%a2-.)), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_expand "movdi" (define_expand "movdi"
[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "") [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
...@@ -2524,7 +2474,7 @@ ...@@ -2524,7 +2474,7 @@
# #
#" #"
[(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*") [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
(set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")]) (set_attr "length" "*,*,2,2,2,2,*,*,2,2,2")])
;; The following are generated by sparc_emit_set_const64 ;; The following are generated by sparc_emit_set_const64
(define_insn "*movdi_sp64_dbl" (define_insn "*movdi_sp64_dbl"
...@@ -2532,8 +2482,7 @@ ...@@ -2532,8 +2482,7 @@
(match_operand:DI 1 "const64_operand" ""))] (match_operand:DI 1 "const64_operand" ""))]
"(TARGET_ARCH64 "(TARGET_ARCH64
&& HOST_BITS_PER_WIDE_INT != 64)" && HOST_BITS_PER_WIDE_INT != 64)"
"mov\\t%1, %0" "mov\\t%1, %0")
[(set_attr "length" "1")])
;; This is needed to show CSE exactly which bits are set ;; This is needed to show CSE exactly which bits are set
;; in a 64-bit register by sethi instructions. ;; in a 64-bit register by sethi instructions.
...@@ -2541,8 +2490,7 @@ ...@@ -2541,8 +2490,7 @@
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const64_high_operand" ""))] (match_operand:DI 1 "const64_high_operand" ""))]
"TARGET_ARCH64" "TARGET_ARCH64"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "*movdi_insn_sp64_novis" (define_insn "*movdi_insn_sp64_novis"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m") [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m")
...@@ -2560,7 +2508,7 @@ ...@@ -2560,7 +2508,7 @@
ldd\\t%1, %0 ldd\\t%1, %0
std\\t%1, %0" std\\t%1, %0"
[(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore") [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore")
(set_attr "length" "1")]) (set_attr "fptype" "*,*,*,*,*,double,*,*")])
(define_insn "*movdi_insn_sp64_vis" (define_insn "*movdi_insn_sp64_vis"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m,b") [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m,b")
...@@ -2579,7 +2527,7 @@ ...@@ -2579,7 +2527,7 @@
std\\t%1, %0 std\\t%1, %0
fzero\\t%0" fzero\\t%0"
[(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove") [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove")
(set_attr "length" "1")]) (set_attr "fptype" "*,*,*,*,*,double,*,*,double")])
(define_expand "movdi_pic_label_ref" (define_expand "movdi_pic_label_ref"
[(set (match_dup 3) (high:DI [(set (match_dup 3) (high:DI
...@@ -2613,8 +2561,7 @@ ...@@ -2613,8 +2561,7 @@
(unspec:DI [(match_operand:DI 1 "label_ref_operand" "") (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
(match_operand:DI 2 "" "")] 5)))] (match_operand:DI 2 "" "")] 5)))]
"TARGET_ARCH64 && flag_pic" "TARGET_ARCH64 && flag_pic"
"sethi\\t%%hi(%a2-(%a1-.)), %0" "sethi\\t%%hi(%a2-(%a1-.)), %0")
[(set_attr "length" "1")])
(define_insn "*movdi_lo_sum_pic_label_ref" (define_insn "*movdi_lo_sum_pic_label_ref"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2622,9 +2569,7 @@ ...@@ -2622,9 +2569,7 @@
(unspec:DI [(match_operand:DI 2 "label_ref_operand" "") (unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
(match_operand:DI 3 "" "")] 5)))] (match_operand:DI 3 "" "")] 5)))]
"TARGET_ARCH64 && flag_pic" "TARGET_ARCH64 && flag_pic"
"or\\t%1, %%lo(%a3-(%a2-.)), %0" "or\\t%1, %%lo(%a3-(%a2-.)), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
;; Sparc-v9 code model support insns. See sparc_emit_set_symbolic_const64 ;; Sparc-v9 code model support insns. See sparc_emit_set_symbolic_const64
;; in sparc.c to see what is going on here... PIC stuff comes first. ;; in sparc.c to see what is going on here... PIC stuff comes first.
...@@ -2634,150 +2579,123 @@ ...@@ -2634,150 +2579,123 @@
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))] (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))]
"TARGET_ARCH64 && flag_pic" "TARGET_ARCH64 && flag_pic"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "movdi_high_pic" (define_insn "movdi_high_pic"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand 1 "" "")] 0)))] (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))]
"TARGET_ARCH64 && flag_pic && check_pic (1)" "TARGET_ARCH64 && flag_pic && check_pic (1)"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "*sethi_di_medlow_embmedany_pic" (define_insn "*sethi_di_medlow_embmedany_pic"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))] (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
"(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)" "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "*sethi_di_medlow" (define_insn "*sethi_di_medlow"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand:DI 1 "symbolic_operand" "")))] (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
"TARGET_CM_MEDLOW && check_pic (1)" "TARGET_CM_MEDLOW && check_pic (1)"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "*losum_di_medlow" (define_insn "*losum_di_medlow"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "")))] (match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDLOW" "TARGET_CM_MEDLOW"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "seth44" (define_insn "seth44"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))] (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))]
"TARGET_CM_MEDMID" "TARGET_CM_MEDMID"
"sethi\\t%%h44(%a1), %0" "sethi\\t%%h44(%a1), %0")
[(set_attr "length" "1")])
(define_insn "setm44" (define_insn "setm44"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))] (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))]
"TARGET_CM_MEDMID" "TARGET_CM_MEDMID"
"or\\t%1, %%m44(%a2), %0" "or\\t%1, %%m44(%a2), %0")
[(set_attr "length" "1")])
(define_insn "setl44" (define_insn "setl44"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "")))] (match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDMID" "TARGET_CM_MEDMID"
"or\\t%1, %%l44(%a2), %0" "or\\t%1, %%l44(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "sethh" (define_insn "sethh"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))] (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))]
"TARGET_CM_MEDANY" "TARGET_CM_MEDANY"
"sethi\\t%%hh(%a1), %0" "sethi\\t%%hh(%a1), %0")
[(set_attr "length" "1")])
(define_insn "setlm" (define_insn "setlm"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))] (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))]
"TARGET_CM_MEDANY" "TARGET_CM_MEDANY"
"sethi\\t%%lm(%a1), %0" "sethi\\t%%lm(%a1), %0")
[(set_attr "length" "1")])
(define_insn "sethm" (define_insn "sethm"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))] (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))]
"TARGET_CM_MEDANY" "TARGET_CM_MEDANY"
"or\\t%1, %%hm(%a2), %0" "or\\t%1, %%hm(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "setlo" (define_insn "setlo"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "")))] (match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDANY" "TARGET_CM_MEDANY"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "embmedany_sethi" (define_insn "embmedany_sethi"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))] (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))]
"TARGET_CM_EMBMEDANY && check_pic (1)" "TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "embmedany_losum" (define_insn "embmedany_losum"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "data_segment_operand" "")))] (match_operand:DI 2 "data_segment_operand" "")))]
"TARGET_CM_EMBMEDANY" "TARGET_CM_EMBMEDANY"
"add\\t%1, %%lo(%a2), %0" "add\\t%1, %%lo(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "embmedany_brsum" (define_insn "embmedany_brsum"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))] (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))]
"TARGET_CM_EMBMEDANY" "TARGET_CM_EMBMEDANY"
"add\\t%1, %_, %0" "add\\t%1, %_, %0")
[(set_attr "length" "1")])
(define_insn "embmedany_textuhi" (define_insn "embmedany_textuhi"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))] (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))]
"TARGET_CM_EMBMEDANY && check_pic (1)" "TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\\t%%uhi(%a1), %0" "sethi\\t%%uhi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "embmedany_texthi" (define_insn "embmedany_texthi"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))] (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))]
"TARGET_CM_EMBMEDANY && check_pic (1)" "TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\\t%%hi(%a1), %0" "sethi\\t%%hi(%a1), %0")
[(set_attr "length" "1")])
(define_insn "embmedany_textulo" (define_insn "embmedany_textulo"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))] (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))]
"TARGET_CM_EMBMEDANY" "TARGET_CM_EMBMEDANY"
"or\\t%1, %%ulo(%a2), %0" "or\\t%1, %%ulo(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "embmedany_textlo" (define_insn "embmedany_textlo"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "text_segment_operand" "")))] (match_operand:DI 2 "text_segment_operand" "")))]
"TARGET_CM_EMBMEDANY" "TARGET_CM_EMBMEDANY"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
;; Now some patterns to help reload out a bit. ;; Now some patterns to help reload out a bit.
(define_expand "reload_indi" (define_expand "reload_indi"
...@@ -2997,8 +2915,7 @@ ...@@ -2997,8 +2915,7 @@
abort(); abort();
} }
}" }"
[(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store") [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])
(set_attr "length" "1")])
(define_insn "*movsf_insn_vis" (define_insn "*movsf_insn_vis"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m") [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
...@@ -3046,8 +2963,7 @@ ...@@ -3046,8 +2963,7 @@
abort(); abort();
} }
}" }"
[(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store") [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")])
(set_attr "length" "1")])
;; Exactly the same as above, except that all `f' cases are deleted. ;; Exactly the same as above, except that all `f' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `f' reg ;; This is necessary to prevent reload from ever trying to use a `f' reg
...@@ -3093,8 +3009,7 @@ ...@@ -3093,8 +3009,7 @@
abort(); abort();
} }
}" }"
[(set_attr "type" "*,*,*,*,load,store") [(set_attr "type" "*,*,*,*,load,store")])
(set_attr "length" "1")])
(define_insn "*movsf_lo_sum" (define_insn "*movsf_lo_sum"
[(set (match_operand:SF 0 "register_operand" "=r") [(set (match_operand:SF 0 "register_operand" "=r")
...@@ -3110,9 +3025,7 @@ ...@@ -3110,9 +3025,7 @@
REAL_VALUE_TO_TARGET_SINGLE (r, i); REAL_VALUE_TO_TARGET_SINGLE (r, i);
operands[2] = GEN_INT (i); operands[2] = GEN_INT (i);
return \"or\\t%1, %%lo(%a2), %0\"; return \"or\\t%1, %%lo(%a2), %0\";
}" }")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "*movsf_high" (define_insn "*movsf_high"
[(set (match_operand:SF 0 "register_operand" "=r") [(set (match_operand:SF 0 "register_operand" "=r")
...@@ -3127,8 +3040,7 @@ ...@@ -3127,8 +3040,7 @@
REAL_VALUE_TO_TARGET_SINGLE (r, i); REAL_VALUE_TO_TARGET_SINGLE (r, i);
operands[1] = GEN_INT (i); operands[1] = GEN_INT (i);
return \"sethi\\t%%hi(%1), %0\"; return \"sethi\\t%%hi(%1), %0\";
}" }")
[(set_attr "length" "1")])
(define_split (define_split
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
...@@ -3282,7 +3194,7 @@ ...@@ -3282,7 +3194,7 @@
# #
#" #"
[(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*") [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
(set_attr "length" "1,1,1,1,2,2,2,2,2,2")]) (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
(define_insn "*movdf_no_e_insn_sp32" (define_insn "*movdf_no_e_insn_sp32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o") [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
...@@ -3300,7 +3212,7 @@ ...@@ -3300,7 +3212,7 @@
# #
#" #"
[(set_attr "type" "load,store,*,*,*") [(set_attr "type" "load,store,*,*,*")
(set_attr "length" "1,1,2,2,2")]) (set_attr "length" "*,*,2,2,2")])
(define_insn "*movdf_no_e_insn_v9_sp32" (define_insn "*movdf_no_e_insn_v9_sp32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o") [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
...@@ -3318,7 +3230,7 @@ ...@@ -3318,7 +3230,7 @@
# #
#" #"
[(set_attr "type" "load,store,store,*,*") [(set_attr "type" "load,store,store,*,*")
(set_attr "length" "1,1,1,2,2")]) (set_attr "length" "*,*,*,2,2")])
;; We have available v9 double floats but not 64-bit ;; We have available v9 double floats but not 64-bit
;; integer registers and no VIS. ;; integer registers and no VIS.
...@@ -3343,7 +3255,8 @@ ...@@ -3343,7 +3255,8 @@
# #
#" #"
[(set_attr "type" "fpmove,load,store,store,load,store,*,*,*") [(set_attr "type" "fpmove,load,store,store,load,store,*,*,*")
(set_attr "length" "1,1,1,1,1,1,2,2,2")]) (set_attr "length" "*,*,*,*,*,*,2,2,2")
(set_attr "fptype" "double,*,*,*,*,*,*,*,*")])
;; We have available v9 double floats but not 64-bit ;; We have available v9 double floats but not 64-bit
;; integer registers but we have VIS. ;; integer registers but we have VIS.
...@@ -3368,7 +3281,8 @@ ...@@ -3368,7 +3281,8 @@
# #
#" #"
[(set_attr "type" "fpmove,fpmove,load,store,store,load,store,*,*,*") [(set_attr "type" "fpmove,fpmove,load,store,store,load,store,*,*,*")
(set_attr "length" "1,1,1,1,1,1,1,2,2,2")]) (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
(set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
;; We have available both v9 double floats and 64-bit ;; We have available both v9 double floats and 64-bit
;; integer registers. No VIS though. ;; integer registers. No VIS though.
...@@ -3390,7 +3304,8 @@ ...@@ -3390,7 +3304,8 @@
stx\\t%r1, %0 stx\\t%r1, %0
#" #"
[(set_attr "type" "fpmove,load,store,*,load,store,*") [(set_attr "type" "fpmove,load,store,*,load,store,*")
(set_attr "length" "1,1,1,1,1,1,2")]) (set_attr "length" "*,*,*,*,*,*,2")
(set_attr "fptype" "double,*,*,*,*,*,*")])
;; We have available both v9 double floats and 64-bit ;; We have available both v9 double floats and 64-bit
;; integer registers. And we have VIS. ;; integer registers. And we have VIS.
...@@ -3413,7 +3328,8 @@ ...@@ -3413,7 +3328,8 @@
stx\\t%r1, %0 stx\\t%r1, %0
#" #"
[(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*") [(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*")
(set_attr "length" "1,1,1,1,1,1,1,2")]) (set_attr "length" "*,*,*,*,*,*,*,2")
(set_attr "fptype" "double,double,*,*,*,*,*,*")])
(define_insn "*movdf_no_e_insn_sp64" (define_insn "*movdf_no_e_insn_sp64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m") [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
...@@ -3427,8 +3343,7 @@ ...@@ -3427,8 +3343,7 @@
mov\\t%1, %0 mov\\t%1, %0
ldx\\t%1, %0 ldx\\t%1, %0
stx\\t%r1, %0" stx\\t%r1, %0"
[(set_attr "type" "*,load,store") [(set_attr "type" "*,load,store")])
(set_attr "length" "1")])
(define_split (define_split
[(set (match_operand:DF 0 "register_operand" "") [(set (match_operand:DF 0 "register_operand" "")
...@@ -3758,7 +3673,7 @@ ...@@ -3758,7 +3673,7 @@
# #
#" #"
[(set_attr "type" "fpmove,fpload,fpstore,*,*") [(set_attr "type" "fpmove,fpload,fpstore,*,*")
(set_attr "length" "1,1,1,2,2")]) (set_attr "length" "*,*,*,2,2")])
(define_insn "*movtf_insn_hq_vis_sp64" (define_insn "*movtf_insn_hq_vis_sp64"
[(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o") [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
...@@ -3778,7 +3693,7 @@ ...@@ -3778,7 +3693,7 @@
# #
#" #"
[(set_attr "type" "fpmove,fpload,fpstore,*,*,*") [(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
(set_attr "length" "1,1,1,2,2,2")]) (set_attr "length" "*,*,*,2,2,2")])
;; Now we allow the integer register cases even when ;; Now we allow the integer register cases even when
;; only arch64 is true. ;; only arch64 is true.
...@@ -4171,8 +4086,7 @@ ...@@ -4171,8 +4086,7 @@
"@ "@
mov%C1\\t%x2, %3, %0 mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0" mov%c1\\t%x2, %4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
(define_insn "*movhi_cc_sp64" (define_insn "*movhi_cc_sp64"
[(set (match_operand:HI 0 "register_operand" "=r,r") [(set (match_operand:HI 0 "register_operand" "=r,r")
...@@ -4185,8 +4099,7 @@ ...@@ -4185,8 +4099,7 @@
"@ "@
mov%C1\\t%x2, %3, %0 mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0" mov%c1\\t%x2, %4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
(define_insn "*movsi_cc_sp64" (define_insn "*movsi_cc_sp64"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
...@@ -4199,8 +4112,7 @@ ...@@ -4199,8 +4112,7 @@
"@ "@
mov%C1\\t%x2, %3, %0 mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0" mov%c1\\t%x2, %4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
;; ??? The constraints of operands 3,4 need work. ;; ??? The constraints of operands 3,4 need work.
(define_insn "*movdi_cc_sp64" (define_insn "*movdi_cc_sp64"
...@@ -4214,8 +4126,7 @@ ...@@ -4214,8 +4126,7 @@
"@ "@
mov%C1\\t%x2, %3, %0 mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0" mov%c1\\t%x2, %4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
(define_insn "*movdi_cc_sp64_trunc" (define_insn "*movdi_cc_sp64_trunc"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
...@@ -4228,8 +4139,7 @@ ...@@ -4228,8 +4139,7 @@
"@ "@
mov%C1\\t%x2, %3, %0 mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0" mov%c1\\t%x2, %4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
(define_insn "*movsf_cc_sp64" (define_insn "*movsf_cc_sp64"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
...@@ -4242,8 +4152,7 @@ ...@@ -4242,8 +4152,7 @@
"@ "@
fmovs%C1\\t%x2, %3, %0 fmovs%C1\\t%x2, %3, %0
fmovs%c1\\t%x2, %4, %0" fmovs%c1\\t%x2, %4, %0"
[(set_attr "type" "fpcmove") [(set_attr "type" "fpcmove")])
(set_attr "length" "1")])
(define_insn "movdf_cc_sp64" (define_insn "movdf_cc_sp64"
[(set (match_operand:DF 0 "register_operand" "=e,e") [(set (match_operand:DF 0 "register_operand" "=e,e")
...@@ -4257,7 +4166,7 @@ ...@@ -4257,7 +4166,7 @@
fmovd%C1\\t%x2, %3, %0 fmovd%C1\\t%x2, %3, %0
fmovd%c1\\t%x2, %4, %0" fmovd%c1\\t%x2, %4, %0"
[(set_attr "type" "fpcmove") [(set_attr "type" "fpcmove")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "*movtf_cc_hq_sp64" (define_insn "*movtf_cc_hq_sp64"
[(set (match_operand:TF 0 "register_operand" "=e,e") [(set (match_operand:TF 0 "register_operand" "=e,e")
...@@ -4270,8 +4179,7 @@ ...@@ -4270,8 +4179,7 @@
"@ "@
fmovq%C1\\t%x2, %3, %0 fmovq%C1\\t%x2, %3, %0
fmovq%c1\\t%x2, %4, %0" fmovq%c1\\t%x2, %4, %0"
[(set_attr "type" "fpcmove") [(set_attr "type" "fpcmove")])
(set_attr "length" "1")])
(define_insn "*movtf_cc_sp64" (define_insn "*movtf_cc_sp64"
[(set (match_operand:TF 0 "register_operand" "=e,e") [(set (match_operand:TF 0 "register_operand" "=e,e")
...@@ -4282,8 +4190,7 @@ ...@@ -4282,8 +4190,7 @@
(match_operand:TF 4 "register_operand" "0,e")))] (match_operand:TF 4 "register_operand" "0,e")))]
"TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD" "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
"#" "#"
[(set_attr "type" "fpcmove") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:TF 0 "register_operand" "") [(set (match_operand:TF 0 "register_operand" "")
...@@ -4344,8 +4251,7 @@ ...@@ -4344,8 +4251,7 @@
"@ "@
movr%D1\\t%2, %r3, %0 movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0" movr%d1\\t%2, %r4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
(define_insn "*movhi_cc_reg_sp64" (define_insn "*movhi_cc_reg_sp64"
[(set (match_operand:HI 0 "register_operand" "=r,r") [(set (match_operand:HI 0 "register_operand" "=r,r")
...@@ -4358,8 +4264,7 @@ ...@@ -4358,8 +4264,7 @@
"@ "@
movr%D1\\t%2, %r3, %0 movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0" movr%d1\\t%2, %r4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
(define_insn "*movsi_cc_reg_sp64" (define_insn "*movsi_cc_reg_sp64"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
...@@ -4372,8 +4277,7 @@ ...@@ -4372,8 +4277,7 @@
"@ "@
movr%D1\\t%2, %r3, %0 movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0" movr%d1\\t%2, %r4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
;; ??? The constraints of operands 3,4 need work. ;; ??? The constraints of operands 3,4 need work.
(define_insn "*movdi_cc_reg_sp64" (define_insn "*movdi_cc_reg_sp64"
...@@ -4387,8 +4291,7 @@ ...@@ -4387,8 +4291,7 @@
"@ "@
movr%D1\\t%2, %r3, %0 movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0" movr%d1\\t%2, %r4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
(define_insn "*movdi_cc_reg_sp64_trunc" (define_insn "*movdi_cc_reg_sp64_trunc"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
...@@ -4401,8 +4304,7 @@ ...@@ -4401,8 +4304,7 @@
"@ "@
movr%D1\\t%2, %r3, %0 movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0" movr%d1\\t%2, %r4, %0"
[(set_attr "type" "cmove") [(set_attr "type" "cmove")])
(set_attr "length" "1")])
(define_insn "*movsf_cc_reg_sp64" (define_insn "*movsf_cc_reg_sp64"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
...@@ -4415,8 +4317,7 @@ ...@@ -4415,8 +4317,7 @@
"@ "@
fmovrs%D1\\t%2, %3, %0 fmovrs%D1\\t%2, %3, %0
fmovrs%d1\\t%2, %4, %0" fmovrs%d1\\t%2, %4, %0"
[(set_attr "type" "fpcmove") [(set_attr "type" "fpcmove")])
(set_attr "length" "1")])
(define_insn "movdf_cc_reg_sp64" (define_insn "movdf_cc_reg_sp64"
[(set (match_operand:DF 0 "register_operand" "=e,e") [(set (match_operand:DF 0 "register_operand" "=e,e")
...@@ -4430,7 +4331,7 @@ ...@@ -4430,7 +4331,7 @@
fmovrd%D1\\t%2, %3, %0 fmovrd%D1\\t%2, %3, %0
fmovrd%d1\\t%2, %4, %0" fmovrd%d1\\t%2, %4, %0"
[(set_attr "type" "fpcmove") [(set_attr "type" "fpcmove")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "*movtf_cc_reg_hq_sp64" (define_insn "*movtf_cc_reg_hq_sp64"
[(set (match_operand:TF 0 "register_operand" "=e,e") [(set (match_operand:TF 0 "register_operand" "=e,e")
...@@ -4443,8 +4344,7 @@ ...@@ -4443,8 +4344,7 @@
"@ "@
fmovrq%D1\\t%2, %3, %0 fmovrq%D1\\t%2, %3, %0
fmovrq%d1\\t%2, %4, %0" fmovrq%d1\\t%2, %4, %0"
[(set_attr "type" "fpcmove") [(set_attr "type" "fpcmove")])
(set_attr "length" "1")])
(define_insn "*movtf_cc_reg_sp64" (define_insn "*movtf_cc_reg_sp64"
[(set (match_operand:TF 0 "register_operand" "=e,e") [(set (match_operand:TF 0 "register_operand" "=e,e")
...@@ -4455,8 +4355,7 @@ ...@@ -4455,8 +4355,7 @@
(match_operand:TF 4 "register_operand" "0,e")))] (match_operand:TF 4 "register_operand" "0,e")))]
"TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD" "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
"#" "#"
[(set_attr "type" "fpcmove") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:TF 0 "register_operand" "") [(set (match_operand:TF 0 "register_operand" "")
...@@ -4542,8 +4441,7 @@ ...@@ -4542,8 +4441,7 @@
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"" ""
"lduh\\t%1, %0" "lduh\\t%1, %0"
[(set_attr "type" "load") [(set_attr "type" "load")])
(set_attr "length" "1")])
(define_expand "zero_extendqihi2" (define_expand "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
...@@ -4558,8 +4456,7 @@ ...@@ -4558,8 +4456,7 @@
"@ "@
and\\t%1, 0xff, %0 and\\t%1, 0xff, %0
ldub\\t%1, %0" ldub\\t%1, %0"
[(set_attr "type" "ialu,load") [(set_attr "type" "*,load")])
(set_attr "length" "1")])
(define_expand "zero_extendqisi2" (define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -4574,8 +4471,7 @@ ...@@ -4574,8 +4471,7 @@
"@ "@
and\\t%1, 0xff, %0 and\\t%1, 0xff, %0
ldub\\t%1, %0" ldub\\t%1, %0"
[(set_attr "type" "ialu,load") [(set_attr "type" "*,load")])
(set_attr "length" "1")])
(define_expand "zero_extendqidi2" (define_expand "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -4590,8 +4486,7 @@ ...@@ -4590,8 +4486,7 @@
"@ "@
and\\t%1, 0xff, %0 and\\t%1, 0xff, %0
ldub\\t%1, %0" ldub\\t%1, %0"
[(set_attr "type" "ialu,load") [(set_attr "type" "*,load")])
(set_attr "length" "1")])
(define_expand "zero_extendhidi2" (define_expand "zero_extendhidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -4622,8 +4517,7 @@ ...@@ -4622,8 +4517,7 @@
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"lduh\\t%1, %0" "lduh\\t%1, %0"
[(set_attr "type" "load") [(set_attr "type" "load")])
(set_attr "length" "1")])
;; ??? Write truncdisi pattern using sra? ;; ??? Write truncdisi pattern using sra?
...@@ -4641,8 +4535,7 @@ ...@@ -4641,8 +4535,7 @@
"@ "@
srl\\t%1, 0, %0 srl\\t%1, 0, %0
lduw\\t%1, %0" lduw\\t%1, %0"
[(set_attr "type" "shift,load") [(set_attr "type" "shift,load")])
(set_attr "length" "1")])
(define_insn "*zero_extendsidi2_insn_sp32" (define_insn "*zero_extendsidi2_insn_sp32"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -4692,8 +4585,7 @@ ...@@ -4692,8 +4585,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"andcc\\t%0, 0xff, %%g0" "andcc\\t%0, 0xff, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_zero_qi" (define_insn "*cmp_zero_qi"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -4701,8 +4593,7 @@ ...@@ -4701,8 +4593,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"andcc\\t%0, 0xff, %%g0" "andcc\\t%0, 0xff, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqisi2_set" (define_insn "*cmp_zero_extendqisi2_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -4712,8 +4603,7 @@ ...@@ -4712,8 +4603,7 @@
(zero_extend:SI (match_dup 1)))] (zero_extend:SI (match_dup 1)))]
"" ""
"andcc\\t%1, 0xff, %0" "andcc\\t%1, 0xff, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqisi2_andcc_set" (define_insn "*cmp_zero_extendqisi2_andcc_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -4724,8 +4614,7 @@ ...@@ -4724,8 +4614,7 @@
(zero_extend:SI (subreg:QI (match_dup 1) 0)))] (zero_extend:SI (subreg:QI (match_dup 1) 0)))]
"" ""
"andcc\\t%1, 0xff, %0" "andcc\\t%1, 0xff, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqidi2" (define_insn "*cmp_zero_extendqidi2"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -4733,8 +4622,7 @@ ...@@ -4733,8 +4622,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"andcc\\t%0, 0xff, %%g0" "andcc\\t%0, 0xff, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_zero_qi_sp64" (define_insn "*cmp_zero_qi_sp64"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -4742,8 +4630,7 @@ ...@@ -4742,8 +4630,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"andcc\\t%0, 0xff, %%g0" "andcc\\t%0, 0xff, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqidi2_set" (define_insn "*cmp_zero_extendqidi2_set"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -4753,8 +4640,7 @@ ...@@ -4753,8 +4640,7 @@
(zero_extend:DI (match_dup 1)))] (zero_extend:DI (match_dup 1)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"andcc\\t%1, 0xff, %0" "andcc\\t%1, 0xff, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqidi2_andcc_set" (define_insn "*cmp_zero_extendqidi2_andcc_set"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -4765,8 +4651,7 @@ ...@@ -4765,8 +4651,7 @@
(zero_extend:DI (subreg:QI (match_dup 1) 0)))] (zero_extend:DI (subreg:QI (match_dup 1) 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"andcc\\t%1, 0xff, %0" "andcc\\t%1, 0xff, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare. ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
...@@ -4776,8 +4661,7 @@ ...@@ -4776,8 +4661,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"andcc\\t%0, 0xff, %%g0" "andcc\\t%0, 0xff, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_siqi_trunc_set" (define_insn "*cmp_siqi_trunc_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -4787,8 +4671,7 @@ ...@@ -4787,8 +4671,7 @@
(subreg:QI (match_dup 1) 3))] (subreg:QI (match_dup 1) 3))]
"" ""
"andcc\\t%1, 0xff, %0" "andcc\\t%1, 0xff, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_diqi_trunc" (define_insn "*cmp_diqi_trunc"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -4796,8 +4679,7 @@ ...@@ -4796,8 +4679,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"andcc\\t%0, 0xff, %%g0" "andcc\\t%0, 0xff, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_diqi_trunc_set" (define_insn "*cmp_diqi_trunc_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -4807,8 +4689,7 @@ ...@@ -4807,8 +4689,7 @@
(subreg:QI (match_dup 1) 7))] (subreg:QI (match_dup 1) 7))]
"TARGET_ARCH64" "TARGET_ARCH64"
"andcc\\t%1, 0xff, %0" "andcc\\t%1, 0xff, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
;;- sign extension instructions ;;- sign extension instructions
...@@ -4845,8 +4726,7 @@ ...@@ -4845,8 +4726,7 @@
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"" ""
"ldsh\\t%1, %0" "ldsh\\t%1, %0"
[(set_attr "type" "sload") [(set_attr "type" "sload")])
(set_attr "length" "1")])
(define_expand "extendqihi2" (define_expand "extendqihi2"
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
...@@ -4886,8 +4766,7 @@ ...@@ -4886,8 +4766,7 @@
(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"" ""
"ldsb\\t%1, %0" "ldsb\\t%1, %0"
[(set_attr "type" "sload") [(set_attr "type" "sload")])
(set_attr "length" "1")])
(define_expand "extendqisi2" (define_expand "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -4918,8 +4797,7 @@ ...@@ -4918,8 +4797,7 @@
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"" ""
"ldsb\\t%1, %0" "ldsb\\t%1, %0"
[(set_attr "type" "sload") [(set_attr "type" "sload")])
(set_attr "length" "1")])
(define_expand "extendqidi2" (define_expand "extendqidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -4950,8 +4828,7 @@ ...@@ -4950,8 +4828,7 @@
(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"ldsb\\t%1, %0" "ldsb\\t%1, %0"
[(set_attr "type" "sload") [(set_attr "type" "sload")])
(set_attr "length" "1")])
(define_expand "extendhidi2" (define_expand "extendhidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -4982,8 +4859,7 @@ ...@@ -4982,8 +4859,7 @@
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"ldsh\\t%1, %0" "ldsh\\t%1, %0"
[(set_attr "type" "sload") [(set_attr "type" "sload")])
(set_attr "length" "1")])
(define_expand "extendsidi2" (define_expand "extendsidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -4998,8 +4874,7 @@ ...@@ -4998,8 +4874,7 @@
"@ "@
sra\\t%1, 0, %0 sra\\t%1, 0, %0
ldsw\\t%1, %0" ldsw\\t%1, %0"
[(set_attr "type" "shift,sload") [(set_attr "type" "shift,sload")])
(set_attr "length" "1")])
;; Special pattern for optimizing bit-field compares. This is needed ;; Special pattern for optimizing bit-field compares. This is needed
;; because combine uses this as a canonical form. ;; because combine uses this as a canonical form.
...@@ -5029,8 +4904,7 @@ ...@@ -5029,8 +4904,7 @@
operands[1] = GEN_INT (mask); operands[1] = GEN_INT (mask);
return \"andcc\\t%0, %1, %%g0\"; return \"andcc\\t%0, %1, %%g0\";
}" }"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_zero_extract_sp64" (define_insn "*cmp_zero_extract_sp64"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -5058,8 +4932,7 @@ ...@@ -5058,8 +4932,7 @@
operands[1] = GEN_INT (mask); operands[1] = GEN_INT (mask);
return \"andcc\\t%0, %1, %%g0\"; return \"andcc\\t%0, %1, %%g0\";
}" }"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
;; Conversions between float, double and long double. ;; Conversions between float, double and long double.
...@@ -5070,7 +4943,7 @@ ...@@ -5070,7 +4943,7 @@
"TARGET_FPU" "TARGET_FPU"
"fstod\\t%1, %0" "fstod\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_expand "extendsftf2" (define_expand "extendsftf2"
[(set (match_operand:TF 0 "register_operand" "=e") [(set (match_operand:TF 0 "register_operand" "=e")
...@@ -5105,8 +4978,7 @@ ...@@ -5105,8 +4978,7 @@
(match_operand:SF 1 "register_operand" "f")))] (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fstoq\\t%1, %0" "fstoq\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_expand "extenddftf2" (define_expand "extenddftf2"
[(set (match_operand:TF 0 "register_operand" "=e") [(set (match_operand:TF 0 "register_operand" "=e")
...@@ -5141,8 +5013,7 @@ ...@@ -5141,8 +5013,7 @@
(match_operand:DF 1 "register_operand" "e")))] (match_operand:DF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fdtoq\\t%1, %0" "fdtoq\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_insn "truncdfsf2" (define_insn "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
...@@ -5151,7 +5022,7 @@ ...@@ -5151,7 +5022,7 @@
"TARGET_FPU" "TARGET_FPU"
"fdtos\\t%1, %0" "fdtos\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_expand "trunctfsf2" (define_expand "trunctfsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
...@@ -5185,8 +5056,7 @@ ...@@ -5185,8 +5056,7 @@
(match_operand:TF 1 "register_operand" "e")))] (match_operand:TF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fqtos\\t%1, %0" "fqtos\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_expand "trunctfdf2" (define_expand "trunctfdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
...@@ -5220,8 +5090,7 @@ ...@@ -5220,8 +5090,7 @@
(match_operand:TF 1 "register_operand" "e")))] (match_operand:TF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fqtod\\t%1, %0" "fqtod\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
;; Conversion between fixed point and floating point. ;; Conversion between fixed point and floating point.
...@@ -5231,7 +5100,7 @@ ...@@ -5231,7 +5100,7 @@
"TARGET_FPU" "TARGET_FPU"
"fitos\\t%1, %0" "fitos\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "floatsidf2" (define_insn "floatsidf2"
[(set (match_operand:DF 0 "register_operand" "=e") [(set (match_operand:DF 0 "register_operand" "=e")
...@@ -5239,7 +5108,7 @@ ...@@ -5239,7 +5108,7 @@
"TARGET_FPU" "TARGET_FPU"
"fitod\\t%1, %0" "fitod\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_expand "floatsitf2" (define_expand "floatsitf2"
[(set (match_operand:TF 0 "register_operand" "=e") [(set (match_operand:TF 0 "register_operand" "=e")
...@@ -5272,8 +5141,7 @@ ...@@ -5272,8 +5141,7 @@
(float:TF (match_operand:SI 1 "register_operand" "f")))] (float:TF (match_operand:SI 1 "register_operand" "f")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fitoq\\t%1, %0" "fitoq\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_expand "floatunssitf2" (define_expand "floatunssitf2"
[(set (match_operand:TF 0 "register_operand" "=e") [(set (match_operand:TF 0 "register_operand" "=e")
...@@ -5306,7 +5174,7 @@ ...@@ -5306,7 +5174,7 @@
"TARGET_V9 && TARGET_FPU" "TARGET_V9 && TARGET_FPU"
"fxtos\\t%1, %0" "fxtos\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "floatdidf2" (define_insn "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "=e") [(set (match_operand:DF 0 "register_operand" "=e")
...@@ -5314,7 +5182,7 @@ ...@@ -5314,7 +5182,7 @@
"TARGET_V9 && TARGET_FPU" "TARGET_V9 && TARGET_FPU"
"fxtod\\t%1, %0" "fxtod\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_expand "floatditf2" (define_expand "floatditf2"
[(set (match_operand:TF 0 "register_operand" "=e") [(set (match_operand:TF 0 "register_operand" "=e")
...@@ -5347,8 +5215,7 @@ ...@@ -5347,8 +5215,7 @@
(float:TF (match_operand:DI 1 "register_operand" "e")))] (float:TF (match_operand:DI 1 "register_operand" "e")))]
"TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
"fxtoq\\t%1, %0" "fxtoq\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_expand "floatunsditf2" (define_expand "floatunsditf2"
[(set (match_operand:TF 0 "register_operand" "=e") [(set (match_operand:TF 0 "register_operand" "=e")
...@@ -5382,7 +5249,7 @@ ...@@ -5382,7 +5249,7 @@
"TARGET_FPU" "TARGET_FPU"
"fstoi\\t%1, %0" "fstoi\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "fix_truncdfsi2" (define_insn "fix_truncdfsi2"
[(set (match_operand:SI 0 "register_operand" "=f") [(set (match_operand:SI 0 "register_operand" "=f")
...@@ -5390,7 +5257,7 @@ ...@@ -5390,7 +5257,7 @@
"TARGET_FPU" "TARGET_FPU"
"fdtoi\\t%1, %0" "fdtoi\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_expand "fix_trunctfsi2" (define_expand "fix_trunctfsi2"
[(set (match_operand:SI 0 "register_operand" "=f") [(set (match_operand:SI 0 "register_operand" "=f")
...@@ -5422,8 +5289,7 @@ ...@@ -5422,8 +5289,7 @@
(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fqtoi\\t%1, %0" "fqtoi\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_expand "fixuns_trunctfsi2" (define_expand "fixuns_trunctfsi2"
[(set (match_operand:SI 0 "register_operand" "=f") [(set (match_operand:SI 0 "register_operand" "=f")
...@@ -5455,7 +5321,7 @@ ...@@ -5455,7 +5321,7 @@
"TARGET_V9 && TARGET_FPU" "TARGET_V9 && TARGET_FPU"
"fstox\\t%1, %0" "fstox\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "fix_truncdfdi2" (define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=e")
...@@ -5463,7 +5329,7 @@ ...@@ -5463,7 +5329,7 @@
"TARGET_V9 && TARGET_FPU" "TARGET_V9 && TARGET_FPU"
"fdtox\\t%1, %0" "fdtox\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_expand "fix_trunctfdi2" (define_expand "fix_trunctfdi2"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=e")
...@@ -5495,8 +5361,7 @@ ...@@ -5495,8 +5361,7 @@
(fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] (fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
"TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
"fqtox\\t%1, %0" "fqtox\\t%1, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_expand "fixuns_trunctfdi2" (define_expand "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "register_operand" "=f") [(set (match_operand:DI 0 "register_operand" "=f")
...@@ -5648,7 +5513,7 @@ ...@@ -5648,7 +5513,7 @@
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"" ""
"addx\\t%1, %2, %0" "addx\\t%1, %2, %0"
[(set_attr "length" "1")]) [(set_attr "type" "misc")])
(define_insn "*addx_extend_sp32" (define_insn "*addx_extend_sp32"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -5678,8 +5543,7 @@ ...@@ -5678,8 +5543,7 @@
(ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
"TARGET_ARCH64" "TARGET_ARCH64"
"addx\\t%r1, %2, %0" "addx\\t%r1, %2, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "subx" (define_insn "subx"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -5688,8 +5552,7 @@ ...@@ -5688,8 +5552,7 @@
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"" ""
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*subx_extend_sp64" (define_insn "*subx_extend_sp64"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -5698,8 +5561,7 @@ ...@@ -5698,8 +5561,7 @@
(ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
"TARGET_ARCH64" "TARGET_ARCH64"
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "*subx_extend" (define_insn "*subx_extend"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -5729,8 +5591,7 @@ ...@@ -5729,8 +5591,7 @@
(clobber (reg:CC 100))] (clobber (reg:CC 100))]
"! TARGET_ARCH64" "! TARGET_ARCH64"
"#" "#"
[(set_attr "type" "multi") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -5755,8 +5616,7 @@ ...@@ -5755,8 +5616,7 @@
(plus:DI (match_operand:DI 1 "arith_double_operand" "%r") (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))] (match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"add\\t%1, %2, %0" "add\\t%1, %2, %0")
[(set_attr "length" "1")])
(define_expand "addsi3" (define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -5786,8 +5646,7 @@ ...@@ -5786,8 +5646,7 @@
"@ "@
add\\t%1, %2, %0 add\\t%1, %2, %0
fpadd32s\\t%1, %2, %0" fpadd32s\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_plus" (define_insn "*cmp_cc_plus"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -5796,8 +5655,7 @@ ...@@ -5796,8 +5655,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"addcc\\t%0, %1, %%g0" "addcc\\t%0, %1, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_plus" (define_insn "*cmp_ccx_plus"
[(set (reg:CCX_NOOV 100) [(set (reg:CCX_NOOV 100)
...@@ -5806,8 +5664,7 @@ ...@@ -5806,8 +5664,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"addcc\\t%0, %1, %%g0" "addcc\\t%0, %1, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_plus_set" (define_insn "*cmp_cc_plus_set"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -5818,8 +5675,7 @@ ...@@ -5818,8 +5675,7 @@
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"" ""
"addcc\\t%1, %2, %0" "addcc\\t%1, %2, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_plus_set" (define_insn "*cmp_ccx_plus_set"
[(set (reg:CCX_NOOV 100) [(set (reg:CCX_NOOV 100)
...@@ -5830,8 +5686,7 @@ ...@@ -5830,8 +5686,7 @@
(plus:DI (match_dup 1) (match_dup 2)))] (plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"addcc\\t%1, %2, %0" "addcc\\t%1, %2, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_expand "subdi3" (define_expand "subdi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -5932,8 +5787,7 @@ ...@@ -5932,8 +5787,7 @@
(clobber (reg:CC 100))] (clobber (reg:CC 100))]
"! TARGET_ARCH64" "! TARGET_ARCH64"
"#" "#"
[(set_attr "type" "multi") [(set_attr "length" "2")])
(set_attr "length" "2")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -5958,8 +5812,7 @@ ...@@ -5958,8 +5812,7 @@
(minus:DI (match_operand:DI 1 "register_operand" "r") (minus:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))] (match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"sub\\t%1, %2, %0" "sub\\t%1, %2, %0")
[(set_attr "length" "1")])
(define_expand "subsi3" (define_expand "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -5985,8 +5838,7 @@ ...@@ -5985,8 +5838,7 @@
"@ "@
sub\\t%1, %2, %0 sub\\t%1, %2, %0
fpsub32s\\t%1, %2, %0" fpsub32s\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1")])
(define_insn "*cmp_minus_cc" (define_insn "*cmp_minus_cc"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -5995,8 +5847,7 @@ ...@@ -5995,8 +5847,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"subcc\\t%r0, %1, %%g0" "subcc\\t%r0, %1, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_minus_ccx" (define_insn "*cmp_minus_ccx"
[(set (reg:CCX_NOOV 100) [(set (reg:CCX_NOOV 100)
...@@ -6005,8 +5856,7 @@ ...@@ -6005,8 +5856,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"subcc\\t%0, %1, %%g0" "subcc\\t%0, %1, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "cmp_minus_cc_set" (define_insn "cmp_minus_cc_set"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -6017,8 +5867,7 @@ ...@@ -6017,8 +5867,7 @@
(minus:SI (match_dup 1) (match_dup 2)))] (minus:SI (match_dup 1) (match_dup 2)))]
"" ""
"subcc\\t%r1, %2, %0" "subcc\\t%r1, %2, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_minus_ccx_set" (define_insn "*cmp_minus_ccx_set"
[(set (reg:CCX_NOOV 100) [(set (reg:CCX_NOOV 100)
...@@ -6029,8 +5878,7 @@ ...@@ -6029,8 +5878,7 @@
(minus:DI (match_dup 1) (match_dup 2)))] (minus:DI (match_dup 1) (match_dup 2)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"subcc\\t%1, %2, %0" "subcc\\t%1, %2, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
;; Integer Multiply/Divide. ;; Integer Multiply/Divide.
...@@ -6043,8 +5891,7 @@ ...@@ -6043,8 +5891,7 @@
(match_operand:SI 2 "arith_operand" "rI")))] (match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_HARD_MUL" "TARGET_HARD_MUL"
"smul\\t%1, %2, %0" "smul\\t%1, %2, %0"
[(set_attr "type" "imul") [(set_attr "type" "imul")])
(set_attr "length" "1")])
(define_expand "muldi3" (define_expand "muldi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -6066,8 +5913,7 @@ ...@@ -6066,8 +5913,7 @@
(match_operand:DI 2 "arith_double_operand" "rHI")))] (match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"mulx\\t%1, %2, %0" "mulx\\t%1, %2, %0"
[(set_attr "type" "imul") [(set_attr "type" "imul")])
(set_attr "length" "1")])
;; V8plus wide multiply. ;; V8plus wide multiply.
;; XXX ;; XXX
...@@ -6098,7 +5944,8 @@ ...@@ -6098,7 +5944,8 @@
else else
return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\";
}" }"
[(set_attr "length" "9,8")]) [(set_attr "type" "multi")
(set_attr "length" "9,8")])
(define_insn "*cmp_mul_set" (define_insn "*cmp_mul_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -6109,8 +5956,7 @@ ...@@ -6109,8 +5956,7 @@
(mult:SI (match_dup 1) (match_dup 2)))] (mult:SI (match_dup 1) (match_dup 2)))]
"TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS" "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
"smulcc\\t%1, %2, %0" "smulcc\\t%1, %2, %0"
[(set_attr "type" "imul") [(set_attr "type" "imul")])
(set_attr "length" "1")])
(define_expand "mulsidi3" (define_expand "mulsidi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -6148,7 +5994,8 @@ ...@@ -6148,7 +5994,8 @@
"@ "@
smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
[(set_attr "length" "2,3")]) [(set_attr "type" "multi")
(set_attr "length" "2,3")])
;; XXX ;; XXX
(define_insn "const_mulsidi3_v8plus" (define_insn "const_mulsidi3_v8plus"
...@@ -6160,7 +6007,8 @@ ...@@ -6160,7 +6007,8 @@
"@ "@
smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
[(set_attr "length" "2,3")]) [(set_attr "type" "multi")
(set_attr "length" "2,3")])
;; XXX ;; XXX
(define_insn "*mulsidi3_sp32" (define_insn "*mulsidi3_sp32"
...@@ -6172,7 +6020,10 @@ ...@@ -6172,7 +6020,10 @@
{ {
return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
}" }"
[(set (attr "length") [(set (attr "type")
(if_then_else (eq_attr "isa" "sparclet")
(const_string "imul") (const_string "multi")))
(set (attr "length")
(if_then_else (eq_attr "isa" "sparclet") (if_then_else (eq_attr "isa" "sparclet")
(const_int 1) (const_int 2)))]) (const_int 1) (const_int 2)))])
...@@ -6182,7 +6033,7 @@ ...@@ -6182,7 +6033,7 @@
(sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"smul\\t%1, %2, %0" "smul\\t%1, %2, %0"
[(set_attr "length" "1")]) [(set_attr "type" "imul")])
;; Extra pattern, because sign_extend of a constant isn't valid. ;; Extra pattern, because sign_extend of a constant isn't valid.
...@@ -6196,7 +6047,10 @@ ...@@ -6196,7 +6047,10 @@
{ {
return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
}" }"
[(set (attr "length") [(set (attr "type")
(if_then_else (eq_attr "isa" "sparclet")
(const_string "imul") (const_string "multi")))
(set (attr "length")
(if_then_else (eq_attr "isa" "sparclet") (if_then_else (eq_attr "isa" "sparclet")
(const_int 1) (const_int 2)))]) (const_int 1) (const_int 2)))])
...@@ -6206,7 +6060,7 @@ ...@@ -6206,7 +6060,7 @@
(match_operand:SI 2 "small_int" "I")))] (match_operand:SI 2 "small_int" "I")))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"smul\\t%1, %2, %0" "smul\\t%1, %2, %0"
[(set_attr "length" "1")]) [(set_attr "type" "imul")])
(define_expand "smulsi3_highpart" (define_expand "smulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -6250,7 +6104,8 @@ ...@@ -6250,7 +6104,8 @@
"@ "@
smul\\t%1, %2, %0\;srlx\\t%0, %3, %0 smul\\t%1, %2, %0\;srlx\\t%0, %3, %0
smul\\t%1, %2, %4\;srlx\\t%4, %3, %0" smul\\t%1, %2, %4\;srlx\\t%4, %3, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; The combiner changes TRUNCATE in the previous pattern to SUBREG. ;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
;; XXX ;; XXX
...@@ -6267,7 +6122,8 @@ ...@@ -6267,7 +6122,8 @@
"@ "@
smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; XXX ;; XXX
(define_insn "const_smulsi3_highpart_v8plus" (define_insn "const_smulsi3_highpart_v8plus"
...@@ -6281,7 +6137,8 @@ ...@@ -6281,7 +6137,8 @@
"@ "@
smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; XXX ;; XXX
(define_insn "*smulsi3_highpart_sp32" (define_insn "*smulsi3_highpart_sp32"
...@@ -6292,7 +6149,8 @@ ...@@ -6292,7 +6149,8 @@
(const_int 32))))] (const_int 32))))]
"TARGET_HARD_MUL32" "TARGET_HARD_MUL32"
"smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; XXX ;; XXX
(define_insn "const_smulsi3_highpart" (define_insn "const_smulsi3_highpart"
...@@ -6303,7 +6161,8 @@ ...@@ -6303,7 +6161,8 @@
(const_int 32))))] (const_int 32))))]
"TARGET_HARD_MUL32" "TARGET_HARD_MUL32"
"smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_expand "umulsidi3" (define_expand "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -6339,7 +6198,8 @@ ...@@ -6339,7 +6198,8 @@
"@ "@
umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
[(set_attr "length" "2,3")]) [(set_attr "type" "multi")
(set_attr "length" "2,3")])
;; XXX ;; XXX
(define_insn "*umulsidi3_sp32" (define_insn "*umulsidi3_sp32"
...@@ -6351,7 +6211,10 @@ ...@@ -6351,7 +6211,10 @@
{ {
return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
}" }"
[(set (attr "length") [(set (attr "type")
(if_then_else (eq_attr "isa" "sparclet")
(const_string "imul") (const_string "multi")))
(set (attr "length")
(if_then_else (eq_attr "isa" "sparclet") (if_then_else (eq_attr "isa" "sparclet")
(const_int 1) (const_int 2)))]) (const_int 1) (const_int 2)))])
...@@ -6361,7 +6224,7 @@ ...@@ -6361,7 +6224,7 @@
(zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"umul\\t%1, %2, %0" "umul\\t%1, %2, %0"
[(set_attr "length" "1")]) [(set_attr "type" "imul")])
;; Extra pattern, because sign_extend of a constant isn't valid. ;; Extra pattern, because sign_extend of a constant isn't valid.
...@@ -6375,7 +6238,10 @@ ...@@ -6375,7 +6238,10 @@
{ {
return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
}" }"
[(set (attr "length") [(set (attr "type")
(if_then_else (eq_attr "isa" "sparclet")
(const_string "imul") (const_string "multi")))
(set (attr "length")
(if_then_else (eq_attr "isa" "sparclet") (if_then_else (eq_attr "isa" "sparclet")
(const_int 1) (const_int 2)))]) (const_int 1) (const_int 2)))])
...@@ -6385,7 +6251,7 @@ ...@@ -6385,7 +6251,7 @@
(match_operand:SI 2 "uns_small_int" "")))] (match_operand:SI 2 "uns_small_int" "")))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"umul\\t%1, %2, %0" "umul\\t%1, %2, %0"
[(set_attr "length" "1")]) [(set_attr "type" "imul")])
;; XXX ;; XXX
(define_insn "const_umulsidi3_v8plus" (define_insn "const_umulsidi3_v8plus"
...@@ -6397,7 +6263,8 @@ ...@@ -6397,7 +6263,8 @@
"@ "@
umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
[(set_attr "length" "2,3")]) [(set_attr "type" "multi")
(set_attr "length" "2,3")])
(define_expand "umulsi3_highpart" (define_expand "umulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -6441,7 +6308,8 @@ ...@@ -6441,7 +6308,8 @@
"@ "@
umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; XXX ;; XXX
(define_insn "const_umulsi3_highpart_v8plus" (define_insn "const_umulsi3_highpart_v8plus"
...@@ -6455,7 +6323,8 @@ ...@@ -6455,7 +6323,8 @@
"@ "@
umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; XXX ;; XXX
(define_insn "*umulsi3_highpart_sp32" (define_insn "*umulsi3_highpart_sp32"
...@@ -6466,7 +6335,8 @@ ...@@ -6466,7 +6335,8 @@
(const_int 32))))] (const_int 32))))]
"TARGET_HARD_MUL32" "TARGET_HARD_MUL32"
"umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; XXX ;; XXX
(define_insn "const_umulsi3_highpart" (define_insn "const_umulsi3_highpart"
...@@ -6477,7 +6347,8 @@ ...@@ -6477,7 +6347,8 @@
(const_int 32))))] (const_int 32))))]
"TARGET_HARD_MUL32" "TARGET_HARD_MUL32"
"umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; The v8 architecture specifies that there must be 3 instructions between ;; The v8 architecture specifies that there must be 3 instructions between
;; a y register write and a use of it for correct results. ;; a y register write and a use of it for correct results.
...@@ -6520,7 +6391,8 @@ ...@@ -6520,7 +6391,8 @@
else else
return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\"; return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\";
}" }"
[(set (attr "length") [(set_attr "type" "multi")
(set (attr "length")
(if_then_else (eq_attr "isa" "v9") (if_then_else (eq_attr "isa" "v9")
(const_int 4) (const_int 7)))]) (const_int 4) (const_int 7)))])
...@@ -6531,14 +6403,16 @@ ...@@ -6531,14 +6403,16 @@
(use (match_operand:SI 3 "register_operand" "r"))] (use (match_operand:SI 3 "register_operand" "r"))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"wr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0" "wr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "divdi3" (define_insn "divdi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(div:DI (match_operand:DI 1 "register_operand" "r") (div:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))] (match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"sdivx\\t%1, %2, %0") "sdivx\\t%1, %2, %0"
[(set_attr "type" "idiv")])
(define_insn "*cmp_sdiv_cc_set" (define_insn "*cmp_sdiv_cc_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -6556,7 +6430,8 @@ ...@@ -6556,7 +6430,8 @@
else else
return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\"; return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\";
}" }"
[(set (attr "length") [(set_attr "type" "multi")
(set (attr "length")
(if_then_else (eq_attr "isa" "v9") (if_then_else (eq_attr "isa" "v9")
(const_int 3) (const_int 6)))]) (const_int 3) (const_int 6)))])
...@@ -6588,7 +6463,8 @@ ...@@ -6588,7 +6463,8 @@
return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\"; return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\";
} }
}" }"
[(set_attr "length" "5")]) [(set_attr "type" "multi")
(set_attr "length" "5")])
(define_insn "udivsi3_sp64" (define_insn "udivsi3_sp64"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -6596,14 +6472,16 @@ ...@@ -6596,14 +6472,16 @@
(match_operand:SI 2 "input_operand" "rI")))] (match_operand:SI 2 "input_operand" "rI")))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"wr\\t%%g0, 0, %%y\\n\\tudiv\\t%1, %2, %0" "wr\\t%%g0, 0, %%y\\n\\tudiv\\t%1, %2, %0"
[(set_attr "length" "2")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "udivdi3" (define_insn "udivdi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(udiv:DI (match_operand:DI 1 "register_operand" "r") (udiv:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))] (match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"udivx\\t%1, %2, %0") "udivx\\t%1, %2, %0"
[(set_attr "type" "idiv")])
(define_insn "*cmp_udiv_cc_set" (define_insn "*cmp_udiv_cc_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -6621,7 +6499,8 @@ ...@@ -6621,7 +6499,8 @@
else else
return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\"; return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\";
}" }"
[(set (attr "length") [(set_attr "type" "multi")
(set (attr "length")
(if_then_else (eq_attr "isa" "v9") (if_then_else (eq_attr "isa" "v9")
(const_int 2) (const_int 5)))]) (const_int 2) (const_int 5)))])
...@@ -6634,8 +6513,7 @@ ...@@ -6634,8 +6513,7 @@
(match_operand:SI 3 "register_operand" "0")))] (match_operand:SI 3 "register_operand" "0")))]
"TARGET_SPARCLET" "TARGET_SPARCLET"
"smac\\t%1, %2, %0" "smac\\t%1, %2, %0"
[(set_attr "type" "imul") [(set_attr "type" "imul")])
(set_attr "length" "1")])
(define_insn "*smacdi" (define_insn "*smacdi"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -6646,8 +6524,7 @@ ...@@ -6646,8 +6524,7 @@
(match_operand:DI 3 "register_operand" "0")))] (match_operand:DI 3 "register_operand" "0")))]
"TARGET_SPARCLET" "TARGET_SPARCLET"
"smacd\\t%1, %2, %L0" "smacd\\t%1, %2, %L0"
[(set_attr "type" "imul") [(set_attr "type" "imul")])
(set_attr "length" "1")])
(define_insn "*umacdi" (define_insn "*umacdi"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -6658,8 +6535,7 @@ ...@@ -6658,8 +6535,7 @@
(match_operand:DI 3 "register_operand" "0")))] (match_operand:DI 3 "register_operand" "0")))]
"TARGET_SPARCLET" "TARGET_SPARCLET"
"umacd\\t%1, %2, %L0" "umacd\\t%1, %2, %L0"
[(set_attr "type" "imul") [(set_attr "type" "imul")])
(set_attr "length" "1")])
;;- Boolean instructions ;;- Boolean instructions
;; We define DImode `and' so with DImode `not' we can get ;; We define DImode `and' so with DImode `not' we can get
...@@ -6680,8 +6556,9 @@ ...@@ -6680,8 +6556,9 @@
"@ "@
# #
fand\\t%1, %2, %0" fand\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "2,1")]) (set_attr "length" "2,*")
(set_attr "fptype" "double")])
(define_insn "*anddi3_sp64" (define_insn "*anddi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r,b") [(set (match_operand:DI 0 "register_operand" "=r,b")
...@@ -6691,8 +6568,8 @@ ...@@ -6691,8 +6568,8 @@
"@ "@
and\\t%1, %2, %0 and\\t%1, %2, %0
fand\\t%1, %2, %0" fand\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "1,1")]) (set_attr "fptype" "double")])
(define_insn "andsi3" (define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -6702,8 +6579,7 @@ ...@@ -6702,8 +6579,7 @@
"@ "@
and\\t%1, %2, %0 and\\t%1, %2, %0
fands\\t%1, %2, %0" fands\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1,1")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -6765,8 +6641,9 @@ ...@@ -6765,8 +6641,9 @@
"@ "@
# #
fandnot1\\t%1, %2, %0" fandnot1\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "2,1")]) (set_attr "length" "2,*")
(set_attr "fptype" "double")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -6798,8 +6675,8 @@ ...@@ -6798,8 +6675,8 @@
"@ "@
andn\\t%2, %1, %0 andn\\t%2, %1, %0
fandnot1\\t%1, %2, %0" fandnot1\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "1,1")]) (set_attr "fptype" "double")])
(define_insn "*and_not_si" (define_insn "*and_not_si"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -6809,8 +6686,7 @@ ...@@ -6809,8 +6686,7 @@
"@ "@
andn\\t%2, %1, %0 andn\\t%2, %1, %0
fandnot1s\\t%1, %2, %0" fandnot1s\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1,1")])
(define_expand "iordi3" (define_expand "iordi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -6827,8 +6703,9 @@ ...@@ -6827,8 +6703,9 @@
"@ "@
# #
for\\t%1, %2, %0" for\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "2,1")]) (set_attr "length" "2,*")
(set_attr "fptype" "double")])
(define_insn "*iordi3_sp64" (define_insn "*iordi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r,b") [(set (match_operand:DI 0 "register_operand" "=r,b")
...@@ -6838,8 +6715,8 @@ ...@@ -6838,8 +6715,8 @@
"@ "@
or\\t%1, %2, %0 or\\t%1, %2, %0
for\\t%1, %2, %0" for\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "1,1")]) (set_attr "fptype" "double")])
(define_insn "iorsi3" (define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -6849,8 +6726,7 @@ ...@@ -6849,8 +6726,7 @@
"@ "@
or\\t%1, %2, %0 or\\t%1, %2, %0
fors\\t%1, %2, %0" fors\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1,1")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -6875,8 +6751,9 @@ ...@@ -6875,8 +6751,9 @@
"@ "@
# #
fornot1\\t%1, %2, %0" fornot1\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "2,1")]) (set_attr "length" "2,*")
(set_attr "fptype" "double")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -6908,8 +6785,8 @@ ...@@ -6908,8 +6785,8 @@
"@ "@
orn\\t%2, %1, %0 orn\\t%2, %1, %0
fornot1\\t%1, %2, %0" fornot1\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "1,1")]) (set_attr "fptype" "double")])
(define_insn "*or_not_si" (define_insn "*or_not_si"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -6919,8 +6796,7 @@ ...@@ -6919,8 +6796,7 @@
"@ "@
orn\\t%2, %1, %0 orn\\t%2, %1, %0
fornot1s\\t%1, %2, %0" fornot1s\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1,1")])
(define_expand "xordi3" (define_expand "xordi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -6937,8 +6813,9 @@ ...@@ -6937,8 +6813,9 @@
"@ "@
# #
fxor\\t%1, %2, %0" fxor\\t%1, %2, %0"
[(set_attr "length" "2,1") [(set_attr "type" "*,fp")
(set_attr "type" "ialu,fp")]) (set_attr "length" "2,*")
(set_attr "fptype" "double")])
(define_insn "*xordi3_sp64" (define_insn "*xordi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r,b") [(set (match_operand:DI 0 "register_operand" "=r,b")
...@@ -6948,8 +6825,8 @@ ...@@ -6948,8 +6825,8 @@
"@ "@
xor\\t%r1, %2, %0 xor\\t%r1, %2, %0
fxor\\t%1, %2, %0" fxor\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "1,1")]) (set_attr "fptype" "double")])
(define_insn "*xordi3_sp64_dbl" (define_insn "*xordi3_sp64_dbl"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -6957,9 +6834,7 @@ ...@@ -6957,9 +6834,7 @@
(match_operand:DI 2 "const64_operand" "")))] (match_operand:DI 2 "const64_operand" "")))]
"(TARGET_ARCH64 "(TARGET_ARCH64
&& HOST_BITS_PER_WIDE_INT != 64)" && HOST_BITS_PER_WIDE_INT != 64)"
"xor\\t%1, %2, %0" "xor\\t%1, %2, %0")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "xorsi3" (define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -6969,8 +6844,7 @@ ...@@ -6969,8 +6844,7 @@
"@ "@
xor\\t%r1, %2, %0 xor\\t%r1, %2, %0
fxors\\t%1, %2, %0" fxors\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1,1")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -7012,8 +6886,9 @@ ...@@ -7012,8 +6886,9 @@
"@ "@
# #
fxnor\\t%1, %2, %0" fxnor\\t%1, %2, %0"
[(set_attr "length" "2,1") [(set_attr "type" "*,fp")
(set_attr "type" "ialu,fp")]) (set_attr "length" "2,*")
(set_attr "fptype" "double")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -7045,8 +6920,8 @@ ...@@ -7045,8 +6920,8 @@
"@ "@
xnor\\t%r1, %2, %0 xnor\\t%r1, %2, %0
fxnor\\t%1, %2, %0" fxnor\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")
(set_attr "length" "1,1")]) (set_attr "fptype" "double")])
(define_insn "*xor_not_si" (define_insn "*xor_not_si"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -7056,8 +6931,7 @@ ...@@ -7056,8 +6931,7 @@
"@ "@
xnor\\t%r1, %2, %0 xnor\\t%r1, %2, %0
fxnors\\t%1, %2, %0" fxnors\\t%1, %2, %0"
[(set_attr "type" "ialu,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1,1")])
;; These correspond to the above in the case where we also (or only) ;; These correspond to the above in the case where we also (or only)
;; want to set the condition code. ;; want to set the condition code.
...@@ -7071,8 +6945,7 @@ ...@@ -7071,8 +6945,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"%A2cc\\t%0, %1, %%g0" "%A2cc\\t%0, %1, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_arith_op" (define_insn "*cmp_ccx_arith_op"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -7083,8 +6956,7 @@ ...@@ -7083,8 +6956,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"%A2cc\\t%0, %1, %%g0" "%A2cc\\t%0, %1, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_arith_op_set" (define_insn "*cmp_cc_arith_op_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -7097,8 +6969,7 @@ ...@@ -7097,8 +6969,7 @@
(match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))] (match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
"GET_CODE (operands[3]) == GET_CODE (operands[4])" "GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%A3cc\\t%1, %2, %0" "%A3cc\\t%1, %2, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_arith_op_set" (define_insn "*cmp_ccx_arith_op_set"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -7111,8 +6982,7 @@ ...@@ -7111,8 +6982,7 @@
(match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))] (match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
"TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%A3cc\\t%1, %2, %0" "%A3cc\\t%1, %2, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_xor_not" (define_insn "*cmp_cc_xor_not"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -7122,8 +6992,7 @@ ...@@ -7122,8 +6992,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"xnorcc\\t%r0, %1, %%g0" "xnorcc\\t%r0, %1, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_xor_not" (define_insn "*cmp_ccx_xor_not"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -7133,8 +7002,7 @@ ...@@ -7133,8 +7002,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"xnorcc\\t%r0, %1, %%g0" "xnorcc\\t%r0, %1, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_xor_not_set" (define_insn "*cmp_cc_xor_not_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -7146,8 +7014,7 @@ ...@@ -7146,8 +7014,7 @@
(not:SI (xor:SI (match_dup 1) (match_dup 2))))] (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
"" ""
"xnorcc\\t%r1, %2, %0" "xnorcc\\t%r1, %2, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_xor_not_set" (define_insn "*cmp_ccx_xor_not_set"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -7159,8 +7026,7 @@ ...@@ -7159,8 +7026,7 @@
(not:DI (xor:DI (match_dup 1) (match_dup 2))))] (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
"TARGET_ARCH64" "TARGET_ARCH64"
"xnorcc\\t%r1, %2, %0" "xnorcc\\t%r1, %2, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_arith_op_not" (define_insn "*cmp_cc_arith_op_not"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -7171,8 +7037,7 @@ ...@@ -7171,8 +7037,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"%B2cc\\t%r1, %0, %%g0" "%B2cc\\t%r1, %0, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_arith_op_not" (define_insn "*cmp_ccx_arith_op_not"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -7183,8 +7048,7 @@ ...@@ -7183,8 +7048,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"%B2cc\\t%r1, %0, %%g0" "%B2cc\\t%r1, %0, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_arith_op_not_set" (define_insn "*cmp_cc_arith_op_not_set"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -7198,8 +7062,7 @@ ...@@ -7198,8 +7062,7 @@
[(not:SI (match_dup 1)) (match_dup 2)]))] [(not:SI (match_dup 1)) (match_dup 2)]))]
"GET_CODE (operands[3]) == GET_CODE (operands[4])" "GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%B3cc\\t%r2, %1, %0" "%B3cc\\t%r2, %1, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_arith_op_not_set" (define_insn "*cmp_ccx_arith_op_not_set"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -7213,8 +7076,7 @@ ...@@ -7213,8 +7076,7 @@
[(not:DI (match_dup 1)) (match_dup 2)]))] [(not:DI (match_dup 1)) (match_dup 2)]))]
"TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%B3cc\\t%r2, %1, %0" "%B3cc\\t%r2, %1, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
;; We cannot use the "neg" pseudo insn because the Sun assembler ;; We cannot use the "neg" pseudo insn because the Sun assembler
;; does not know how to make it work for constants. ;; does not know how to make it work for constants.
...@@ -7268,15 +7130,13 @@ ...@@ -7268,15 +7130,13 @@
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(neg:DI (match_operand:DI 1 "register_operand" "r")))] (neg:DI (match_operand:DI 1 "register_operand" "r")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"sub\\t%%g0, %1, %0" "sub\\t%%g0, %1, %0")
[(set_attr "length" "1")])
(define_insn "negsi2" (define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "arith_operand" "rI")))] (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
"" ""
"sub\\t%%g0, %1, %0" "sub\\t%%g0, %1, %0")
[(set_attr "length" "1")])
(define_insn "*cmp_cc_neg" (define_insn "*cmp_cc_neg"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -7284,8 +7144,7 @@ ...@@ -7284,8 +7144,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"subcc\\t%%g0, %0, %%g0" "subcc\\t%%g0, %0, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_neg" (define_insn "*cmp_ccx_neg"
[(set (reg:CCX_NOOV 100) [(set (reg:CCX_NOOV 100)
...@@ -7293,8 +7152,7 @@ ...@@ -7293,8 +7152,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"subcc\\t%%g0, %0, %%g0" "subcc\\t%%g0, %0, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_set_neg" (define_insn "*cmp_cc_set_neg"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -7304,8 +7162,7 @@ ...@@ -7304,8 +7162,7 @@
(neg:SI (match_dup 1)))] (neg:SI (match_dup 1)))]
"" ""
"subcc\\t%%g0, %1, %0" "subcc\\t%%g0, %1, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_set_neg" (define_insn "*cmp_ccx_set_neg"
[(set (reg:CCX_NOOV 100) [(set (reg:CCX_NOOV 100)
...@@ -7315,8 +7172,7 @@ ...@@ -7315,8 +7172,7 @@
(neg:DI (match_dup 1)))] (neg:DI (match_dup 1)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"subcc\\t%%g0, %1, %0" "subcc\\t%%g0, %1, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
;; We cannot use the "not" pseudo insn because the Sun assembler ;; We cannot use the "not" pseudo insn because the Sun assembler
;; does not know how to make it work for constants. ;; does not know how to make it work for constants.
...@@ -7334,7 +7190,8 @@ ...@@ -7334,7 +7190,8 @@
# #
fnot1\\t%1, %0" fnot1\\t%1, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fp")
(set_attr "length" "2,1")]) (set_attr "length" "2,*")
(set_attr "fptype" "double")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -7363,7 +7220,7 @@ ...@@ -7363,7 +7220,7 @@
xnor\\t%%g0, %1, %0 xnor\\t%%g0, %1, %0
fnot1\\t%1, %0" fnot1\\t%1, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "one_cmplsi2" (define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -7372,8 +7229,7 @@ ...@@ -7372,8 +7229,7 @@
"@ "@
xnor\\t%%g0, %1, %0 xnor\\t%%g0, %1, %0
fnot1s\\t%1, %0" fnot1s\\t%1, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fp")])
(set_attr "length" "1,1")])
(define_insn "*cmp_cc_not" (define_insn "*cmp_cc_not"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -7381,8 +7237,7 @@ ...@@ -7381,8 +7237,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"xnorcc\\t%%g0, %0, %%g0" "xnorcc\\t%%g0, %0, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_not" (define_insn "*cmp_ccx_not"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -7390,8 +7245,7 @@ ...@@ -7390,8 +7245,7 @@
(const_int 0)))] (const_int 0)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"xnorcc\\t%%g0, %0, %%g0" "xnorcc\\t%%g0, %0, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_set_not" (define_insn "*cmp_cc_set_not"
[(set (reg:CC 100) [(set (reg:CC 100)
...@@ -7401,8 +7255,7 @@ ...@@ -7401,8 +7255,7 @@
(not:SI (match_dup 1)))] (not:SI (match_dup 1)))]
"" ""
"xnorcc\\t%%g0, %1, %0" "xnorcc\\t%%g0, %1, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_ccx_set_not" (define_insn "*cmp_ccx_set_not"
[(set (reg:CCX 100) [(set (reg:CCX 100)
...@@ -7412,8 +7265,7 @@ ...@@ -7412,8 +7265,7 @@
(not:DI (match_dup 1)))] (not:DI (match_dup 1)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"xnorcc\\t%%g0, %1, %0" "xnorcc\\t%%g0, %1, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
;; Floating point arithmetic instructions. ;; Floating point arithmetic instructions.
...@@ -7465,8 +7317,7 @@ ...@@ -7465,8 +7317,7 @@
(match_operand:TF 2 "register_operand" "e")))] (match_operand:TF 2 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"faddq\\t%1, %2, %0" "faddq\\t%1, %2, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_insn "adddf3" (define_insn "adddf3"
[(set (match_operand:DF 0 "register_operand" "=e") [(set (match_operand:DF 0 "register_operand" "=e")
...@@ -7475,7 +7326,7 @@ ...@@ -7475,7 +7326,7 @@
"TARGET_FPU" "TARGET_FPU"
"faddd\\t%1, %2, %0" "faddd\\t%1, %2, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "addsf3" (define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
...@@ -7483,8 +7334,7 @@ ...@@ -7483,8 +7334,7 @@
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU" "TARGET_FPU"
"fadds\\t%1, %2, %0" "fadds\\t%1, %2, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_expand "subtf3" (define_expand "subtf3"
[(set (match_operand:TF 0 "nonimmediate_operand" "") [(set (match_operand:TF 0 "nonimmediate_operand" "")
...@@ -7534,8 +7384,7 @@ ...@@ -7534,8 +7384,7 @@
(match_operand:TF 2 "register_operand" "e")))] (match_operand:TF 2 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fsubq\\t%1, %2, %0" "fsubq\\t%1, %2, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_insn "subdf3" (define_insn "subdf3"
[(set (match_operand:DF 0 "register_operand" "=e") [(set (match_operand:DF 0 "register_operand" "=e")
...@@ -7544,7 +7393,7 @@ ...@@ -7544,7 +7393,7 @@
"TARGET_FPU" "TARGET_FPU"
"fsubd\\t%1, %2, %0" "fsubd\\t%1, %2, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "subsf3" (define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
...@@ -7552,8 +7401,7 @@ ...@@ -7552,8 +7401,7 @@
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU" "TARGET_FPU"
"fsubs\\t%1, %2, %0" "fsubs\\t%1, %2, %0"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "1")])
(define_expand "multf3" (define_expand "multf3"
[(set (match_operand:TF 0 "nonimmediate_operand" "") [(set (match_operand:TF 0 "nonimmediate_operand" "")
...@@ -7603,8 +7451,7 @@ ...@@ -7603,8 +7451,7 @@
(match_operand:TF 2 "register_operand" "e")))] (match_operand:TF 2 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fmulq\\t%1, %2, %0" "fmulq\\t%1, %2, %0"
[(set_attr "type" "fpmul") [(set_attr "type" "fpmul")])
(set_attr "length" "1")])
(define_insn "muldf3" (define_insn "muldf3"
[(set (match_operand:DF 0 "register_operand" "=e") [(set (match_operand:DF 0 "register_operand" "=e")
...@@ -7613,7 +7460,7 @@ ...@@ -7613,7 +7460,7 @@
"TARGET_FPU" "TARGET_FPU"
"fmuld\\t%1, %2, %0" "fmuld\\t%1, %2, %0"
[(set_attr "type" "fpmul") [(set_attr "type" "fpmul")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "mulsf3" (define_insn "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
...@@ -7621,8 +7468,7 @@ ...@@ -7621,8 +7468,7 @@
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU" "TARGET_FPU"
"fmuls\\t%1, %2, %0" "fmuls\\t%1, %2, %0"
[(set_attr "type" "fpmul") [(set_attr "type" "fpmul")])
(set_attr "length" "1")])
(define_insn "*muldf3_extend" (define_insn "*muldf3_extend"
[(set (match_operand:DF 0 "register_operand" "=e") [(set (match_operand:DF 0 "register_operand" "=e")
...@@ -7631,7 +7477,7 @@ ...@@ -7631,7 +7477,7 @@
"(TARGET_V8 || TARGET_V9) && TARGET_FPU" "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
"fsmuld\\t%1, %2, %0" "fsmuld\\t%1, %2, %0"
[(set_attr "type" "fpmul") [(set_attr "type" "fpmul")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "*multf3_extend" (define_insn "*multf3_extend"
[(set (match_operand:TF 0 "register_operand" "=e") [(set (match_operand:TF 0 "register_operand" "=e")
...@@ -7639,8 +7485,7 @@ ...@@ -7639,8 +7485,7 @@
(float_extend:TF (match_operand:DF 2 "register_operand" "e"))))] (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
"(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD" "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
"fdmulq\\t%1, %2, %0" "fdmulq\\t%1, %2, %0"
[(set_attr "type" "fpmul") [(set_attr "type" "fpmul")])
(set_attr "length" "1")])
(define_expand "divtf3" (define_expand "divtf3"
[(set (match_operand:TF 0 "nonimmediate_operand" "") [(set (match_operand:TF 0 "nonimmediate_operand" "")
...@@ -7691,8 +7536,7 @@ ...@@ -7691,8 +7536,7 @@
(match_operand:TF 2 "register_operand" "e")))] (match_operand:TF 2 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fdivq\\t%1, %2, %0" "fdivq\\t%1, %2, %0"
[(set_attr "type" "fpdivd") [(set_attr "type" "fpdivd")])
(set_attr "length" "1")])
(define_insn "divdf3" (define_insn "divdf3"
[(set (match_operand:DF 0 "register_operand" "=e") [(set (match_operand:DF 0 "register_operand" "=e")
...@@ -7701,7 +7545,7 @@ ...@@ -7701,7 +7545,7 @@
"TARGET_FPU" "TARGET_FPU"
"fdivd\\t%1, %2, %0" "fdivd\\t%1, %2, %0"
[(set_attr "type" "fpdivd") [(set_attr "type" "fpdivd")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "divsf3" (define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
...@@ -7709,8 +7553,7 @@ ...@@ -7709,8 +7553,7 @@
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU" "TARGET_FPU"
"fdivs\\t%1, %2, %0" "fdivs\\t%1, %2, %0"
[(set_attr "type" "fpdivs") [(set_attr "type" "fpdivs")])
(set_attr "length" "1")])
(define_expand "negtf2" (define_expand "negtf2"
[(set (match_operand:TF 0 "register_operand" "=e,e") [(set (match_operand:TF 0 "register_operand" "=e,e")
...@@ -7727,8 +7570,8 @@ ...@@ -7727,8 +7570,8 @@
"@ "@
fnegs\\t%0, %0 fnegs\\t%0, %0
#" #"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove,*")
(set_attr "length" "1,2")]) (set_attr "length" "*,2")])
(define_split (define_split
[(set (match_operand:TF 0 "register_operand" "") [(set (match_operand:TF 0 "register_operand" "")
...@@ -7759,8 +7602,9 @@ ...@@ -7759,8 +7602,9 @@
"@ "@
fnegd\\t%0, %0 fnegd\\t%0, %0
#" #"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove,*")
(set_attr "length" "1,2")]) (set_attr "length" "*,2")
(set_attr "fptype" "double")])
(define_split (define_split
[(set (match_operand:TF 0 "register_operand" "") [(set (match_operand:TF 0 "register_operand" "")
...@@ -7793,8 +7637,8 @@ ...@@ -7793,8 +7637,8 @@
"@ "@
fnegs\\t%0, %0 fnegs\\t%0, %0
#" #"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove,*")
(set_attr "length" "1,2")]) (set_attr "length" "*,2")])
(define_split (define_split
[(set (match_operand:DF 0 "register_operand" "") [(set (match_operand:DF 0 "register_operand" "")
...@@ -7820,15 +7664,14 @@ ...@@ -7820,15 +7664,14 @@
"TARGET_FPU && TARGET_V9" "TARGET_FPU && TARGET_V9"
"fnegd\\t%1, %0" "fnegd\\t%1, %0"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "negsf2" (define_insn "negsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (match_operand:SF 1 "register_operand" "f")))] (neg:SF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU" "TARGET_FPU"
"fnegs\\t%1, %0" "fnegs\\t%1, %0"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove")])
(set_attr "length" "1")])
(define_expand "abstf2" (define_expand "abstf2"
[(set (match_operand:TF 0 "register_operand" "") [(set (match_operand:TF 0 "register_operand" "")
...@@ -7844,8 +7687,8 @@ ...@@ -7844,8 +7687,8 @@
"@ "@
fabss\\t%0, %0 fabss\\t%0, %0
#" #"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove,*")
(set_attr "length" "1,2")]) (set_attr "length" "*,2")])
(define_split (define_split
[(set (match_operand:TF 0 "register_operand" "") [(set (match_operand:TF 0 "register_operand" "")
...@@ -7876,7 +7719,7 @@ ...@@ -7876,7 +7719,7 @@
fabsd\\t%0, %0 fabsd\\t%0, %0
fabsq\\t%1, %0" fabsq\\t%1, %0"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove")
(set_attr "length" "1")]) (set_attr "fptype" "double,*")])
(define_insn "*abstf2_v9" (define_insn "*abstf2_v9"
[(set (match_operand:TF 0 "register_operand" "=e,e") [(set (match_operand:TF 0 "register_operand" "=e,e")
...@@ -7885,8 +7728,9 @@ ...@@ -7885,8 +7728,9 @@
"@ "@
fabsd\\t%0, %0 fabsd\\t%0, %0
#" #"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove,*")
(set_attr "length" "1,2")]) (set_attr "length" "*,2")
(set_attr "fptype" "double,*")])
(define_split (define_split
[(set (match_operand:TF 0 "register_operand" "") [(set (match_operand:TF 0 "register_operand" "")
...@@ -7919,8 +7763,8 @@ ...@@ -7919,8 +7763,8 @@
"@ "@
fabss\\t%0, %0 fabss\\t%0, %0
#" #"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove,*")
(set_attr "length" "1,2")]) (set_attr "length" "*,2")])
(define_split (define_split
[(set (match_operand:DF 0 "register_operand" "") [(set (match_operand:DF 0 "register_operand" "")
...@@ -7946,15 +7790,14 @@ ...@@ -7946,15 +7790,14 @@
"TARGET_FPU && TARGET_V9" "TARGET_FPU && TARGET_V9"
"fabsd\\t%1, %0" "fabsd\\t%1, %0"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "abssf2" (define_insn "abssf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(abs:SF (match_operand:SF 1 "register_operand" "f")))] (abs:SF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU" "TARGET_FPU"
"fabss\\t%1, %0" "fabss\\t%1, %0"
[(set_attr "type" "fpmove") [(set_attr "type" "fpmove")])
(set_attr "length" "1")])
(define_expand "sqrttf2" (define_expand "sqrttf2"
[(set (match_operand:TF 0 "register_operand" "=e") [(set (match_operand:TF 0 "register_operand" "=e")
...@@ -7994,8 +7837,7 @@ ...@@ -7994,8 +7837,7 @@
(sqrt:TF (match_operand:TF 1 "register_operand" "e")))] (sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD" "TARGET_FPU && TARGET_HARD_QUAD"
"fsqrtq\\t%1, %0" "fsqrtq\\t%1, %0"
[(set_attr "type" "fpsqrtd") [(set_attr "type" "fpsqrtd")])
(set_attr "length" "1")])
(define_insn "sqrtdf2" (define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=e") [(set (match_operand:DF 0 "register_operand" "=e")
...@@ -8003,15 +7845,14 @@ ...@@ -8003,15 +7845,14 @@
"TARGET_FPU" "TARGET_FPU"
"fsqrtd\\t%1, %0" "fsqrtd\\t%1, %0"
[(set_attr "type" "fpsqrtd") [(set_attr "type" "fpsqrtd")
(set_attr "length" "1")]) (set_attr "fptype" "double")])
(define_insn "sqrtsf2" (define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "f")))] (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU" "TARGET_FPU"
"fsqrts\\t%1, %0" "fsqrts\\t%1, %0"
[(set_attr "type" "fpsqrts") [(set_attr "type" "fpsqrts")])
(set_attr "length" "1")])
;;- arithmetic shift instructions ;;- arithmetic shift instructions
...@@ -8028,8 +7869,7 @@ ...@@ -8028,8 +7869,7 @@
return \"sll\\t%1, %2, %0\"; return \"sll\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
;; We special case multiplication by two, as add can be done ;; We special case multiplication by two, as add can be done
;; in both ALUs, while shift only in IEU0 on UltraSPARC. ;; in both ALUs, while shift only in IEU0 on UltraSPARC.
...@@ -8038,8 +7878,7 @@ ...@@ -8038,8 +7878,7 @@
(ashift:SI (match_operand:SI 1 "register_operand" "r") (ashift:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)))] (const_int 1)))]
"" ""
"add\\t%1, %1, %0" "add\\t%1, %1, %0")
[(set_attr "length" "1")])
(define_expand "ashldi3" (define_expand "ashldi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -8064,8 +7903,7 @@ ...@@ -8064,8 +7903,7 @@
(ashift:DI (match_operand:DI 1 "register_operand" "r") (ashift:DI (match_operand:DI 1 "register_operand" "r")
(const_int 1)))] (const_int 1)))]
"TARGET_ARCH64" "TARGET_ARCH64"
"add\\t%1, %1, %0" "add\\t%1, %1, %0")
[(set_attr "length" "1")])
(define_insn "*ashldi3_sp64" (define_insn "*ashldi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -8080,8 +7918,7 @@ ...@@ -8080,8 +7918,7 @@
return \"sllx\\t%1, %2, %0\"; return \"sllx\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
;; XXX UGH! ;; XXX UGH!
(define_insn "ashldi3_v8plus" (define_insn "ashldi3_v8plus"
...@@ -8091,7 +7928,8 @@ ...@@ -8091,7 +7928,8 @@
(clobber (match_scratch:SI 3 "=X,X,&h"))] (clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS" "TARGET_V8PLUS"
"*return sparc_v8plus_shift (operands, insn, \"sllx\");" "*return sparc_v8plus_shift (operands, insn, \"sllx\");"
[(set_attr "length" "5,5,6")]) [(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
;; Optimize (1LL<<x)-1 ;; Optimize (1LL<<x)-1
;; XXX this also needs to be fixed to handle equal subregs ;; XXX this also needs to be fixed to handle equal subregs
...@@ -8108,7 +7946,8 @@ ...@@ -8108,7 +7946,8 @@
; return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\"; ; return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
; return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\"; ; return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
;}" ;}"
; [(set_attr "length" "4")]) ; [(set_attr "type" "multi")
; (set_attr "length" "4")])
(define_insn "*cmp_cc_ashift_1" (define_insn "*cmp_cc_ashift_1"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -8117,8 +7956,7 @@ ...@@ -8117,8 +7956,7 @@
(const_int 0)))] (const_int 0)))]
"" ""
"addcc\\t%0, %0, %%g0" "addcc\\t%0, %0, %%g0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "*cmp_cc_set_ashift_1" (define_insn "*cmp_cc_set_ashift_1"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -8129,8 +7967,7 @@ ...@@ -8129,8 +7967,7 @@
(ashift:SI (match_dup 1) (const_int 1)))] (ashift:SI (match_dup 1) (const_int 1)))]
"" ""
"addcc\\t%1, %1, %0" "addcc\\t%1, %1, %0"
[(set_attr "type" "compare") [(set_attr "type" "compare")])
(set_attr "length" "1")])
(define_insn "ashrsi3" (define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -8145,8 +7982,7 @@ ...@@ -8145,8 +7982,7 @@
return \"sra\\t%1, %2, %0\"; return \"sra\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
(define_insn "*ashrsi3_extend" (define_insn "*ashrsi3_extend"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -8154,8 +7990,7 @@ ...@@ -8154,8 +7990,7 @@
(match_operand:SI 2 "arith_operand" "r"))))] (match_operand:SI 2 "arith_operand" "r"))))]
"TARGET_ARCH64" "TARGET_ARCH64"
"sra\\t%1, %2, %0" "sra\\t%1, %2, %0"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
;; This handles the case as above, but with constant shift instead of ;; This handles the case as above, but with constant shift instead of
;; register. Combiner "simplifies" it for us a little bit though. ;; register. Combiner "simplifies" it for us a little bit though.
...@@ -8177,8 +8012,7 @@ ...@@ -8177,8 +8012,7 @@
return \"sra\\t%1, %2, %0\"; return \"sra\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
(define_expand "ashrdi3" (define_expand "ashrdi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -8209,8 +8043,7 @@ ...@@ -8209,8 +8043,7 @@
return \"srax\\t%1, %2, %0\"; return \"srax\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
;; XXX ;; XXX
(define_insn "ashrdi3_v8plus" (define_insn "ashrdi3_v8plus"
...@@ -8220,7 +8053,8 @@ ...@@ -8220,7 +8053,8 @@
(clobber (match_scratch:SI 3 "=X,X,&h"))] (clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS" "TARGET_V8PLUS"
"*return sparc_v8plus_shift (operands, insn, \"srax\");" "*return sparc_v8plus_shift (operands, insn, \"srax\");"
[(set_attr "length" "5,5,6")]) [(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
(define_insn "lshrsi3" (define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -8235,8 +8069,7 @@ ...@@ -8235,8 +8069,7 @@
return \"srl\\t%1, %2, %0\"; return \"srl\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
;; This handles the case where ;; This handles the case where
;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))), ;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
...@@ -8254,8 +8087,7 @@ ...@@ -8254,8 +8087,7 @@
&& GET_CODE (operands[3]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))" && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))"
"srl\\t%1, %2, %0" "srl\\t%1, %2, %0"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
;; This handles the case where ;; This handles the case where
;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32)) ;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
...@@ -8277,8 +8109,7 @@ ...@@ -8277,8 +8109,7 @@
return \"srl\\t%1, %2, %0\"; return \"srl\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
(define_expand "lshrdi3" (define_expand "lshrdi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -8309,8 +8140,7 @@ ...@@ -8309,8 +8140,7 @@
return \"srlx\\t%1, %2, %0\"; return \"srlx\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
;; XXX ;; XXX
(define_insn "lshrdi3_v8plus" (define_insn "lshrdi3_v8plus"
...@@ -8320,7 +8150,8 @@ ...@@ -8320,7 +8150,8 @@
(clobber (match_scratch:SI 3 "=X,X,&h"))] (clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS" "TARGET_V8PLUS"
"*return sparc_v8plus_shift (operands, insn, \"srlx\");" "*return sparc_v8plus_shift (operands, insn, \"srlx\");"
[(set_attr "length" "5,5,6")]) [(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -8339,8 +8170,7 @@ ...@@ -8339,8 +8170,7 @@
return \"srax\\t%1, %2, %0\"; return \"srax\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -8359,8 +8189,7 @@ ...@@ -8359,8 +8189,7 @@
return \"srlx\\t%1, %2, %0\"; return \"srlx\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -8378,8 +8207,7 @@ ...@@ -8378,8 +8207,7 @@
return \"srax\\t%1, %2, %0\"; return \"srax\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -8397,8 +8225,7 @@ ...@@ -8397,8 +8225,7 @@
return \"srlx\\t%1, %2, %0\"; return \"srlx\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift") [(set_attr "type" "shift")])
(set_attr "length" "1")])
;; Unconditional and other jump instructions ;; Unconditional and other jump instructions
;; On the Sparc, by setting the annul bit on an unconditional branch, the ;; On the Sparc, by setting the annul bit on an unconditional branch, the
...@@ -8862,7 +8689,8 @@ ...@@ -8862,7 +8689,8 @@
(match_operand:SI 1 "register_operand" "r")] 1)] (match_operand:SI 1 "register_operand" "r")] 1)]
"! TARGET_ARCH64" "! TARGET_ARCH64"
"cmp\\t%1, 0\;be,a\\t.+8\;add\\t%0, 4, %0" "cmp\\t%1, 0\;be,a\\t.+8\;add\\t%0, 4, %0"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "3")])
(define_insn "return" (define_insn "return"
[(return) [(return)
...@@ -8882,9 +8710,7 @@ ...@@ -8882,9 +8710,7 @@
(define_insn "nop" (define_insn "nop"
[(const_int 0)] [(const_int 0)]
"" ""
"nop" "nop")
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_expand "indirect_jump" (define_expand "indirect_jump"
[(set (pc) (match_operand 0 "address_operand" "p"))] [(set (pc) (match_operand 0 "address_operand" "p"))]
...@@ -8971,14 +8797,13 @@ ...@@ -8971,14 +8797,13 @@
[(unspec_volatile [(const_int 0)] 1)] [(unspec_volatile [(const_int 0)] 1)]
"" ""
"* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";" "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "goto_handler_and_restore" (define_insn "goto_handler_and_restore"
[(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)] [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)]
"GET_MODE (operands[0]) == Pmode" "GET_MODE (operands[0]) == Pmode"
"jmp\\t%0+0\\n\\trestore" "jmp\\t%0+0\\n\\trestore"
[(set_attr "type" "misc") [(set_attr "type" "multi")
(set_attr "length" "2")]) (set_attr "length" "2")])
;;(define_insn "goto_handler_and_restore_v9" ;;(define_insn "goto_handler_and_restore_v9"
...@@ -8989,7 +8814,7 @@ ...@@ -8989,7 +8814,7 @@
;; "@ ;; "@
;; return\\t%0+0\\n\\tmov\\t%2, %Y1 ;; return\\t%0+0\\n\\tmov\\t%2, %Y1
;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" ;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
;; [(set_attr "type" "misc") ;; [(set_attr "type" "multi")
;; (set_attr "length" "2,3")]) ;; (set_attr "length" "2,3")])
;; ;;
;;(define_insn "*goto_handler_and_restore_v9_sp64" ;;(define_insn "*goto_handler_and_restore_v9_sp64"
...@@ -9000,7 +8825,7 @@ ...@@ -9000,7 +8825,7 @@
;; "@ ;; "@
;; return\\t%0+0\\n\\tmov\\t%2, %Y1 ;; return\\t%0+0\\n\\tmov\\t%2, %Y1
;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" ;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
;; [(set_attr "type" "misc") ;; [(set_attr "type" "multi")
;; (set_attr "length" "2,3")]) ;; (set_attr "length" "2,3")])
;; For __builtin_setjmp we need to flush register windows iff the function ;; For __builtin_setjmp we need to flush register windows iff the function
...@@ -9015,6 +8840,10 @@ ...@@ -9015,6 +8840,10 @@
DONE; DONE;
}") }")
;; ??? Should set length to zero when !current_function_calls_alloca,
;; ??? but there is no easy way to get at that definition. It would
;; ??? require including function.h into sparc-protos.h and that is
;; ??? likely not a good idea. -DaveM
(define_insn "do_builtin_setjmp_setup" (define_insn "do_builtin_setjmp_setup"
[(unspec_volatile [(const_int 0)] 5)] [(unspec_volatile [(const_int 0)] 5)]
"" ""
...@@ -9026,8 +8855,7 @@ ...@@ -9026,8 +8855,7 @@
return \"flushw\"; return \"flushw\";
return \"ta\\t3\"; return \"ta\\t3\";
}" }"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
;; Pattern for use after a setjmp to store FP and the return register ;; Pattern for use after a setjmp to store FP and the return register
;; into the stack area. ;; into the stack area.
...@@ -9278,7 +9106,8 @@ ...@@ -9278,7 +9106,8 @@
else else
return \"ret\\n\\trestore %%g0, %1, %Y0\"; return \"ret\\n\\trestore %%g0, %1, %Y0\";
}" }"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_hi" (define_insn "*return_hi"
[(set (match_operand:HI 0 "restore_operand" "") [(set (match_operand:HI 0 "restore_operand" "")
...@@ -9295,7 +9124,8 @@ ...@@ -9295,7 +9124,8 @@
else else
return \"ret\;restore %%g0, %1, %Y0\"; return \"ret\;restore %%g0, %1, %Y0\";
}" }"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_si" (define_insn "*return_si"
[(set (match_operand:SI 0 "restore_operand" "") [(set (match_operand:SI 0 "restore_operand" "")
...@@ -9312,7 +9142,8 @@ ...@@ -9312,7 +9142,8 @@
else else
return \"ret\;restore %%g0, %1, %Y0\"; return \"ret\;restore %%g0, %1, %Y0\";
}" }"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; The following pattern is only generated by delayed-branch scheduling, ;; The following pattern is only generated by delayed-branch scheduling,
;; when the insn winds up in the epilogue. This can happen not only when ;; when the insn winds up in the epilogue. This can happen not only when
...@@ -9332,7 +9163,8 @@ ...@@ -9332,7 +9163,8 @@
else else
return \"ret\;restore %%g0, %1, %Y0\"; return \"ret\;restore %%g0, %1, %Y0\";
}" }"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_df_no_fpu" (define_insn "*return_df_no_fpu"
[(set (match_operand:DF 0 "restore_operand" "=r") [(set (match_operand:DF 0 "restore_operand" "=r")
...@@ -9346,7 +9178,8 @@ ...@@ -9346,7 +9178,8 @@
else else
return \"ret\;restore %%g0, %1, %Y0\"; return \"ret\;restore %%g0, %1, %Y0\";
}" }"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_addsi" (define_insn "*return_addsi"
[(set (match_operand:SI 0 "restore_operand" "") [(set (match_operand:SI 0 "restore_operand" "")
...@@ -9366,7 +9199,8 @@ ...@@ -9366,7 +9199,8 @@
else else
return \"ret\;restore %r1, %2, %Y0\"; return \"ret\;restore %r1, %2, %Y0\";
}" }"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_losum_si" (define_insn "*return_losum_si"
[(set (match_operand:SI 0 "restore_operand" "") [(set (match_operand:SI 0 "restore_operand" "")
...@@ -9384,7 +9218,8 @@ ...@@ -9384,7 +9218,8 @@
else else
return \"ret\;restore %r1, %%lo(%a2), %Y0\"; return \"ret\;restore %r1, %%lo(%a2), %Y0\";
}" }"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_di" (define_insn "*return_di"
[(set (match_operand:DI 0 "restore_operand" "") [(set (match_operand:DI 0 "restore_operand" "")
...@@ -9392,7 +9227,8 @@ ...@@ -9392,7 +9227,8 @@
(return)] (return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE" "TARGET_ARCH64 && ! TARGET_EPILOGUE"
"ret\;restore %%g0, %1, %Y0" "ret\;restore %%g0, %1, %Y0"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_adddi" (define_insn "*return_adddi"
[(set (match_operand:DI 0 "restore_operand" "") [(set (match_operand:DI 0 "restore_operand" "")
...@@ -9401,7 +9237,8 @@ ...@@ -9401,7 +9237,8 @@
(return)] (return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE" "TARGET_ARCH64 && ! TARGET_EPILOGUE"
"ret\;restore %r1, %2, %Y0" "ret\;restore %r1, %2, %Y0"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_losum_di" (define_insn "*return_losum_di"
[(set (match_operand:DI 0 "restore_operand" "") [(set (match_operand:DI 0 "restore_operand" "")
...@@ -9410,7 +9247,8 @@ ...@@ -9410,7 +9247,8 @@
(return)] (return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID" "TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
"ret\;restore %r1, %%lo(%a2), %Y0" "ret\;restore %r1, %%lo(%a2), %Y0"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; The following pattern is only generated by delayed-branch scheduling, ;; The following pattern is only generated by delayed-branch scheduling,
;; when the insn winds up in the epilogue. ;; when the insn winds up in the epilogue.
...@@ -9420,7 +9258,8 @@ ...@@ -9420,7 +9258,8 @@
(return)] (return)]
"! TARGET_EPILOGUE" "! TARGET_EPILOGUE"
"ret\;fmovs\\t%0, %%f0" "ret\;fmovs\\t%0, %%f0"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")
(set_attr "length" "2")])
;; Now peepholes to do a call followed by a jump. ;; Now peepholes to do a call followed by a jump.
...@@ -9499,8 +9338,7 @@ ...@@ -9499,8 +9338,7 @@
[(trap_if (const_int 1) (const_int 5))] [(trap_if (const_int 1) (const_int 5))]
"" ""
"ta\\t5" "ta\\t5"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_expand "conditional_trap" (define_expand "conditional_trap"
[(trap_if (match_operator 0 "noov_compare_op" [(trap_if (match_operator 0 "noov_compare_op"
...@@ -9516,13 +9354,11 @@ ...@@ -9516,13 +9354,11 @@
(match_operand:SI 1 "arith_operand" "rM"))] (match_operand:SI 1 "arith_operand" "rM"))]
"" ""
"t%C0\\t%1" "t%C0\\t%1"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
(define_insn "" (define_insn ""
[(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)]) [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
(match_operand:SI 1 "arith_operand" "rM"))] (match_operand:SI 1 "arith_operand" "rM"))]
"TARGET_V9" "TARGET_V9"
"t%C0\\t%%xcc, %1" "t%C0\\t%%xcc, %1"
[(set_attr "type" "misc") [(set_attr "type" "misc")])
(set_attr "length" "1")])
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