re PR rtl-optimization/60851 (ICE: in extract_constrain_insn_cached, at…

re PR rtl-optimization/60851 (ICE: in extract_constrain_insn_cached, at recog.c:2117 with -flive-range-shrinkage -mdispatch-scheduler -march=bdver4)

	PR rtl-optimization/60851
	* recog.c (constrain_operands): Accept a pseudo register before reload
	for LRA enabled targets.

testsuite/ChangeLog:

	PR rtl-optimization/60851
	* gcc.target/i386/pr60851.c: New test.

From-SVN: r221529

gcc/ChangeLog

+2015-03-20  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR rtl-optimization/60851
+	* recog.c (constrain_operands): Accept a pseudo register before reload
+	for LRA enabled targets.
+
 2015-03-19  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	PR target/65240

gcc/recog.c

@@ -2773,8 +2773,12 @@ constrain_operands (int strict, alternative_mask alternatives)
 			   /* Every memory operand can be reloaded to fit.  */
 			   && ((strict < 0 && MEM_P (op))
 			       /* Before reload, accept what reload can turn
-				  into mem.  */
+				  into a mem.  */
 			       || (strict < 0 && CONSTANT_P (op))
+			       /* Before reload, accept a pseudo,
+				  since LRA can turn it into a mem.  */
+			       || (strict < 0 && targetm.lra_p () && REG_P (op)
+				   && REGNO (op) >= FIRST_PSEUDO_REGISTER)
 			       /* During reload, accept a pseudo  */
 			       || (reload_in_progress && REG_P (op)
 				   && REGNO (op) >= FIRST_PSEUDO_REGISTER)))

gcc/testsuite/ChangeLog

-2015-03-17  Michael Meissner  <meissner@linux.vnet.ibm.com>
+2015-03-20  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR rtl-optimization/60851
+	* gcc.target/i386/pr60851.c: New test.
+
+2015-03-19  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	PR target/65240
 	* gcc/testsuite/g++.dg/pr65240.h: Add tests for PR 65240.

gcc/testsuite/gcc.target/i386/pr60851.c

+/* { dg-do compile } */
+/* { dg-options "-O2 -flive-range-shrinkage -mtune=bdver4 -mdispatch-scheduler" } */
+
+long double ld (char c)
+{
+  return c;
+}