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riscv-gcc-1
Commit 1e24ce83 by David Edelsohn
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rs6000.md (ltu<mode>_compare): Convert to define_insn_and_split. 

	* config/rs6000/rs6000.md (ltu<mode>_compare): Convert to
	define_insn_and_split.
	(plus_ltu<mode>_compare): Same.
	(gtu<mode>_compare): Same.
	(plus_gtu<mode>_compare): Same.

From-SVN: r103253
parent 90ff949f
Showing with 53 additions and 243 deletions
gcc/ChangeLog
2005-08-18 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.md (ltu<mode>_compare): Convert to
define_insn_and_split.
(plus_ltu<mode>_compare): Same.
(gtu<mode>_compare): Same.
(plus_gtu<mode>_compare): Same.
2005-08-18 Dorit Nuzman <dorit@il.ibm.com> 2005-08-18 Dorit Nuzman <dorit@il.ibm.com>
PR tree-optimization/22228 PR tree-optimization/22228
* tree-ssa-loop (pass_vectorize): Add TODO_verify_loops to todo_flags_start. * tree-ssa-loop (pass_vectorize): Add TODO_verify_loops to
todo_flags_start.
* tree-vect-transform.c (vect_transform_loop): Mark the variables that * tree-vect-transform.c (vect_transform_loop): Mark the variables that
are recorded in vect_vnames_to_rename for renaming. are recorded in vect_vnames_to_rename for renaming.
* tree-vectorizer.c (vect_vnames_to_rename): New global bitmap. * tree-vectorizer.c (vect_vnames_to_rename): New global bitmap.
......
gcc/config/rs6000/rs6000.md
...@@ -11995,7 +11995,7 @@ ...@@ -11995,7 +11995,7 @@
(set (match_dup 0) (neg:P (match_dup 0)))] (set (match_dup 0) (neg:P (match_dup 0)))]
"") "")
(define_insn "*ltu<mode>_compare" (define_insn_and_split "*ltu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (compare:CC
(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
...@@ -12004,28 +12004,12 @@ ...@@ -12004,28 +12004,12 @@
(set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
(ltu:P (match_dup 1) (match_dup 2)))] (ltu:P (match_dup 1) (match_dup 2)))]
"" ""
"@ "#"
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 ""
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
# (parallel [(set (match_dup 3)
#" (compare:CC (neg:P (match_dup 0)) (const_int 0)))
[(set_attr "type" "compare") (set (match_dup 0) (neg:P (match_dup 0)))])]
(set_attr "length" "12,12,16,16")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
(ltu:P (match_operand:P 1 "gpc_reg_operand" "")
(match_operand:P 2 "reg_or_neg_short_operand" ""))
(const_int 0)))
(set (match_operand:P 0 "gpc_reg_operand" "")
(ltu:P (match_dup 1) (match_dup 2)))]
"reload_completed"
[(set (match_dup 0)
(ltu:P (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"") "")
(define_insn_and_split "*plus_ltu<mode>" (define_insn_and_split "*plus_ltu<mode>"
...@@ -12040,73 +12024,23 @@ ...@@ -12040,73 +12024,23 @@
(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
"") "")
(define_insn "" (define_insn_and_split "*plus_ltu<mode>_compare"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"TARGET_32BIT"
"@
{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
#
#"
[(set_attr "type" "compare")
(set_attr "length" "12,12,16,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC
(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_neg_short_operand" ""))
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(plus:SI (ltu:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
(set (match_dup 0)
(compare:CC (match_dup 4)
(const_int 0)))]
"")
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (compare:CC
(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_32BIT" ""
"@ "#"
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
# (parallel [(set (match_dup 4)
#" (compare:CC (minus:P (match_dup 3) (match_dup 0))
[(set_attr "type" "compare")
(set_attr "length" "12,12,16,16")])
(define_split
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
(compare:CC
(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_neg_short_operand" ""))
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "") (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"") "")
(define_insn "*neg_ltu<mode>" (define_insn "*neg_ltu<mode>"
...@@ -12799,7 +12733,7 @@ ...@@ -12799,7 +12733,7 @@
(const_int 0)))] (const_int 0)))]
"") "")
(define_insn "" (define_insn "*neg_gt0si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))))] (const_int 0))))]
...@@ -12808,7 +12742,7 @@ ...@@ -12808,7 +12742,7 @@
[(set_attr "type" "three") [(set_attr "type" "three")
(set_attr "length" "12")]) (set_attr "length" "12")])
(define_insn "" (define_insn "neg_gt0di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 0))))] (const_int 0))))]
...@@ -12836,7 +12770,7 @@ ...@@ -12836,7 +12770,7 @@
(set (match_dup 0) (neg:P (match_dup 0)))] (set (match_dup 0) (neg:P (match_dup 0)))]
"") "")
(define_insn "*gtu<mode>_compare" (define_insn_and_split "*gtu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (compare:CC
(gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r") (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
...@@ -12845,29 +12779,15 @@ ...@@ -12845,29 +12779,15 @@
(set (match_operand:P 0 "gpc_reg_operand" "=r,r") (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(gtu:P (match_dup 1) (match_dup 2)))] (gtu:P (match_dup 1) (match_dup 2)))]
"" ""
"@ "#"
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 ""
#" [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
[(set_attr "type" "compare") (parallel [(set (match_dup 3)
(set_attr "length" "12,16")]) (compare:CC (neg:P (match_dup 0)) (const_int 0)))
(set (match_dup 0) (neg:P (match_dup 0)))])]
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
(gtu:P (match_operand:P 1 "gpc_reg_operand" "")
(match_operand:P 2 "reg_or_short_operand" ""))
(const_int 0)))
(set (match_operand:P 0 "gpc_reg_operand" "")
(gtu:P (match_dup 1) (match_dup 2)))]
"reload_completed"
[(set (match_dup 0)
(gtu:P (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"") "")
(define_insn_and_split "plus_gtu<mode>" (define_insn_and_split "*plus_gtu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=&r") [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
(plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "reg_or_short_operand" "rI")) (match_operand:P 2 "reg_or_short_operand" "rI"))
...@@ -12879,142 +12799,23 @@ ...@@ -12879,142 +12799,23 @@
(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
"") "")
(define_insn "" (define_insn_and_split "*plus_gtu<mode>_compare"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"TARGET_32BIT"
"@
{ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
#
#"
[(set_attr "type" "compare")
(set_attr "length" "8,12,12,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" ""))
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(plus:SI (gtu:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
(set (match_dup 0)
(compare:CC (match_dup 4)
(const_int 0)))]
"")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
(match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
"TARGET_64BIT"
"@
addic %4,%1,%k2\;addze. %4,%3
subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
#
#"
[(set_attr "type" "compare")
(set_attr "length" "8,12,12,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:DI 2 "reg_or_short_operand" ""))
(match_operand:DI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 4 ""))]
"TARGET_64BIT && reload_completed"
[(set (match_dup 4)
(plus:DI (gtu:DI (match_dup 1) (match_dup 2))
(match_dup 3)))
(set (match_dup 0)
(compare:CC (match_dup 4)
(const_int 0)))]
"")
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (compare:CC
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_32BIT" ""
"@ "#"
{ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
# (parallel [(set (match_dup 4)
#" (compare:CC (minus:P (match_dup 3) (match_dup 0))
[(set_attr "type" "compare")
(set_attr "length" "8,12,12,16")])
(define_split
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
(compare:CC
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" ""))
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
(match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_64BIT"
"@
addic %0,%1,%k2\;addze. %0,%3
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
#
#"
[(set_attr "type" "compare")
(set_attr "length" "8,12,12,16")])
(define_split
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
(compare:CC
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:DI 2 "reg_or_short_operand" ""))
(match_operand:DI 3 "gpc_reg_operand" ""))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "") (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"") "")
(define_insn "*neg_gtu<mode>" (define_insn "*neg_gtu<mode>"
......
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