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riscv-gcc-1
Commit 1db70317 by Richard Henderson Committed by Richard Henderson
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i386.c (x86_sse_partial_regs_for_cvtsd2ss): Remove. 

        * config/i386/i386.c (x86_sse_partial_regs_for_cvtsd2ss): Remove.
        * config/i386/i386.h (TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS): Remove.
        * config/i386/i386.md (truncdfsf2_1_sse): Don't test it.
        (truncdfsf2_2, truncdfsf2_sse_only): Likewise.
        (truncdfsf2_1_sse_nooverlap, truncdfsf2_2_nooverlap): Remove.
        (truncdfsf2_sse_only_nooverlap): Remove.

From-SVN: r92457
parent 944c6ecc
Showing with 10 additions and 100 deletions
gcc/ChangeLog
2004-12-21 Richard Henderson <rth@redhat.com> 2004-12-21 Richard Henderson <rth@redhat.com>
* config/i386/i386.c (x86_sse_partial_regs_for_cvtsd2ss): Remove.
* config/i386/i386.h (TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS): Remove.
* config/i386/i386.md (truncdfsf2_1_sse): Don't test it.
(truncdfsf2_2, truncdfsf2_sse_only): Likewise.
(truncdfsf2_1_sse_nooverlap, truncdfsf2_2_nooverlap): Remove.
(truncdfsf2_sse_only_nooverlap): Remove.
* config/i386/i386.h (TARGET_SSE_TYPELESS_LOAD0): Remove. * config/i386/i386.h (TARGET_SSE_TYPELESS_LOAD0): Remove.
2004-12-21 Eric Botcazou <ebotcazou@libertysurf.fr> 2004-12-21 Eric Botcazou <ebotcazou@libertysurf.fr>
......
gcc/config/i386/i386.c
...@@ -566,9 +566,6 @@ const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO; ...@@ -566,9 +566,6 @@ const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO;
parts instead of whole registers, so we may maintain just lower part of parts instead of whole registers, so we may maintain just lower part of
scalar values in proper format leaving the upper part undefined. */ scalar values in proper format leaving the upper part undefined. */
const int x86_sse_partial_regs = m_ATHLON_K8; const int x86_sse_partial_regs = m_ATHLON_K8;
/* Athlon optimizes partial-register FPS special case, thus avoiding the
need for extra instructions beforehand */
const int x86_sse_partial_regs_for_cvtsd2ss = 0;
const int x86_sse_typeless_stores = m_ATHLON_K8; const int x86_sse_typeless_stores = m_ATHLON_K8;
const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA; const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
const int x86_use_ffreep = m_ATHLON_K8; const int x86_use_ffreep = m_ATHLON_K8;
......
gcc/config/i386/i386.h
...@@ -287,8 +287,6 @@ extern int x86_prefetch_sse; ...@@ -287,8 +287,6 @@ extern int x86_prefetch_sse;
#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
(x86_sse_partial_reg_dependency & TUNEMASK) (x86_sse_partial_reg_dependency & TUNEMASK)
#define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK) #define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK)
#define TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS \
(x86_sse_partial_regs_for_cvtsd2ss & TUNEMASK)
#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
......
gcc/config/i386/i386.md
...@@ -3696,30 +3696,7 @@ ...@@ -3696,30 +3696,7 @@
(float_truncate:SF (float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f"))) (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))] (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
"TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" "TARGET_80387 && TARGET_SSE2"
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
case 4:
return "#";
default:
abort ();
}
}
[(set_attr "type" "fmov,multi,multi,multi,ssecvt")
(set_attr "mode" "SF,SF,SF,SF,DF")])
(define_insn "*truncdfsf2_1_sse_nooverlap"
[(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
"TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
{ {
switch (which_alternative) switch (which_alternative)
{ {
...@@ -3741,7 +3718,7 @@ ...@@ -3741,7 +3718,7 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m") [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
(float_truncate:SF (float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))] (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
"TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS "TARGET_80387 && TARGET_SSE2
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{ {
switch (which_alternative) switch (which_alternative)
...@@ -3762,29 +3739,6 @@ ...@@ -3762,29 +3739,6 @@
(set_attr "athlon_decode" "vector,double,*") (set_attr "athlon_decode" "vector,double,*")
(set_attr "mode" "SF,SF,SF")]) (set_attr "mode" "SF,SF,SF")])
(define_insn "*truncdfsf2_2_nooverlap"
[(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
"TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
{
case 0:
return "#";
case 1:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
default:
abort ();
}
}
[(set_attr "type" "ssecvt,fmov")
(set_attr "mode" "DF,SF")])
(define_insn "*truncdfsf2_3" (define_insn "*truncdfsf2_3"
[(set (match_operand:SF 0 "memory_operand" "=m") [(set (match_operand:SF 0 "memory_operand" "=m")
(float_truncate:SF (float_truncate:SF
...@@ -3803,21 +3757,12 @@ ...@@ -3803,21 +3757,12 @@
[(set (match_operand:SF 0 "register_operand" "=Y,Y") [(set (match_operand:SF 0 "register_operand" "=Y,Y")
(float_truncate:SF (float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "Y,mY")))] (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
"!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" "!TARGET_80387 && TARGET_SSE2"
"cvtsd2ss\t{%1, %0|%0, %1}" "cvtsd2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "athlon_decode" "vector,double") (set_attr "athlon_decode" "vector,double")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "*truncdfsf2_sse_only_nooverlap"
[(set (match_operand:SF 0 "register_operand" "=&Y")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
"!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
"#"
[(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
(define_split (define_split
[(set (match_operand:SF 0 "memory_operand" "") [(set (match_operand:SF 0 "memory_operand" "")
(float_truncate:SF (float_truncate:SF
...@@ -3827,8 +3772,6 @@ ...@@ -3827,8 +3772,6 @@
[(set (match_dup 0) (float_truncate:SF (match_dup 1)))] [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
"") "")
; Avoid possible reformatting penalty on the destination by first
; zeroing it out
(define_split (define_split
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (float_truncate:SF
...@@ -3839,42 +3782,7 @@ ...@@ -3839,42 +3782,7 @@
&& !STACK_REG_P (operands[1])" && !STACK_REG_P (operands[1])"
[(const_int 0)] [(const_int 0)]
{ {
rtx src, dest;
if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1])); emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
else
{
dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
/* simplify_gen_subreg refuses to widen memory references. */
if (GET_CODE (src) == SUBREG)
alter_subreg (&src);
if (reg_overlap_mentioned_p (operands[0], operands[1]))
abort ();
emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
emit_insn (gen_cvtsd2ss (dest, dest, src));
}
DONE;
})
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_80387 && reload_completed
&& SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
[(const_int 0)]
{
rtx src, dest;
dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
/* simplify_gen_subreg refuses to widen memory references. */
if (GET_CODE (src) == SUBREG)
alter_subreg (&src);
if (reg_overlap_mentioned_p (operands[0], operands[1]))
abort ();
emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
emit_insn (gen_cvtsd2ss (dest, dest, src));
DONE; DONE;
}) })
......
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