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riscv-gcc-1
Commit 1d5d7a21 by Richard Henderson Committed by Richard Henderson
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ia64.md: Use braced strings instead of quoted strings for code blocks. 

        * config/ia64/ia64.md: Use braced strings instead of quoted strings
        for code blocks.  Tidy whitespace.

From-SVN: r53551
parent ae46c4e0
Showing with 206 additions and 273 deletions
gcc/ChangeLog
2002-05-17 Richard Henderson <rth@redhat.com> 2002-05-17 Richard Henderson <rth@redhat.com>
* config/ia64/ia64.md: Use braced strings instead of quoted strings
for code blocks. Tidy whitespace.
2002-05-17 Richard Henderson <rth@redhat.com>
* hooks.c (hook_tree_bool_false): New. * hooks.c (hook_tree_bool_false): New.
* hooks.h: Declare it. * hooks.h: Declare it.
* target-def.h (TARGET_ASM_SELECT_SECTION): New. * target-def.h (TARGET_ASM_SELECT_SECTION): New.
......
gcc/config/ia64/ia64.md
...@@ -99,8 +99,12 @@ ...@@ -99,8 +99,12 @@
;; multiple instructions, patterns which emit 0 instructions, and patterns ;; multiple instructions, patterns which emit 0 instructions, and patterns
;; which emit instruction that can go in any slot (e.g. nop). ;; which emit instruction that can go in any slot (e.g. nop).
(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,nop_i,nop_m,nop_x,lfetch" (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
(const_string "unknown")) fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,
nop_i,nop_m,nop_x,lfetch"
(const_string "unknown"))
;; chk_s has an I and an M form; use type A for convenience. ;; chk_s has an I and an M form; use type A for convenience.
(define_attr "type" "unknown,A,I,M,F,B,L,X,S" (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
...@@ -271,12 +275,11 @@ ...@@ -271,12 +275,11 @@
[(set (match_operand:QI 0 "general_operand" "") [(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))] (match_operand:QI 1 "general_operand" ""))]
"" ""
"
{ {
if (! reload_in_progress && ! reload_completed if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1])) && ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (QImode, operands[1]); operands[1] = force_reg (QImode, operands[1]);
}") })
(define_insn "*movqi_internal" (define_insn "*movqi_internal"
[(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
...@@ -296,12 +299,11 @@ ...@@ -296,12 +299,11 @@
[(set (match_operand:HI 0 "general_operand" "") [(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))] (match_operand:HI 1 "general_operand" ""))]
"" ""
"
{ {
if (! reload_in_progress && ! reload_completed if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1])) && ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (HImode, operands[1]); operands[1] = force_reg (HImode, operands[1]);
}") })
(define_insn "*movhi_internal" (define_insn "*movhi_internal"
[(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
...@@ -321,12 +323,11 @@ ...@@ -321,12 +323,11 @@
[(set (match_operand:SI 0 "general_operand" "") [(set (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))] (match_operand:SI 1 "general_operand" ""))]
"" ""
"
{ {
if (! reload_in_progress && ! reload_completed if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1])) && ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (SImode, operands[1]); operands[1] = force_reg (SImode, operands[1]);
}") })
(define_insn "*movsi_internal" (define_insn "*movsi_internal"
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
...@@ -343,14 +344,13 @@ ...@@ -343,14 +344,13 @@
mov %0 = %1 mov %0 = %1
mov %0 = %1 mov %0 = %1
mov %0 = %r1" mov %0 = %r1"
;; frar_m, toar_m ??? why not frar_i and toar_i ;; frar_m, toar_m ??? why not frar_i and toar_i
[(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
(define_expand "movdi" (define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "") [(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))] (match_operand:DI 1 "general_operand" ""))]
"" ""
"
{ {
if (! reload_in_progress && ! reload_completed if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1])) && ! ia64_move_ok (operands[0], operands[1]))
...@@ -370,12 +370,13 @@ ...@@ -370,12 +370,13 @@
if (rtx_equal_function_value_matters if (rtx_equal_function_value_matters
&& ! (GET_CODE (operands[1]) == SYMBOL_REF && ! (GET_CODE (operands[1]) == SYMBOL_REF
&& SYMBOL_REF_FLAG (operands[1]))) && SYMBOL_REF_FLAG (operands[1])))
emit_insn (gen_movdi_symbolic (operands[0], operands[1], gen_reg_rtx (DImode))); emit_insn (gen_movdi_symbolic (operands[0], operands[1],
gen_reg_rtx (DImode)));
else else
ia64_expand_load_address (operands[0], operands[1], NULL_RTX); ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
DONE; DONE;
} }
}") })
;; This is used during early compilation to delay the decision on ;; This is used during early compilation to delay the decision on
;; how to refer to a variable as long as possible. This is especially ;; how to refer to a variable as long as possible. This is especially
...@@ -395,7 +396,7 @@ ...@@ -395,7 +396,7 @@
"* abort ();" "* abort ();"
"" ""
[(const_int 0)] [(const_int 0)]
"ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;") { ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE; })
(define_insn "*movdi_internal" (define_insn "*movdi_internal"
[(set (match_operand:DI 0 "destination_operand" [(set (match_operand:DI 0 "destination_operand"
...@@ -403,27 +404,26 @@ ...@@ -403,27 +404,26 @@
(match_operand:DI 1 "move_operand" (match_operand:DI 1 "move_operand"
"rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
"ia64_move_ok (operands[0], operands[1])" "ia64_move_ok (operands[0], operands[1])"
"*
{ {
static const char * const alt[] = { static const char * const alt[] = {
\"%,mov %0 = %r1\", "%,mov %0 = %r1",
\"%,addl %0 = %1, r0\", "%,addl %0 = %1, r0",
\"%,movl %0 = %1\", "%,movl %0 = %1",
\"%,ld8%O1 %0 = %1%P1\", "%,ld8%O1 %0 = %1%P1",
\"%,st8%Q0 %0 = %r1%P0\", "%,st8%Q0 %0 = %r1%P0",
\"%,getf.sig %0 = %1\", "%,getf.sig %0 = %1",
\"%,setf.sig %0 = %r1\", "%,setf.sig %0 = %r1",
\"%,mov %0 = %1\", "%,mov %0 = %1",
\"%,ldf8 %0 = %1%P1\", "%,ldf8 %0 = %1%P1",
\"%,stf8 %0 = %1%P0\", "%,stf8 %0 = %1%P0",
\"%,mov %0 = %1\", "%,mov %0 = %1",
\"%,mov %0 = %r1\", "%,mov %0 = %r1",
\"%,mov %0 = %1\", "%,mov %0 = %1",
\"%,mov %0 = %1\", "%,mov %0 = %1",
\"%,mov %0 = %1\", "%,mov %0 = %1",
\"%,mov %0 = %1\", "%,mov %0 = %1",
\"mov %0 = pr\", "mov %0 = pr",
\"mov pr = %1, -1\" "mov pr = %1, -1"
}; };
if (which_alternative == 2 && ! TARGET_NO_PIC if (which_alternative == 2 && ! TARGET_NO_PIC
...@@ -431,7 +431,7 @@ ...@@ -431,7 +431,7 @@
abort (); abort ();
return alt[which_alternative]; return alt[which_alternative];
}" }
[(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
(define_split (define_split
...@@ -439,23 +439,21 @@ ...@@ -439,23 +439,21 @@
(match_operand:DI 1 "symbolic_operand" ""))] (match_operand:DI 1 "symbolic_operand" ""))]
"reload_completed && ! TARGET_NO_PIC" "reload_completed && ! TARGET_NO_PIC"
[(const_int 0)] [(const_int 0)]
"
{ {
ia64_expand_load_address (operands[0], operands[1], NULL_RTX); ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
DONE; DONE;
}") })
(define_expand "load_fptr" (define_expand "load_fptr"
[(set (match_dup 2) [(set (match_dup 2)
(plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" ""))) (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "")))
(set (match_operand:DI 0 "register_operand" "") (match_dup 3))] (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
"" ""
"
{ {
operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
operands[3] = gen_rtx_MEM (DImode, operands[2]); operands[3] = gen_rtx_MEM (DImode, operands[2]);
RTX_UNCHANGING_P (operands[3]) = 1; RTX_UNCHANGING_P (operands[3]) = 1;
}") })
(define_insn "*load_fptr_internal1" (define_insn "*load_fptr_internal1"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -484,23 +482,21 @@ ...@@ -484,23 +482,21 @@
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_dup 3) (match_dup 2)))] (plus:DI (match_dup 3) (match_dup 2)))]
"" ""
"
{ {
operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
operands[3] = pic_offset_table_rtx; operands[3] = pic_offset_table_rtx;
}") })
(define_expand "load_symptr" (define_expand "load_symptr"
[(set (match_operand:DI 2 "register_operand" "") [(set (match_operand:DI 2 "register_operand" "")
(plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" ""))) (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" "")))
(set (match_operand:DI 0 "register_operand" "") (match_dup 3))] (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
"" ""
"
{ {
operands[3] = gen_rtx_MEM (DImode, operands[2]); operands[3] = gen_rtx_MEM (DImode, operands[2]);
operands[4] = pic_offset_table_rtx; operands[4] = pic_offset_table_rtx;
RTX_UNCHANGING_P (operands[3]) = 1; RTX_UNCHANGING_P (operands[3]) = 1;
}") })
(define_insn "*load_symptr_internal1" (define_insn "*load_symptr_internal1"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -516,12 +512,11 @@ ...@@ -516,12 +512,11 @@
(match_operand:TI 1 "general_operand" "")) (match_operand:TI 1 "general_operand" ""))
(clobber (match_scratch:DI 2 ""))])] (clobber (match_scratch:DI 2 ""))])]
"" ""
"
{ {
if (! reload_in_progress && ! reload_completed if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1])) && ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (TImode, operands[1]); operands[1] = force_reg (TImode, operands[1]);
}") })
(define_insn_and_split "*movti_internal" (define_insn_and_split "*movti_internal"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
...@@ -531,7 +526,6 @@ ...@@ -531,7 +526,6 @@
"#" "#"
"reload_completed" "reload_completed"
[(const_int 0)] [(const_int 0)]
"
{ {
rtx adj1, adj2, in[2], out[2], insn; rtx adj1, adj2, in[2], out[2], insn;
int first; int first;
...@@ -566,7 +560,7 @@ ...@@ -566,7 +560,7 @@
XEXP (XEXP (out[!first], 0), 0), XEXP (XEXP (out[!first], 0), 0),
REG_NOTES (insn)); REG_NOTES (insn));
DONE; DONE;
}" }
[(set_attr "itanium_class" "unknown") [(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -580,7 +574,6 @@ ...@@ -580,7 +574,6 @@
"#" "#"
"reload_completed" "reload_completed"
[(const_int 0)] [(const_int 0)]
"
{ {
rtx in[2], out[2]; rtx in[2], out[2];
int first; int first;
...@@ -599,7 +592,7 @@ ...@@ -599,7 +592,7 @@
emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
DONE; DONE;
}" }
[(set_attr "itanium_class" "unknown") [(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -608,26 +601,24 @@ ...@@ -608,26 +601,24 @@
(match_operand:TI 1 "" "m")) (match_operand:TI 1 "" "m"))
(clobber (match_operand:TI 2 "register_operand" "=&r"))])] (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
"" ""
"
{ {
unsigned int s_regno = REGNO (operands[2]); unsigned int s_regno = REGNO (operands[2]);
if (s_regno == REGNO (operands[0])) if (s_regno == REGNO (operands[0]))
s_regno += 1; s_regno += 1;
operands[2] = gen_rtx_REG (DImode, s_regno); operands[2] = gen_rtx_REG (DImode, s_regno);
}") })
(define_expand "reload_outti" (define_expand "reload_outti"
[(parallel [(set (match_operand:TI 0 "" "=m") [(parallel [(set (match_operand:TI 0 "" "=m")
(match_operand:TI 1 "register_operand" "r")) (match_operand:TI 1 "register_operand" "r"))
(clobber (match_operand:TI 2 "register_operand" "=&r"))])] (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
"" ""
"
{ {
unsigned int s_regno = REGNO (operands[2]); unsigned int s_regno = REGNO (operands[2]);
if (s_regno == REGNO (operands[1])) if (s_regno == REGNO (operands[1]))
s_regno += 1; s_regno += 1;
operands[2] = gen_rtx_REG (DImode, s_regno); operands[2] = gen_rtx_REG (DImode, s_regno);
}") })
;; Floating Point Moves ;; Floating Point Moves
;; ;;
...@@ -638,52 +629,50 @@ ...@@ -638,52 +629,50 @@
[(set (match_operand:SF 0 "general_operand" "") [(set (match_operand:SF 0 "general_operand" "")
(match_operand:SF 1 "general_operand" ""))] (match_operand:SF 1 "general_operand" ""))]
"" ""
"
{ {
if (! reload_in_progress && ! reload_completed if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1])) && ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (SFmode, operands[1]); operands[1] = force_reg (SFmode, operands[1]);
}") })
(define_insn "*movsf_internal" (define_insn "*movsf_internal"
[(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"ia64_move_ok (operands[0], operands[1])" "ia64_move_ok (operands[0], operands[1])"
"@ "@
mov %0 = %F1 mov %0 = %F1
ldfs %0 = %1%P1 ldfs %0 = %1%P1
stfs %0 = %F1%P0 stfs %0 = %F1%P0
getf.s %0 = %F1 getf.s %0 = %F1
setf.s %0 = %1 setf.s %0 = %1
mov %0 = %1 mov %0 = %1
ld4%O1 %0 = %1%P1 ld4%O1 %0 = %1%P1
st4%Q0 %0 = %1%P0" st4%Q0 %0 = %1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
(define_expand "movdf" (define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "") [(set (match_operand:DF 0 "general_operand" "")
(match_operand:DF 1 "general_operand" ""))] (match_operand:DF 1 "general_operand" ""))]
"" ""
"
{ {
if (! reload_in_progress && ! reload_completed if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1])) && ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (DFmode, operands[1]); operands[1] = force_reg (DFmode, operands[1]);
}") })
(define_insn "*movdf_internal" (define_insn "*movdf_internal"
[(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"ia64_move_ok (operands[0], operands[1])" "ia64_move_ok (operands[0], operands[1])"
"@ "@
mov %0 = %F1 mov %0 = %F1
ldfd %0 = %1%P1 ldfd %0 = %1%P1
stfd %0 = %F1%P0 stfd %0 = %F1%P0
getf.d %0 = %F1 getf.d %0 = %F1
setf.d %0 = %1 setf.d %0 = %1
mov %0 = %1 mov %0 = %1
ld8%O1 %0 = %1%P1 ld8%O1 %0 = %1%P1
st8%Q0 %0 = %1%P0" st8%Q0 %0 = %1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
;; With no offsettable memory references, we've got to have a scratch ;; With no offsettable memory references, we've got to have a scratch
...@@ -692,7 +681,6 @@ ...@@ -692,7 +681,6 @@
[(set (match_operand:TF 0 "general_operand" "") [(set (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" ""))] (match_operand:TF 1 "general_operand" ""))]
"INTEL_EXTENDED_IEEE_FORMAT" "INTEL_EXTENDED_IEEE_FORMAT"
"
{ {
/* We must support TFmode loads into general registers for stdarg/vararg /* We must support TFmode loads into general registers for stdarg/vararg
and unprototyped calls. We split them into DImode loads for convenience. and unprototyped calls. We split them into DImode loads for convenience.
...@@ -753,7 +741,7 @@ ...@@ -753,7 +741,7 @@
if (! ia64_move_ok (operands[0], operands[1])) if (! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (TFmode, operands[1]); operands[1] = force_reg (TFmode, operands[1]);
} }
}") })
;; ??? There's no easy way to mind volatile acquire/release semantics. ;; ??? There's no easy way to mind volatile acquire/release semantics.
...@@ -762,9 +750,9 @@ ...@@ -762,9 +750,9 @@
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))] (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
"INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])" "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])"
"@ "@
mov %0 = %F1 mov %0 = %F1
ldfe %0 = %1%P1 ldfe %0 = %1%P1
stfe %0 = %F1%P0" stfe %0 = %F1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf")]) [(set_attr "itanium_class" "fmisc,fld,stf")])
;; :::::::::::::::::::: ;; ::::::::::::::::::::
...@@ -1032,7 +1020,6 @@ ...@@ -1032,7 +1020,6 @@
(match_operand:DI 2 "const_int_operand" "")) (match_operand:DI 2 "const_int_operand" ""))
(match_operand:DI 3 "nonmemory_operand" ""))] (match_operand:DI 3 "nonmemory_operand" ""))]
"" ""
"
{ {
int width = INTVAL (operands[1]); int width = INTVAL (operands[1]);
int shift = INTVAL (operands[2]); int shift = INTVAL (operands[2]);
...@@ -1100,7 +1087,7 @@ ...@@ -1100,7 +1087,7 @@
operands[2] = GEN_INT (shift); operands[2] = GEN_INT (shift);
#endif #endif
} }
}") })
(define_insn "*insv_internal" (define_insn "*insv_internal"
[(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
...@@ -1120,11 +1107,10 @@ ...@@ -1120,11 +1107,10 @@
(match_operand:DI 3 "const_int_operand" "n")))] (match_operand:DI 3 "const_int_operand" "n")))]
"CONST_OK_FOR_M (INTVAL (operands[2])) "CONST_OK_FOR_M (INTVAL (operands[2]))
&& ia64_depz_field_mask (operands[3], operands[2]) > 0" && ia64_depz_field_mask (operands[3], operands[2]) > 0"
"*
{ {
operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
return \"%,dep.z %0 = %1, %2, %3\"; return "%,dep.z %0 = %1, %2, %3";
}" }
[(set_attr "itanium_class" "ishf")]) [(set_attr "itanium_class" "ishf")])
(define_insn "shift_mix4left" (define_insn "shift_mix4left"
...@@ -1728,9 +1714,9 @@ ...@@ -1728,9 +1714,9 @@
(match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
"" ""
"@ "@
add %0 = %1, %2 add %0 = %1, %2
adds %0 = %2, %1 adds %0 = %2, %1
addl %0 = %2, %1" addl %0 = %2, %1"
[(set_attr "itanium_class" "ialu")]) [(set_attr "itanium_class" "ialu")])
(define_insn "*addsi3_plus1" (define_insn "*addsi3_plus1"
...@@ -1810,10 +1796,7 @@ ...@@ -1810,10 +1796,7 @@
(neg:SI (match_dup 1)) (neg:SI (match_dup 1))
(match_dup 1)))] (match_dup 1)))]
"" ""
" { operands[2] = gen_reg_rtx (BImode); })
{
operands[2] = gen_reg_rtx (BImode);
}")
(define_expand "sminsi3" (define_expand "sminsi3"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -1823,10 +1806,7 @@ ...@@ -1823,10 +1806,7 @@
(if_then_else:SI (ne (match_dup 3) (const_int 0)) (if_then_else:SI (ne (match_dup 3) (const_int 0))
(match_dup 2) (match_dup 1)))] (match_dup 2) (match_dup 1)))]
"" ""
" { operands[3] = gen_reg_rtx (BImode); })
{
operands[3] = gen_reg_rtx (BImode);
}")
(define_expand "smaxsi3" (define_expand "smaxsi3"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -1836,10 +1816,7 @@ ...@@ -1836,10 +1816,7 @@
(if_then_else:SI (ne (match_dup 3) (const_int 0)) (if_then_else:SI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"" ""
" { operands[3] = gen_reg_rtx (BImode); })
{
operands[3] = gen_reg_rtx (BImode);
}")
(define_expand "uminsi3" (define_expand "uminsi3"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -1849,10 +1826,7 @@ ...@@ -1849,10 +1826,7 @@
(if_then_else:SI (ne (match_dup 3) (const_int 0)) (if_then_else:SI (ne (match_dup 3) (const_int 0))
(match_dup 2) (match_dup 1)))] (match_dup 2) (match_dup 1)))]
"" ""
" { operands[3] = gen_reg_rtx (BImode); })
{
operands[3] = gen_reg_rtx (BImode);
}")
(define_expand "umaxsi3" (define_expand "umaxsi3"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -1862,17 +1836,13 @@ ...@@ -1862,17 +1836,13 @@
(if_then_else:SI (ne (match_dup 3) (const_int 0)) (if_then_else:SI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"" ""
" { operands[3] = gen_reg_rtx (BImode); })
{
operands[3] = gen_reg_rtx (BImode);
}")
(define_expand "divsi3" (define_expand "divsi3"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "") (div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))] (match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
...@@ -1904,14 +1874,13 @@ ...@@ -1904,14 +1874,13 @@
emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
DONE; DONE;
}") })
(define_expand "modsi3" (define_expand "modsi3"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "") (mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))] (match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx op2_neg, op1_di, div; rtx op2_neg, op1_di, div;
...@@ -1928,14 +1897,13 @@ ...@@ -1928,14 +1897,13 @@
emit_insn (gen_maddsi4 (operands[0], div, op2_neg, emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
gen_lowpart (SImode, op1_di))); gen_lowpart (SImode, op1_di)));
DONE; DONE;
}") })
(define_expand "udivsi3" (define_expand "udivsi3"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "") (udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))] (match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
...@@ -1967,14 +1935,13 @@ ...@@ -1967,14 +1935,13 @@
emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
DONE; DONE;
}") })
(define_expand "umodsi3" (define_expand "umodsi3"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "") (umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))] (match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx op2_neg, op1_di, div; rtx op2_neg, op1_di, div;
...@@ -1991,7 +1958,7 @@ ...@@ -1991,7 +1958,7 @@
emit_insn (gen_maddsi4 (operands[0], div, op2_neg, emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
gen_lowpart (SImode, op1_di))); gen_lowpart (SImode, op1_di)));
DONE; DONE;
}") })
(define_insn_and_split "divsi3_internal" (define_insn_and_split "divsi3_internal"
[(set (match_operand:TF 0 "fr_register_operand" "=&f") [(set (match_operand:TF 0 "fr_register_operand" "=&f")
...@@ -2047,9 +2014,9 @@ ...@@ -2047,9 +2014,9 @@
(match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
"" ""
"@ "@
add %0 = %1, %2 add %0 = %1, %2
adds %0 = %2, %1 adds %0 = %2, %1
addl %0 = %2, %1" addl %0 = %2, %1"
[(set_attr "itanium_class" "ialu")]) [(set_attr "itanium_class" "ialu")])
(define_insn "*adddi3_plus1" (define_insn "*adddi3_plus1"
...@@ -2198,10 +2165,7 @@ ...@@ -2198,10 +2165,7 @@
(neg:DI (match_dup 1)) (neg:DI (match_dup 1))
(match_dup 1)))] (match_dup 1)))]
"" ""
" { operands[2] = gen_reg_rtx (BImode); })
{
operands[2] = gen_reg_rtx (BImode);
}")
(define_expand "smindi3" (define_expand "smindi3"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -2211,10 +2175,7 @@ ...@@ -2211,10 +2175,7 @@
(if_then_else:DI (ne (match_dup 3) (const_int 0)) (if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 2) (match_dup 1)))] (match_dup 2) (match_dup 1)))]
"" ""
" { operands[3] = gen_reg_rtx (BImode); })
{
operands[3] = gen_reg_rtx (BImode);
}")
(define_expand "smaxdi3" (define_expand "smaxdi3"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -2224,10 +2185,7 @@ ...@@ -2224,10 +2185,7 @@
(if_then_else:DI (ne (match_dup 3) (const_int 0)) (if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"" ""
" { operands[3] = gen_reg_rtx (BImode); })
{
operands[3] = gen_reg_rtx (BImode);
}")
(define_expand "umindi3" (define_expand "umindi3"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -2237,10 +2195,7 @@ ...@@ -2237,10 +2195,7 @@
(if_then_else:DI (ne (match_dup 3) (const_int 0)) (if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 2) (match_dup 1)))] (match_dup 2) (match_dup 1)))]
"" ""
" { operands[3] = gen_reg_rtx (BImode); })
{
operands[3] = gen_reg_rtx (BImode);
}")
(define_expand "umaxdi3" (define_expand "umaxdi3"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -2250,10 +2205,7 @@ ...@@ -2250,10 +2205,7 @@
(if_then_else:DI (ne (match_dup 3) (const_int 0)) (if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"" ""
" { operands[3] = gen_reg_rtx (BImode); })
{
operands[3] = gen_reg_rtx (BImode);
}")
(define_expand "ffsdi2" (define_expand "ffsdi2"
[(set (match_dup 6) [(set (match_dup 6)
...@@ -2266,14 +2218,13 @@ ...@@ -2266,14 +2218,13 @@
(if_then_else:DI (ne (match_dup 6) (const_int 0)) (if_then_else:DI (ne (match_dup 6) (const_int 0))
(match_dup 5) (match_dup 4)))] (match_dup 5) (match_dup 4)))]
"" ""
"
{ {
operands[2] = gen_reg_rtx (DImode); operands[2] = gen_reg_rtx (DImode);
operands[3] = gen_reg_rtx (DImode); operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (DImode);
operands[5] = gen_reg_rtx (DImode); operands[5] = gen_reg_rtx (DImode);
operands[6] = gen_reg_rtx (BImode); operands[6] = gen_reg_rtx (BImode);
}") })
(define_insn "*popcnt" (define_insn "*popcnt"
[(set (match_operand:DI 0 "gr_register_operand" "=r") [(set (match_operand:DI 0 "gr_register_operand" "=r")
...@@ -2288,7 +2239,6 @@ ...@@ -2288,7 +2239,6 @@
(div:DI (match_operand:DI 1 "general_operand" "") (div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))] (match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx op1_tf, op2_tf, op0_tf; rtx op1_tf, op2_tf, op0_tf;
...@@ -2311,14 +2261,13 @@ ...@@ -2311,14 +2261,13 @@
emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
DONE; DONE;
}") })
(define_expand "moddi3" (define_expand "moddi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "") (mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))] (match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx op2_neg, div; rtx op2_neg, div;
...@@ -2329,14 +2278,13 @@ ...@@ -2329,14 +2278,13 @@
emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
DONE; DONE;
}") })
(define_expand "udivdi3" (define_expand "udivdi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "") (udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))] (match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx op1_tf, op2_tf, op0_tf; rtx op1_tf, op2_tf, op0_tf;
...@@ -2359,14 +2307,13 @@ ...@@ -2359,14 +2307,13 @@
emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
DONE; DONE;
}") })
(define_expand "umoddi3" (define_expand "umoddi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "") (umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))] (match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx op2_neg, div; rtx op2_neg, div;
...@@ -2377,7 +2324,7 @@ ...@@ -2377,7 +2324,7 @@
emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
DONE; DONE;
}") })
(define_insn_and_split "divdi3_internal_lat" (define_insn_and_split "divdi3_internal_lat"
[(set (match_operand:TF 0 "fr_register_operand" "=&f") [(set (match_operand:TF 0 "fr_register_operand" "=&f")
...@@ -2598,7 +2545,6 @@ ...@@ -2598,7 +2545,6 @@
(div:SF (match_operand:SF 1 "fr_register_operand" "") (div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))] (match_operand:SF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx insn; rtx insn;
if (TARGET_INLINE_DIV_LAT) if (TARGET_INLINE_DIV_LAT)
...@@ -2607,7 +2553,7 @@ ...@@ -2607,7 +2553,7 @@
insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
emit_insn (insn); emit_insn (insn);
DONE; DONE;
}") })
(define_insn_and_split "divsf3_internal_lat" (define_insn_and_split "divsf3_internal_lat"
[(set (match_operand:SF 0 "fr_register_operand" "=&f") [(set (match_operand:SF 0 "fr_register_operand" "=&f")
...@@ -2657,11 +2603,13 @@ ...@@ -2657,11 +2603,13 @@
(set (match_dup 0) (set (match_dup 0)
(float_truncate:SF (match_dup 6)))) (float_truncate:SF (match_dup 6))))
] ]
"operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); {
operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
operands[10] = CONST1_RTX (TFmode);" operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
operands[10] = CONST1_RTX (TFmode);
}
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
(define_insn_and_split "divsf3_internal_thr" (define_insn_and_split "divsf3_internal_thr"
...@@ -2709,11 +2657,13 @@ ...@@ -2709,11 +2657,13 @@
(plus:TF (mult:TF (match_dup 4) (match_dup 6)) (plus:TF (mult:TF (match_dup 4) (match_dup 6))
(match_dup 3))))) (match_dup 3)))))
] ]
"operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); {
operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
operands[10] = CONST1_RTX (TFmode);" operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
operands[10] = CONST1_RTX (TFmode);
}
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
;; :::::::::::::::::::: ;; ::::::::::::::::::::
...@@ -2904,7 +2854,6 @@ ...@@ -2904,7 +2854,6 @@
(div:DF (match_operand:DF 1 "fr_register_operand" "") (div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))] (match_operand:DF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx insn; rtx insn;
if (TARGET_INLINE_DIV_LAT) if (TARGET_INLINE_DIV_LAT)
...@@ -2913,7 +2862,7 @@ ...@@ -2913,7 +2862,7 @@
insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
emit_insn (insn); emit_insn (insn);
DONE; DONE;
}") })
(define_insn_and_split "divdf3_internal_lat" (define_insn_and_split "divdf3_internal_lat"
[(set (match_operand:DF 0 "fr_register_operand" "=&f") [(set (match_operand:DF 0 "fr_register_operand" "=&f")
...@@ -2986,12 +2935,14 @@ ...@@ -2986,12 +2935,14 @@
(float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7)) (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
(match_dup 3))))) (match_dup 3)))))
] ]
"operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0])); {
operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1])); operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2])); operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
operands[12] = CONST1_RTX (TFmode);" operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
operands[12] = CONST1_RTX (TFmode);
}
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
(define_insn_and_split "divdf3_internal_thr" (define_insn_and_split "divdf3_internal_thr"
...@@ -3051,11 +3002,13 @@ ...@@ -3051,11 +3002,13 @@
(plus:DF (mult:DF (match_dup 4) (match_dup 0)) (plus:DF (mult:DF (match_dup 4) (match_dup 0))
(match_dup 9)))) (match_dup 9))))
] ]
"operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); {
operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
operands[10] = CONST1_RTX (TFmode);" operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
operands[10] = CONST1_RTX (TFmode);
}
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
;; :::::::::::::::::::: ;; ::::::::::::::::::::
...@@ -3378,7 +3331,6 @@ ...@@ -3378,7 +3331,6 @@
(div:TF (match_operand:TF 1 "fr_register_operand" "") (div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))] (match_operand:TF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"
{ {
rtx insn; rtx insn;
if (TARGET_INLINE_DIV_LAT) if (TARGET_INLINE_DIV_LAT)
...@@ -3387,7 +3339,7 @@ ...@@ -3387,7 +3339,7 @@
insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]); insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
emit_insn (insn); emit_insn (insn);
DONE; DONE;
}") })
(define_insn_and_split "divtf3_internal_lat" (define_insn_and_split "divtf3_internal_lat"
[(set (match_operand:TF 0 "fr_register_operand" "=&f") [(set (match_operand:TF 0 "fr_register_operand" "=&f")
...@@ -3573,7 +3525,6 @@ ...@@ -3573,7 +3525,6 @@
(ashift:SI (match_operand:SI 1 "gr_register_operand" "") (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
"" ""
"
{ {
if (GET_CODE (operands[2]) != CONST_INT) if (GET_CODE (operands[2]) != CONST_INT)
{ {
...@@ -3583,7 +3534,7 @@ ...@@ -3583,7 +3534,7 @@
emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
operands[2] = subshift; operands[2] = subshift;
} }
}") })
(define_insn "*ashlsi3_internal" (define_insn "*ashlsi3_internal"
[(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
...@@ -3601,7 +3552,6 @@ ...@@ -3601,7 +3552,6 @@
(ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
"" ""
"
{ {
rtx subtarget = gen_reg_rtx (DImode); rtx subtarget = gen_reg_rtx (DImode);
if (GET_CODE (operands[2]) == CONST_INT) if (GET_CODE (operands[2]) == CONST_INT)
...@@ -3616,14 +3566,13 @@ ...@@ -3616,14 +3566,13 @@
} }
emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
DONE; DONE;
}") })
(define_expand "lshrsi3" (define_expand "lshrsi3"
[(set (match_operand:SI 0 "gr_register_operand" "") [(set (match_operand:SI 0 "gr_register_operand" "")
(lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
"" ""
"
{ {
rtx subtarget = gen_reg_rtx (DImode); rtx subtarget = gen_reg_rtx (DImode);
if (GET_CODE (operands[2]) == CONST_INT) if (GET_CODE (operands[2]) == CONST_INT)
...@@ -3638,7 +3587,7 @@ ...@@ -3638,7 +3587,7 @@
} }
emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
DONE; DONE;
}") })
;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
;; here, instead of 64 like the patterns above. Keep the pattern together ;; here, instead of 64 like the patterns above. Keep the pattern together
...@@ -3649,7 +3598,6 @@ ...@@ -3649,7 +3598,6 @@
(rotatert:SI (match_operand:SI 1 "gr_register_operand" "") (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
"" ""
"
{ {
if (GET_MODE (operands[2]) != VOIDmode) if (GET_MODE (operands[2]) != VOIDmode)
{ {
...@@ -3657,7 +3605,7 @@ ...@@ -3657,7 +3605,7 @@
emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
operands[2] = tmp; operands[2] = tmp;
} }
}") })
(define_insn_and_split "*rotrsi3_internal" (define_insn_and_split "*rotrsi3_internal"
[(set (match_operand:SI 0 "gr_register_operand" "=&r") [(set (match_operand:SI 0 "gr_register_operand" "=&r")
...@@ -3678,7 +3626,6 @@ ...@@ -3678,7 +3626,6 @@
(rotate:SI (match_operand:SI 1 "gr_register_operand" "") (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
"" ""
"
{ {
if (! shift_32bit_count_operand (operands[2], SImode)) if (! shift_32bit_count_operand (operands[2], SImode))
{ {
...@@ -3687,7 +3634,7 @@ ...@@ -3687,7 +3634,7 @@
emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
DONE; DONE;
} }
}") })
(define_insn_and_split "*rotlsi3_internal" (define_insn_and_split "*rotlsi3_internal"
[(set (match_operand:SI 0 "gr_register_operand" "=r") [(set (match_operand:SI 0 "gr_register_operand" "=r")
...@@ -3701,8 +3648,10 @@ ...@@ -3701,8 +3648,10 @@
(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
(set (match_dup 3) (set (match_dup 3)
(lshiftrt:DI (match_dup 3) (match_dup 2)))] (lshiftrt:DI (match_dup 3) (match_dup 2)))]
"operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); {
operands[2] = GEN_INT (32 - INTVAL (operands[2]));") operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
})
;; :::::::::::::::::::: ;; ::::::::::::::::::::
;; :: ;; ::
...@@ -3785,11 +3734,10 @@ ...@@ -3785,11 +3734,10 @@
(rotatert:DI (match_operand:DI 1 "gr_register_operand" "") (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
(match_operand:DI 2 "nonmemory_operand" "")))] (match_operand:DI 2 "nonmemory_operand" "")))]
"" ""
"
{ {
if (! shift_count_operand (operands[2], DImode)) if (! shift_count_operand (operands[2], DImode))
FAIL; FAIL;
}") })
(define_insn "*rotrdi3_internal" (define_insn "*rotrdi3_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r") [(set (match_operand:DI 0 "gr_register_operand" "=r")
...@@ -3804,11 +3752,10 @@ ...@@ -3804,11 +3752,10 @@
(rotate:DI (match_operand:DI 1 "gr_register_operand" "") (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
(match_operand:DI 2 "nonmemory_operand" "")))] (match_operand:DI 2 "nonmemory_operand" "")))]
"" ""
"
{ {
if (! shift_count_operand (operands[2], DImode)) if (! shift_count_operand (operands[2], DImode))
FAIL; FAIL;
}") })
(define_insn "*rotldi3_internal" (define_insn "*rotldi3_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r") [(set (match_operand:DI 0 "gr_register_operand" "=r")
...@@ -3909,72 +3856,66 @@ ...@@ -3909,72 +3856,66 @@
(compare (match_operand:BI 0 "register_operand" "") (compare (match_operand:BI 0 "register_operand" "")
(match_operand:BI 1 "const_int_operand" "")))] (match_operand:BI 1 "const_int_operand" "")))]
"" ""
"
{ {
ia64_compare_op0 = operands[0]; ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1]; ia64_compare_op1 = operands[1];
DONE; DONE;
}") })
(define_expand "cmpsi" (define_expand "cmpsi"
[(set (cc0) [(set (cc0)
(compare (match_operand:SI 0 "gr_register_operand" "") (compare (match_operand:SI 0 "gr_register_operand" "")
(match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
"" ""
"
{ {
ia64_compare_op0 = operands[0]; ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1]; ia64_compare_op1 = operands[1];
DONE; DONE;
}") })
(define_expand "cmpdi" (define_expand "cmpdi"
[(set (cc0) [(set (cc0)
(compare (match_operand:DI 0 "gr_register_operand" "") (compare (match_operand:DI 0 "gr_register_operand" "")
(match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
"" ""
"
{ {
ia64_compare_op0 = operands[0]; ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1]; ia64_compare_op1 = operands[1];
DONE; DONE;
}") })
(define_expand "cmpsf" (define_expand "cmpsf"
[(set (cc0) [(set (cc0)
(compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
(match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
"" ""
"
{ {
ia64_compare_op0 = operands[0]; ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1]; ia64_compare_op1 = operands[1];
DONE; DONE;
}") })
(define_expand "cmpdf" (define_expand "cmpdf"
[(set (cc0) [(set (cc0)
(compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
(match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
"" ""
"
{ {
ia64_compare_op0 = operands[0]; ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1]; ia64_compare_op1 = operands[1];
DONE; DONE;
}") })
(define_expand "cmptf" (define_expand "cmptf"
[(set (cc0) [(set (cc0)
(compare (match_operand:TF 0 "tfreg_or_fp01_operand" "") (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
(match_operand:TF 1 "tfreg_or_fp01_operand" "")))] (match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT" "INTEL_EXTENDED_IEEE_FORMAT"
"
{ {
ia64_compare_op0 = operands[0]; ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1]; ia64_compare_op1 = operands[1];
DONE; DONE;
}") })
(define_insn "*cmpsi_normal" (define_insn "*cmpsi_normal"
[(set (match_operand:BI 0 "register_operand" "=c") [(set (match_operand:BI 0 "register_operand" "=c")
...@@ -4206,7 +4147,6 @@ ...@@ -4206,7 +4147,6 @@
(use (match_operand 3 "" "")) ; loop level (use (match_operand 3 "" "")) ; loop level
(use (match_operand 4 "" ""))] ; label (use (match_operand 4 "" ""))] ; label
"" ""
"
{ {
/* Only use cloop on innermost loops. */ /* Only use cloop on innermost loops. */
if (INTVAL (operands[3]) > 1) if (INTVAL (operands[3]) > 1)
...@@ -4214,7 +4154,7 @@ ...@@ -4214,7 +4154,7 @@
emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
operands[4])); operands[4]));
DONE; DONE;
}") })
(define_insn "doloop_end_internal" (define_insn "doloop_end_internal"
[(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
...@@ -4352,7 +4292,7 @@ ...@@ -4352,7 +4292,7 @@
"rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
"ia64_move_ok (operands[0], operands[2]) "ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])" && ia64_move_ok (operands[0], operands[3])"
"* abort ();" { abort (); }
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
(define_split (define_split
...@@ -4365,7 +4305,6 @@ ...@@ -4365,7 +4305,6 @@
(match_operand 3 "move_operand" "")))] (match_operand 3 "move_operand" "")))]
"reload_completed" "reload_completed"
[(const_int 0)] [(const_int 0)]
"
{ {
rtx tmp; rtx tmp;
if (! rtx_equal_p (operands[0], operands[2])) if (! rtx_equal_p (operands[0], operands[2]))
...@@ -4384,7 +4323,7 @@ ...@@ -4384,7 +4323,7 @@
emit_insn (tmp); emit_insn (tmp);
} }
DONE; DONE;
}") })
;; Absolute value pattern. ;; Absolute value pattern.
...@@ -4431,11 +4370,10 @@ ...@@ -4431,11 +4370,10 @@
(cond_exec (cond_exec
(match_dup 5) (match_dup 5)
(set (match_dup 0) (match_dup 3)))] (set (match_dup 0) (match_dup 3)))]
"
{ {
operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
VOIDmode, operands[1], const0_rtx); VOIDmode, operands[1], const0_rtx);
}") })
;; ;;
;; SImode if_then_else patterns. ;; SImode if_then_else patterns.
...@@ -4453,7 +4391,7 @@ ...@@ -4453,7 +4391,7 @@
"rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
"ia64_move_ok (operands[0], operands[2]) "ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])" && ia64_move_ok (operands[0], operands[3])"
"* abort ();" { abort (); }
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
(define_insn "*abssi2_internal" (define_insn "*abssi2_internal"
...@@ -4499,11 +4437,10 @@ ...@@ -4499,11 +4437,10 @@
(cond_exec (cond_exec
(match_dup 5) (match_dup 5)
(set (match_dup 0) (match_dup 3)))] (set (match_dup 0) (match_dup 3)))]
"
{ {
operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
VOIDmode, operands[1], const0_rtx); VOIDmode, operands[1], const0_rtx);
}") })
(define_insn_and_split "*cond_opsi2_internal" (define_insn_and_split "*cond_opsi2_internal"
[(set (match_operand:SI 0 "gr_register_operand" "=r") [(set (match_operand:SI 0 "gr_register_operand" "=r")
...@@ -4524,11 +4461,10 @@ ...@@ -4524,11 +4461,10 @@
(cond_exec (cond_exec
(match_dup 7) (match_dup 7)
(set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
"
{ {
operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
VOIDmode, operands[1], const0_rtx); VOIDmode, operands[1], const0_rtx);
}" }
[(set_attr "itanium_class" "ialu") [(set_attr "itanium_class" "ialu")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -4552,11 +4488,10 @@ ...@@ -4552,11 +4488,10 @@
(cond_exec (cond_exec
(match_dup 7) (match_dup 7)
(set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
"
{ {
operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
VOIDmode, operands[1], const0_rtx); VOIDmode, operands[1], const0_rtx);
}" }
[(set_attr "itanium_class" "ialu") [(set_attr "itanium_class" "ialu")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -4583,11 +4518,10 @@ ...@@ -4583,11 +4518,10 @@
(use (match_operand 2 "" "")) (use (match_operand 2 "" ""))
(use (match_operand 3 "" ""))] (use (match_operand 3 "" ""))]
"" ""
"
{ {
ia64_expand_call (NULL_RTX, operands[0], operands[2], 0); ia64_expand_call (NULL_RTX, operands[0], operands[2], 0);
DONE; DONE;
}") })
(define_expand "sibcall" (define_expand "sibcall"
[(use (match_operand:DI 0 "" "")) [(use (match_operand:DI 0 "" ""))
...@@ -4595,11 +4529,10 @@ ...@@ -4595,11 +4529,10 @@
(use (match_operand 2 "" "")) (use (match_operand 2 "" ""))
(use (match_operand 3 "" ""))] (use (match_operand 3 "" ""))]
"" ""
"
{ {
ia64_expand_call (NULL_RTX, operands[0], operands[2], 1); ia64_expand_call (NULL_RTX, operands[0], operands[2], 1);
DONE; DONE;
}") })
;; Subroutine call instruction returning a value. Operand 0 is the hard ;; Subroutine call instruction returning a value. Operand 0 is the hard
;; register in which the value is returned. There are three more operands, ;; register in which the value is returned. There are three more operands,
...@@ -4615,11 +4548,10 @@ ...@@ -4615,11 +4548,10 @@
(use (match_operand 3 "" "")) (use (match_operand 3 "" ""))
(use (match_operand 4 "" ""))] (use (match_operand 4 "" ""))]
"" ""
"
{ {
ia64_expand_call (operands[0], operands[1], operands[3], 0); ia64_expand_call (operands[0], operands[1], operands[3], 0);
DONE; DONE;
}") })
(define_expand "sibcall_value" (define_expand "sibcall_value"
[(use (match_operand 0 "" "")) [(use (match_operand 0 "" ""))
...@@ -4628,11 +4560,10 @@ ...@@ -4628,11 +4560,10 @@
(use (match_operand 3 "" "")) (use (match_operand 3 "" ""))
(use (match_operand 4 "" ""))] (use (match_operand 4 "" ""))]
"" ""
"
{ {
ia64_expand_call (operands[0], operands[1], operands[3], 1); ia64_expand_call (operands[0], operands[1], operands[3], 1);
DONE; DONE;
}") })
;; Call subroutine returning any type. ;; Call subroutine returning any type.
...@@ -4642,7 +4573,6 @@ ...@@ -4642,7 +4573,6 @@
(match_operand 1 "" "") (match_operand 1 "" "")
(match_operand 2 "" "")])] (match_operand 2 "" "")])]
"" ""
"
{ {
int i; int i;
...@@ -4661,7 +4591,7 @@ ...@@ -4661,7 +4591,7 @@
emit_insn (gen_blockage ()); emit_insn (gen_blockage ());
DONE; DONE;
}") })
(define_insn "call_nopic" (define_insn "call_nopic"
[(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
...@@ -4826,29 +4756,26 @@ ...@@ -4826,29 +4756,26 @@
(define_expand "prologue" (define_expand "prologue"
[(const_int 1)] [(const_int 1)]
"" ""
"
{ {
ia64_expand_prologue (); ia64_expand_prologue ();
DONE; DONE;
}") })
(define_expand "epilogue" (define_expand "epilogue"
[(return)] [(return)]
"" ""
"
{ {
ia64_expand_epilogue (0); ia64_expand_epilogue (0);
DONE; DONE;
}") })
(define_expand "sibcall_epilogue" (define_expand "sibcall_epilogue"
[(return)] [(return)]
"" ""
"
{ {
ia64_expand_epilogue (1); ia64_expand_epilogue (1);
DONE; DONE;
}") })
;; This prevents the scheduler from moving the SP decrement past FP-relative ;; This prevents the scheduler from moving the SP decrement past FP-relative
;; stack accesses. This is the same as adddi3 plus the extra set. ;; stack accesses. This is the same as adddi3 plus the extra set.
...@@ -4861,9 +4788,9 @@ ...@@ -4861,9 +4788,9 @@
(match_dup 3))] (match_dup 3))]
"" ""
"@ "@
add %0 = %1, %2 add %0 = %1, %2
adds %0 = %2, %1 adds %0 = %2, %1
addl %0 = %2, %1" addl %0 = %2, %1"
[(set_attr "itanium_class" "ialu")]) [(set_attr "itanium_class" "ialu")])
;; This prevents the scheduler from moving the SP restore past FP-relative ;; This prevents the scheduler from moving the SP restore past FP-relative
...@@ -4877,6 +4804,16 @@ ...@@ -4877,6 +4804,16 @@
"mov %0 = %1" "mov %0 = %1"
[(set_attr "itanium_class" "ialu")]) [(set_attr "itanium_class" "ialu")])
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for EH handling
(define_insn "prologue_use"
[(unspec:DI [(match_operand:DI 0 "register_operand" "")]
UNSPEC_PROLOGUE_USE)]
""
""
[(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
;; Allocate a new register frame. ;; Allocate a new register frame.
(define_insn "alloc" (define_insn "alloc"
...@@ -4908,10 +4845,11 @@ ...@@ -4908,10 +4845,11 @@
UNSPEC_GR_SPILL)) UNSPEC_GR_SPILL))
(clobber (match_operand:DI 3 "register_operand" ""))] (clobber (match_operand:DI 3 "register_operand" ""))]
"" ""
"*
{ {
return \".mem.offset %2, 0\;%,st8.spill %0 = %1%P0\"; /* Note that we use a C output pattern here to avoid the predicate
}" being automatically added before the .mem.offset directive. */
return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
}
[(set_attr "itanium_class" "st")]) [(set_attr "itanium_class" "st")])
;; Reads ar.unat ;; Reads ar.unat
...@@ -4931,10 +4869,7 @@ ...@@ -4931,10 +4869,7 @@
UNSPEC_GR_RESTORE)) UNSPEC_GR_RESTORE))
(use (match_operand:DI 3 "register_operand" ""))] (use (match_operand:DI 3 "register_operand" ""))]
"" ""
"* { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
{
return \".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1\";
}"
[(set_attr "itanium_class" "ld")]) [(set_attr "itanium_class" "ld")])
(define_insn "fr_spill" (define_insn "fr_spill"
...@@ -4968,7 +4903,21 @@ ...@@ -4968,7 +4903,21 @@
[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
UNSPECV_SET_BSP)] UNSPECV_SET_BSP)]
"" ""
"flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19" "flushrs
mov r19=ar.rsc
;;
and r19=0x1c,r19
;;
mov ar.rsc=r19
;;
mov ar.bspstore=%0
;;
or r19=0x3,r19
;;
loadrs
invala
;;
mov ar.rsc=r19"
[(set_attr "itanium_class" "unknown") [(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -5031,10 +4980,7 @@ ...@@ -5031,10 +4980,7 @@
(define_insn "bundle_selector" (define_insn "bundle_selector"
[(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
"" ""
"* { return get_bundle_name (INTVAL (operands[0])); }
{
return get_bundle_name (INTVAL (operands[0]));
}"
[(set_attr "itanium_class" "ignore") [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -5129,14 +5075,13 @@ ...@@ -5129,14 +5075,13 @@
[(use (match_operand:OI 0 "memory_operand" "")) [(use (match_operand:OI 0 "memory_operand" ""))
(use (match_operand:DI 1 "register_operand" ""))] (use (match_operand:DI 1 "register_operand" ""))]
"" ""
"
{ {
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
\"__ia64_save_stack_nonlocal\"), \"__ia64_save_stack_nonlocal\"),
0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
operands[1], Pmode); operands[1], Pmode);
DONE; DONE;
}") })
(define_expand "nonlocal_goto" (define_expand "nonlocal_goto"
[(use (match_operand 0 "general_operand" "")) [(use (match_operand 0 "general_operand" ""))
...@@ -5144,7 +5089,6 @@ ...@@ -5144,7 +5089,6 @@
(use (match_operand 2 "general_operand" "")) (use (match_operand 2 "general_operand" ""))
(use (match_operand 3 "general_operand" ""))] (use (match_operand 3 "general_operand" ""))]
"" ""
"
{ {
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
LCT_NORETURN, VOIDmode, 3, LCT_NORETURN, VOIDmode, 3,
...@@ -5153,34 +5097,31 @@ ...@@ -5153,34 +5097,31 @@
operands[3], Pmode); operands[3], Pmode);
emit_barrier (); emit_barrier ();
DONE; DONE;
}") })
;; The rest of the setjmp processing happens with the nonlocal_goto expander. ;; The rest of the setjmp processing happens with the nonlocal_goto expander.
;; ??? This is not tested. ;; ??? This is not tested.
(define_expand "builtin_setjmp_setup" (define_expand "builtin_setjmp_setup"
[(use (match_operand:DI 0 "" ""))] [(use (match_operand:DI 0 "" ""))]
"" ""
"
{ {
emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1))); emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1)));
DONE; DONE;
}") })
(define_expand "builtin_setjmp_receiver" (define_expand "builtin_setjmp_receiver"
[(use (match_operand:DI 0 "" ""))] [(use (match_operand:DI 0 "" ""))]
"" ""
"
{ {
emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0)); emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0));
DONE; DONE;
}") })
(define_expand "eh_epilogue" (define_expand "eh_epilogue"
[(use (match_operand:DI 0 "register_operand" "r")) [(use (match_operand:DI 0 "register_operand" "r"))
(use (match_operand:DI 1 "register_operand" "r")) (use (match_operand:DI 1 "register_operand" "r"))
(use (match_operand:DI 2 "register_operand" "r"))] (use (match_operand:DI 2 "register_operand" "r"))]
"" ""
"
{ {
rtx bsp = gen_rtx_REG (Pmode, 10); rtx bsp = gen_rtx_REG (Pmode, 10);
rtx sp = gen_rtx_REG (Pmode, 9); rtx sp = gen_rtx_REG (Pmode, 9);
...@@ -5200,7 +5141,7 @@ ...@@ -5200,7 +5141,7 @@
cfun->machine->ia64_eh_epilogue_sp = sp; cfun->machine->ia64_eh_epilogue_sp = sp;
cfun->machine->ia64_eh_epilogue_bsp = bsp; cfun->machine->ia64_eh_epilogue_bsp = bsp;
}") })
;; Builtin apply support. ;; Builtin apply support.
...@@ -5208,14 +5149,13 @@ ...@@ -5208,14 +5149,13 @@
[(use (match_operand:DI 0 "register_operand" "")) [(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:OI 1 "memory_operand" ""))] (use (match_operand:OI 1 "memory_operand" ""))]
"" ""
"
{ {
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
\"__ia64_restore_stack_nonlocal\"), "__ia64_restore_stack_nonlocal"),
0, VOIDmode, 1, 0, VOIDmode, 1,
copy_to_reg (XEXP (operands[1], 0)), Pmode); copy_to_reg (XEXP (operands[1], 0)), Pmode);
DONE; DONE;
}") })
;;; Intrinsics support. ;;; Intrinsics support.
...@@ -5224,11 +5164,10 @@ ...@@ -5224,11 +5164,10 @@
[(set (mem:BLK (match_dup 0)) [(set (mem:BLK (match_dup 0))
(unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))] (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
"" ""
"
{ {
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
MEM_VOLATILE_P (operands[0]) = 1; MEM_VOLATILE_P (operands[0]) = 1;
}") })
(define_insn "*mf_internal" (define_insn "*mf_internal"
[(set (match_operand:BLK 0 "" "") [(set (match_operand:BLK 0 "" "")
...@@ -5328,11 +5267,10 @@ ...@@ -5328,11 +5267,10 @@
(define_insn "safe_across_calls_normal" (define_insn "safe_across_calls_normal"
[(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
"" ""
"*
{ {
emit_safe_across_calls (asm_out_file); emit_safe_across_calls (asm_out_file);
return \"\"; return "";
}" }
[(set_attr "itanium_class" "ignore") [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -5369,13 +5307,3 @@ ...@@ -5369,13 +5307,3 @@
"" ""
"addp4 %0 = %1, %2" "addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")]) [(set_attr "itanium_class" "ialu")])
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for EH handling
(define_insn "prologue_use"
[(unspec:DI [(match_operand:DI 0 "register_operand" "")]
UNSPEC_PROLOGUE_USE)]
""
"// %0 needed for EH"
[(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
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