[PATCH][AARCH64][PR66776]Add cmovdi_insn_uxtw pattern.

gcc/

2015-10-02  Renlin Li  <renlin.li@arm.com>

	PR target/66776
	* config/aarch64/aarch64.md (cmovdi_insn_uxtw): New pattern.

gcc/testsuite/

2015-10-02  Renlin Li  <renlin.li@arm.com>

	PR target/66776
	* gcc.target/aarch64/pr66776.c: New.

From-SVN: r228384

gcc/ChangeLog

+2015-10-02  Renlin Li  <renlin.li@arm.com>
+
+	PR target/66776
+	* config/aarch64/aarch64.md (cmovdi_insn_uxtw): New pattern.
+
 2015-10-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	PR rtl-optimization/67786

gcc/config/aarch64/aarch64.md

@@ -3010,6 +3010,18 @@
   [(set_attr "type" "csel")]
 )
 
+(define_insn "*cmovdi_insn_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(if_then_else:DI
+	 (match_operator 1 "aarch64_comparison_operator"
+	  [(match_operand 2 "cc_register" "") (const_int 0)])
+	 (zero_extend:DI (match_operand:SI 3 "register_operand" "r"))
+	 (zero_extend:DI (match_operand:SI 4 "register_operand" "r"))))]
+  ""
+  "csel\\t%w0, %w3, %w4, %m1"
+  [(set_attr "type" "csel")]
+)
+
 (define_insn "*cmov<mode>_insn"
   [(set (match_operand:GPF 0 "register_operand" "=w")
 	(if_then_else:GPF

gcc/testsuite/ChangeLog

+2015-10-02  Renlin Li  <renlin.li@arm.com>
+
+	PR target/66776
+	* gcc.target/aarch64/pr66776.c: New.
+
 2015-10-02  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gnat.dg/warn13.adb: New test.

gcc/testsuite/gcc.target/aarch64/pr66776.c

+/* { dg-do compile } */
+/* { dg-options "-O2 --save-temps" } */
+
+unsigned long long
+foo (unsigned int a, unsigned int b, unsigned int c)
+{
+  return a ? b : c;
+}
+
+/* { dg-final { scan-assembler-not "uxtw" } } */