Commit 17640f24 by Eric Christopher

configure.target: Fix comment for mips atomicity.

2002-07-08  Eric Christopher  <echristo@redhat.com>

	* configure.target: Fix comment for mips atomicity. Add
	mips*-*-linux* target, enable atomic operations there.
	* config/cpu/mips/atomicity.h: Fix comments, remove
	#ifndef/#endif. Add push/pop mips2.

From-SVN: r55331
parent 0c3a2ea0
2002-07-08 Eric Christopher <echristo@redhat.com>
* configure.target: Fix comment for mips atomicity. Add
mips*-*-linux* target, enable atomic operations there.
* config/cpu/mips/atomicity.h: Fix comments, remove
#ifndef/#endif. Add push/pop mips2.
2002-07-08 Peter Schmid <schmid@snake.iap.physik.tu-darmstadt.de> 2002-07-08 Peter Schmid <schmid@snake.iap.physik.tu-darmstadt.de>
* include/bits/stl_deque.h (_Deque_alloc_base): Change order of * include/bits/stl_deque.h (_Deque_alloc_base): Change order of
......
// Low-level functions for atomic operations. MIPS II version. // Low-level functions for atomic operations.
// Copyright (C) 2001 Free Software Foundation, Inc. // Copyright (C) 2001, 2002 Free Software Foundation, Inc.
// //
// This file is part of the GNU ISO C++ Library. This library is free // This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the // software; you can redistribute it and/or modify it under the
...@@ -30,9 +30,6 @@ ...@@ -30,9 +30,6 @@
#ifndef _BITS_ATOMICITY_H #ifndef _BITS_ATOMICITY_H
#define _BITS_ATOMICITY_H 1 #define _BITS_ATOMICITY_H 1
// #include <sgidefs.h>
// #ifdef (_MIPS_ISA_MIPS2)
typedef int _Atomic_word; typedef int _Atomic_word;
static inline int static inline int
...@@ -44,9 +41,12 @@ __exchange_and_add (volatile _Atomic_word *__mem, int __val) ...@@ -44,9 +41,12 @@ __exchange_and_add (volatile _Atomic_word *__mem, int __val)
__asm__ __volatile__ __asm__ __volatile__
("/* Inline exchange & add */\n\t" ("/* Inline exchange & add */\n\t"
"1:\n\t" "1:\n\t"
".set push\n\t"
".set mips2\n\t"
"ll %0,%3\n\t" "ll %0,%3\n\t"
"addu %1,%4,%0\n\t" "addu %1,%4,%0\n\t"
"sc %1,%2\n\t" "sc %1,%2\n\t"
".set pop\n\t"
"beqz %1,1b\n\t" "beqz %1,1b\n\t"
"/* End exchange & add */" "/* End exchange & add */"
: "=&r"(__result), "=&r"(__tmp), "=m"(*__mem) : "=&r"(__result), "=&r"(__tmp), "=m"(*__mem)
...@@ -65,9 +65,12 @@ __atomic_add (volatile _Atomic_word *__mem, int __val) ...@@ -65,9 +65,12 @@ __atomic_add (volatile _Atomic_word *__mem, int __val)
__asm__ __volatile__ __asm__ __volatile__
("/* Inline atomic add */\n\t" ("/* Inline atomic add */\n\t"
"1:\n\t" "1:\n\t"
".set push\n\t"
".set mips2\n\t"
"ll %0,%2\n\t" "ll %0,%2\n\t"
"addu %0,%3,%0\n\t" "addu %0,%3,%0\n\t"
"sc %0,%1\n\t" "sc %0,%1\n\t"
".set pop\n\t"
"beqz %0,1b\n\t" "beqz %0,1b\n\t"
"/* End atomic add */" "/* End atomic add */"
: "=&r"(__result), "=m"(*__mem) : "=&r"(__result), "=m"(*__mem)
......
...@@ -77,8 +77,9 @@ case "${target_cpu}" in ...@@ -77,8 +77,9 @@ case "${target_cpu}" in
m68k | m680[246]0) m68k | m680[246]0)
cpu_include_dir="cpu/m68k" cpu_include_dir="cpu/m68k"
;; ;;
mips) mips*)
# This is only until the mips routines are fixed. # MIPS chips are unreliable as to sc/ll support. By default
# don't use atomic instructions and override for the OS.
cpu_include_dir="cpu/generic" cpu_include_dir="cpu/generic"
;; ;;
mmix) mmix)
...@@ -202,5 +203,7 @@ case "${target}" in ...@@ -202,5 +203,7 @@ case "${target}" in
alpha*-*-*osf5*) alpha*-*-*osf5*)
CPULIMITSH="os/osf/osf5.0" CPULIMITSH="os/osf/osf5.0"
;; ;;
mips*-*-linux*)
ATOMICITYH="cpu/mips"
;;
esac esac
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment