Add CCZmode.

From-SVN: r32777

gcc/ChangeLog

+2000-03-27  Richard Henderson  <rth@cygnus.com>
+
+	* i386-protos.h (ix86_match_ccmode): Declare.
+	* i386.c (ix86_match_ccmode): New.
+	(ix86_expand_fp_compare): Update for pattern renames.
+	(ix86_expand_strlensi_unroll_1): Likewise.
+	* i386.h (EXTRA_CC_MODES): Add CCZ.
+	(SELECT_CC_MODE): Use it for EQ/NE zero.
+	* i386.md (cmpsi_ccz_1): New.
+	(cmpqi_ccz_1): New.
+	(*testsi_ccz_1): New.
+	(testqi_ccz_1): New.
+	(cmpsi_ccno_1): Rename from cmpsi_0.
+	(testsi_ccno_1): Rename from testsi_1.
+	(testqi_ccno_1): Rename from testqi_1.
+	(*testqi_ext_ccz_0): Rename from testqi_ext_0.
+	(testqi_ext_ccno_0): Rename from *testqi_ext_1.
+	(*cmphi_0): Use ix86_match_ccmode.
+	(*cmpqi_ext_2, *addsi_2, *addhi_2, *addqi_2): Likewise.
+	(*subsi_2, *subhi_2, *subqi_2, *testhi_1): Likewise.
+	(*testqi_ext_1, *testqi_ext_2, *testqi_ext_3): Likewise.
+	(*andsi_2, *andhi_2, *andqi_2, *andqi_ext_0_cc): Likewise.
+	(*iorsi_2, *iorhi_2, *iorqi_2): Likewise.
+	(*xorsi_2, *xorhi_2, *xorqi_cc_1): Likewise.
+	(*one_cmplsi2_2, *one_cmplhi2_2, *one_cmplqi2_2): Likewise.
+	(*ashlsi3_cmpno, *ashlhi3_cmpno, *ashlqi3_cmpno): Likewise.
+	(*ashrsi3_cmpno, *ashrhi3_cmpno, *ashrqi3_cmpno): Likewise.
+	(*lshrsi3_cmpno, *lshrhi3_cmpno, *lshrqi3_cmpno): Likewise.
+	(appropriate peepholes): Likewise.
+	(*cmphi_1, *cmpqi_ccno_1, *cmpqi_1): Star out name.
+	(*subsi_3, *subhi_3, *subqi_3): Remove.
+	(*negdi2_1+1 splitter): Use CCZ for neg patterns.
+	(*negsi2_cmp, *neghi2_cmp, *negqi2_cmp): Remove.
+	(*negsi2_cmpz): Rename from *negsi2_cmpno, use CCZ.
+	(*neghi2_cmpz, *negqi2_cmpz): Similarly.
+	(x86_shift_adj_1): Use CCZ.
+	(*dbra_ge+1, *dbra_ge+2, ffssi2, ffssi_1): Likewise.
+
 2000-03-27  Stan Cox  <scox@cygnus.com>	
 
 	* resource.h (mark_resource_type): New.

gcc/config/i386/i386-protos.h

@@ -96,6 +96,7 @@ extern void ix86_expand_unary_operator PARAMS ((enum rtx_code, enum machine_mode
 					      rtx[]));
 extern int ix86_unary_operator_ok PARAMS ((enum rtx_code, enum machine_mode,
 					 rtx[]));
+extern int ix86_match_ccmode PARAMS ((rtx, enum machine_mode));
 extern void ix86_expand_branch PARAMS ((enum rtx_code, int, rtx));
 extern int ix86_expand_setcc PARAMS ((enum rtx_code, int, rtx));
 extern int ix86_expand_int_movcc PARAMS ((rtx[]));

gcc/config/i386/i386.c

@@ -1373,7 +1373,7 @@ memory_displacement_operand (op, mode)
   return parts.disp != NULL_RTX;
 }
 
-/* To avoid problems when jump re-emits comparisons like testqi_ext_0,
+/* To avoid problems when jump re-emits comparisons like testqi_ext_ccno_0,
    re-recognize the operand to avoid a copy_to_mode_reg that will fail.
 
    ??? It seems likely that this will only work because cmpsi is an
@@ -4252,6 +4252,45 @@ ix86_unary_operator_ok (code, mode, operands)
   return TRUE;
 }
 
+/* Return TRUE or FALSE depending on whether the first SET in INSN
+   has source and destination with matching CC modes, and that the
+   CC mode is at least as constrained as REQ_MODE.  */
+
+int
+ix86_match_ccmode (insn, req_mode)
+     rtx insn;
+     enum machine_mode req_mode;
+{
+  rtx set;
+  enum machine_mode set_mode;
+
+  set = PATTERN (insn);
+  if (GET_CODE (set) == PARALLEL)
+    set = XVECEXP (set, 0, 0);
+  if (GET_CODE (set) != SET)
+    abort ();
+
+  set_mode = GET_MODE (SET_DEST (set));
+  switch (set_mode)
+    {
+    case CCmode:
+      if (req_mode == CCNOmode)
+	return 0;
+      /* FALLTHRU */
+    case CCNOmode:
+      if (req_mode == CCZmode)
+	return 0;
+      /* FALLTHRU */
+    case CCZmode:
+      break;
+
+    default:
+      abort ();
+    }
+
+  return (GET_MODE (SET_SRC (set)) == set_mode);
+}
+
 /* Produce an unsigned comparison for a given signed comparison.  */
 
 static enum rtx_code
@@ -4455,7 +4494,7 @@ ix86_expand_fp_compare (code, op0, op1, unordered)
 		  abort ();
 		}
 
-	      emit_insn (gen_testqi_ext_0 (tmp, GEN_INT (mask)));
+	      emit_insn (gen_testqi_ext_ccno_0 (tmp, GEN_INT (mask)));
 	      intcmp_mode = CCNOmode;
 	    }
 	}
@@ -4470,7 +4509,7 @@ ix86_expand_fp_compare (code, op0, op1, unordered)
 	  switch (code)
 	    {
 	    case GT:
-	      emit_insn (gen_testqi_ext_0 (tmp, GEN_INT (0x45)));
+	      emit_insn (gen_testqi_ext_ccno_0 (tmp, GEN_INT (0x45)));
 	      code = EQ;
 	      break;
 	    case LT:
@@ -4480,7 +4519,7 @@ ix86_expand_fp_compare (code, op0, op1, unordered)
 	      code = EQ;
 	      break;
 	    case GE:
-	      emit_insn (gen_testqi_ext_0 (tmp, GEN_INT (0x05)));
+	      emit_insn (gen_testqi_ext_ccno_0 (tmp, GEN_INT (0x05)));
 	      code = EQ;
 	      break;
 	    case LE:
@@ -5490,7 +5529,8 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch)
   rtx align_4_label = gen_label_rtx ();
   rtx end_0_label = gen_label_rtx ();
   rtx mem;
-  rtx flags = gen_rtx_REG (CCNOmode, FLAGS_REG);
+  rtx no_flags = gen_rtx_REG (CCNOmode, FLAGS_REG);
+  rtx z_flags = gen_rtx_REG (CCNOmode, FLAGS_REG);
   rtx tmpreg = gen_reg_rtx (SImode);
 
   align = 0;
@@ -5512,25 +5552,25 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch)
 	  align_rtx = expand_binop (SImode, and_optab, scratch, GEN_INT (3),
 				    NULL_RTX, 0, OPTAB_WIDEN);
 
-	  emit_insn (gen_cmpsi_0 (align_rtx, const0_rtx));
+	  emit_insn (gen_cmpsi_ccz_1 (align_rtx, const0_rtx));
 
-	  tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx);
+	  tmp = gen_rtx_EQ (VOIDmode, z_flags, const0_rtx);
 	  tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 
 				      gen_rtx_LABEL_REF (VOIDmode,
 							 align_4_label),
 				      pc_rtx);
 	  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
 
-	  emit_insn (gen_cmpsi_1 (align_rtx, GEN_INT (2)));
+	  emit_insn (gen_cmpsi_ccno_1 (align_rtx, GEN_INT (2)));
 
-	  tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx);
+	  tmp = gen_rtx_EQ (VOIDmode, no_flags, const0_rtx);
 	  tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 
 				      gen_rtx_LABEL_REF (VOIDmode,
 							 align_2_label),
 				      pc_rtx);
 	  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
 
-	  tmp = gen_rtx_GTU (VOIDmode, flags, const0_rtx);
+	  tmp = gen_rtx_GTU (VOIDmode, no_flags, const0_rtx);
 	  tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 
 				      gen_rtx_LABEL_REF (VOIDmode,
 							 align_3_label),
@@ -5545,9 +5585,9 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch)
 	  align_rtx = expand_binop (SImode, and_optab, scratch, GEN_INT (2),
 				    NULL_RTX, 0, OPTAB_WIDEN);
 
-	  emit_insn (gen_cmpsi_0 (align_rtx, const0_rtx));
+	  emit_insn (gen_cmpsi_ccz_1 (align_rtx, const0_rtx));
 
-	  tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx);
+	  tmp = gen_rtx_EQ (VOIDmode, z_flags, const0_rtx);
 	  tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 
 				      gen_rtx_LABEL_REF (VOIDmode,
 							 align_4_label),
@@ -5560,9 +5600,9 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch)
       /* Now compare the bytes.  */
 
       /* Compare the first n unaligned byte on a byte per byte basis. */
-      emit_insn (gen_cmpqi_0 (mem, const0_rtx));
+      emit_insn (gen_cmpqi_ccz_1 (mem, const0_rtx));
 
-      tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx);
+      tmp = gen_rtx_EQ (VOIDmode, z_flags, const0_rtx);
       tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 
 				  gen_rtx_LABEL_REF (VOIDmode, end_0_label),
 				  pc_rtx);
@@ -5576,9 +5616,9 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch)
 	{
 	  emit_label (align_2_label);
 
-	  emit_insn (gen_cmpqi_0 (mem, const0_rtx));
+	  emit_insn (gen_cmpqi_ccz_1 (mem, const0_rtx));
 
-	  tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx);
+	  tmp = gen_rtx_EQ (VOIDmode, z_flags, const0_rtx);
 	  tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 
 				      gen_rtx_LABEL_REF (VOIDmode,
 							 end_0_label),
@@ -5590,9 +5630,9 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch)
 	  emit_label (align_3_label);
 	}
 
-      emit_insn (gen_cmpqi_0 (mem, const0_rtx));
+      emit_insn (gen_cmpqi_ccz_1 (mem, const0_rtx));
 
-      tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx);
+      tmp = gen_rtx_EQ (VOIDmode, z_flags, const0_rtx);
       tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 
 				  gen_rtx_LABEL_REF (VOIDmode, end_0_label),
 				  pc_rtx);
@@ -5626,7 +5666,7 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch)
        emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
 
        /* If zero is not in the first two bytes, move two bytes forward. */
-       emit_insn (gen_testsi_1 (tmpreg, GEN_INT (0x8080)));
+       emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
        tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
        tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
        emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
@@ -5650,7 +5690,7 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch)
        rtx end_2_label = gen_label_rtx ();
        /* Is zero in the first two bytes? */
 
-       emit_insn (gen_testsi_1 (tmpreg, GEN_INT (0x8080)));
+       emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
        tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
        tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
        tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,

gcc/config/i386/i386.h

@@ -2160,10 +2160,13 @@ while (0)
 
    Add CCNO to indicate No Overflow, which is often also includes
    No Carry.  This is typically used on the output of logicals,
-   and is only valid in comparisons against zero.  */
+   and is only valid in comparisons against zero.
+
+   Add CCZ to indicate that only the Zero flag is valid.  */
 
 #define EXTRA_CC_MODES \
 	CC(CCNOmode, "CCNO") \
+	CC(CCZmode, "CCZ") \
 	CC(CCFPmode, "CCFP") \
 	CC(CCFPUmode, "CCFPU")
 
@@ -2173,7 +2176,7 @@ while (0)
    For floating-point equality comparisons, CCFPEQmode should be used.
    VOIDmode should be used in all other cases.
 
-   For integer comparisons against zero, reduce to CCNOmode if
+   For integer comparisons against zero, reduce to CCNOmode or CCZmode if
    possible, to allow for more combinations.  */
 
 #define SELECT_CC_MODE(OP,X,Y)				\
@@ -2181,7 +2184,7 @@ while (0)
    ? (OP) == EQ || (OP) == NE ? CCFPUmode : CCFPmode	\
    : (OP) == LE || (OP) == GT ? CCmode			\
    : (Y) != const0_rtx ? CCmode				\
-   : CCNOmode)
+   : (OP) == EQ || (OP) == NE ? CCZmode : CCNOmode)
 
 /* Control the assembler format that we output, to the extent
    this does not vary between assemblers.  */

gcc/config/i386/i386.md

@@ -911,7 +911,17 @@
   DONE;
 }")
 
-(define_insn "cmpsi_0"
+(define_insn "cmpsi_ccz_1"
+  [(set (reg:CCZ 17)
+	(compare:CCZ (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
+		     (match_operand:SI 1 "const0_operand" "n,n")))]
+  ""
+  "@
+   test{l}\\t{%0, %0|%0, %0}
+   cmp{l}\\t{%1, %0|%0, %1}"
+  [(set_attr "type" "icmp")])
+
+(define_insn "cmpsi_ccno_1"
   [(set (reg:CCNO 17)
 	(compare:CCNO (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
 		      (match_operand:SI 1 "const0_operand" "n,n")))]
@@ -929,17 +939,17 @@
   "cmp{l}\\t{%1, %0|%0, %1}"
   [(set_attr "type" "icmp")])
 
-(define_insn "cmphi_0"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
-		      (match_operand:HI 1 "const0_operand" "n,n")))]
-  ""
+(define_insn "*cmphi_0"
+  [(set (reg 17)
+	(compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
+		 (match_operand:HI 1 "const0_operand" "n,n")))]
+  "ix86_match_ccmode (insn, CCNOmode)"
   "@
    test{w}\\t{%0, %0|%0, %0}
    cmp{w}\\t{%1, %0|%0, %1}"
   [(set_attr "type" "icmp")])
 
-(define_insn "cmphi_1"
+(define_insn "*cmphi_1"
   [(set (reg:CC 17)
 	(compare:CC (match_operand:HI 0 "nonimmediate_operand" "rm,r")
 		    (match_operand:HI 1 "general_operand" "ri,mr")))]
@@ -947,7 +957,17 @@
   "cmp{w}\\t{%1, %0|%0, %1}"
   [(set_attr "type" "icmp")])
 
-(define_insn "cmpqi_0"
+(define_insn "cmpqi_ccz_1"
+  [(set (reg:CCZ 17)
+	(compare:CCZ (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
+		     (match_operand:QI 1 "const0_operand" "n,n")))]
+  ""
+  "@
+   test{b}\\t{%0, %0|%0, %0}
+   cmp{b}\\t{$0, %0|%0, 0}"
+  [(set_attr "type" "icmp")])
+
+(define_insn "*cmpqi_ccno_1"
   [(set (reg:CCNO 17)
 	(compare:CCNO (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
 		      (match_operand:QI 1 "const0_operand" "n,n")))]
@@ -957,7 +977,7 @@
    cmp{b}\\t{$0, %0|%0, 0}"
   [(set_attr "type" "icmp")])
 
-(define_insn "cmpqi_1"
+(define_insn "*cmpqi_1"
   [(set (reg:CC 17)
 	(compare:CC (match_operand:QI 0 "nonimmediate_operand" "qm,q")
 		    (match_operand:QI 1 "general_operand" "qi,mq")))]
@@ -979,15 +999,15 @@
   [(set_attr "type" "icmp")])
 
 (define_insn "*cmpqi_ext_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (subreg:QI
 	    (zero_extract:SI
 	      (match_operand 0 "ext_register_operand" "q")
 	      (const_int 8)
 	      (const_int 8)) 0)
 	  (match_operand:QI 1 "const0_operand" "n")))]
-  ""
+  "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\\t%h0, %h0"
   [(set_attr "type" "icmp")])
 
@@ -3347,14 +3367,15 @@
   "")
 
 (define_insn "*addsi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
 		   (match_operand:SI 2 "general_operand" "rmni,rni"))
 	  (const_int 0)))			
    (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
 	(plus:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (PLUS, SImode, operands)
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (PLUS, SImode, operands)
    /* Current assemblers are broken and do not allow @GOTOFF in
       ought but a memory context. */
    && ! pic_symbolic_operand (operands[2], VOIDmode)"
@@ -3458,14 +3479,15 @@
 	(const_string "alu")))])
 
 (define_insn "*addhi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
 		   (match_operand:HI 2 "general_operand" "rmni,rni"))
 	  (const_int 0)))			
    (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
 	(plus:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (PLUS, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (PLUS, HImode, operands)"
   "*
 {
   switch (get_attr_type (insn))
@@ -3564,14 +3586,15 @@
 	(const_string "alu")))])
 
 (define_insn "*addqi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
 		   (match_operand:QI 2 "general_operand" "qmni,qni"))
 	  (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
 	(plus:QI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (PLUS, QImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (PLUS, QImode, operands)"
   "*
 {
   switch (get_attr_type (insn))
@@ -3784,26 +3807,15 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*subsi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
-	  (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
-		    (match_operand:SI 2 "general_operand" "ri,rm"))
-	  (const_int 0)))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(minus:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (MINUS, SImode, operands)"
-  "sub{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
-
-(define_insn "*subsi_3"
-  [(set (reg:CC 17)
-	(compare:CC
+  [(set (reg 17)
+	(compare
 	  (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
 		    (match_operand:SI 2 "general_operand" "ri,rm"))
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
 	(minus:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (MINUS, SImode, operands)"
+  "ix86_match_ccmode (insn, CCmode)
+   && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sub{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -3825,26 +3837,15 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*subhi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
-	  (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
-		    (match_operand:HI 2 "general_operand" "ri,rm"))
-	  (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
-	(minus:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (MINUS, HImode, operands)"
-  "sub{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
-
-(define_insn "*subhi_3"
-  [(set (reg:CC 17)
-	(compare:CC
+  [(set (reg 17)
+	(compare
 	  (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
 		    (match_operand:HI 2 "general_operand" "ri,rm"))
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
 	(minus:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (MINUS, HImode, operands)"
+  "ix86_match_ccmode (insn, CCmode)
+   && ix86_binary_operator_ok (MINUS, HImode, operands)"
   "sub{w}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -3866,26 +3867,15 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*subqi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
-	  (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
-		    (match_operand:QI 2 "general_operand" "qi,qm"))
-	  (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
-	(minus:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (MINUS, QImode, operands)"
-  "sub{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
-
-(define_insn "*subqi_3"
-  [(set (reg:CC 17)
-	(compare:CC
+  [(set (reg 17)
+	(compare
 	  (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
 		    (match_operand:QI 2 "general_operand" "qi,qm"))
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
 	(minus:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (MINUS, QImode, operands)"
+  "ix86_match_ccmode (insn, CCmode)
+   && ix86_binary_operator_ok (MINUS, QImode, operands)"
   "sub{b}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4301,27 +4291,50 @@
 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
 ;; Note that this excludes ah.
 
-(define_insn "testsi_1"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
-			      (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
-		      (const_int 0)))]
+(define_insn "*testsi_ccz_1"
+  [(set (reg:CCZ 17)
+	(compare:CCZ
+	  (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
+		  (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
+	  (const_int 0)))]
   ""
   "test{l}\\t{%1, %0|%0, %1}"
   [(set_attr "type" "icmp")
    (set_attr "pent_pair" "uv,np,uv")])
 
-(define_insn "*testhi_1"
+(define_insn "testsi_ccno_1"
   [(set (reg:CCNO 17)
-        (compare:CCNO (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
-			      (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
-		      (const_int 0)))]
+	(compare:CCNO
+	  (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
+		  (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
+	  (const_int 0)))]
   ""
+  "test{l}\\t{%1, %0|%0, %1}"
+  [(set_attr "type" "icmp")
+   (set_attr "pent_pair" "uv,np,uv")])
+
+(define_insn "*testhi_1"
+  [(set (reg 17)
+        (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
+			 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
+		 (const_int 0)))]
+  "ix86_match_ccmode (insn, CCNOmode)"
   "test{w}\\t{%1, %0|%0, %1}"
   [(set_attr "type" "icmp")
    (set_attr "pent_pair" "uv,np,uv")])
 
-(define_insn "testqi_1"
+(define_insn "testqi_ccz_1"
+  [(set (reg:CCZ 17)
+        (compare:CCZ
+	  (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm")
+		  (match_operand:QI 1 "nonmemory_operand" "n,n,qn"))
+	  (const_int 0)))]
+  ""
+  "test{b}\\t{%1, %0|%0, %1}"
+  [(set_attr "type" "icmp")
+   (set_attr "pent_pair" "uv,np,uv")])
+
+(define_insn "testqi_ccno_1"
   [(set (reg:CCNO 17)
         (compare:CCNO (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm")
 			      (match_operand:QI 1 "nonmemory_operand" "n,n,qn"))
@@ -4331,11 +4344,22 @@
   [(set_attr "type" "icmp")
    (set_attr "pent_pair" "uv,np,uv")])
 
-;; ??? A bug in recog prevents it from recognizing a const_int as an
-;; operand to zero_extend in andqi_ext_1.  It was checking explicitly
-;; for a QImode operand, which of course failed.
+(define_insn "*testqi_ext_ccz_0"
+  [(set (reg:CCZ 17)
+	(compare:CCZ
+	  (and:SI
+	    (zero_extract:SI
+	      (match_operand 0 "ext_register_operand" "q")
+	      (const_int 8)
+	      (const_int 8))
+	    (match_operand 1 "const_int_operand" "n"))
+	  (const_int 0)))]
+  "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff"
+  "test{b}\\t{%1, %h0|%h0, %1}"
+  [(set_attr "type" "icmp")
+   (set_attr "pent_pair" "np")])
 
-(define_insn "testqi_ext_0"
+(define_insn "testqi_ext_ccno_0"
   [(set (reg:CCNO 17)
 	(compare:CCNO
 	  (and:SI
@@ -4351,8 +4375,8 @@
    (set_attr "pent_pair" "np")])
 
 (define_insn "*testqi_ext_1"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (and:SI
 	    (zero_extract:SI
 	      (match_operand 0 "ext_register_operand" "q")
@@ -4361,13 +4385,13 @@
 	    (zero_extend:SI
 	      (match_operand:QI 1 "nonimmediate_operand" "qm")))
 	  (const_int 0)))]
-  ""
+  "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\\t{%1, %h0|%h0, %1}"
   [(set_attr "type" "icmp")])
 
 (define_insn "*testqi_ext_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (and:SI
 	    (zero_extract:SI
 	      (match_operand 0 "ext_register_operand" "q")
@@ -4378,31 +4402,32 @@
 	      (const_int 8)
 	      (const_int 8)))
 	  (const_int 0)))]
-  ""
+  "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\\t{%h1, %h0|%h0, %h1}"
   [(set_attr "type" "icmp")])
 
 ;; Combine likes to form bit extractions for some tests.  Humor it.
 (define_insn "*testqi_ext_3"
-  [(set (reg:CCNO 17)
-        (compare:CCNO (zero_extract:SI
-			(match_operand 0 "nonimmediate_operand" "rm")
-			(match_operand:SI 1 "const_int_operand" "")
-			(match_operand:SI 2 "const_int_operand" ""))
-		      (const_int 0)))]
-  "GET_MODE (operands[0]) == SImode
-   || GET_MODE (operands[0]) == HImode
-   || GET_MODE (operands[0]) == QImode"
+  [(set (reg 17)
+        (compare (zero_extract:SI
+		   (match_operand 0 "nonimmediate_operand" "rm")
+		   (match_operand:SI 1 "const_int_operand" "")
+		   (match_operand:SI 2 "const_int_operand" ""))
+		 (const_int 0)))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_MODE (operands[0]) == SImode
+       || GET_MODE (operands[0]) == HImode
+       || GET_MODE (operands[0]) == QImode)"
   "#")
 
 (define_split
-  [(set (reg:CCNO 17)
-        (compare:CCNO (zero_extract:SI
-			(match_operand 0 "nonimmediate_operand" "rm")
-			(match_operand:SI 1 "const_int_operand" "")
-			(match_operand:SI 2 "const_int_operand" ""))
-		      (const_int 0)))]
-  ""
+  [(set (reg 17)
+        (compare (zero_extract:SI
+		   (match_operand 0 "nonimmediate_operand" "rm")
+		   (match_operand:SI 1 "const_int_operand" "")
+		   (match_operand:SI 2 "const_int_operand" ""))
+		 (const_int 0)))]
+  "ix86_match_ccmode (insn, CCNOmode)"
   [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
   "
 {
@@ -4506,13 +4531,14 @@
   [(set_attr "type" "alu,alu,imovx")])
 
 (define_insn "*andsi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-			      (match_operand:SI 2 "general_operand" "rim,ri"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
+			 (match_operand:SI 2 "general_operand" "rim,ri"))
+		 (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
 	(and:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (AND, SImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (AND, SImode, operands)"
   "and{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4566,13 +4592,14 @@
   [(set_attr "type" "alu,alu,imovx")])
 
 (define_insn "*andhi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-			      (match_operand:HI 2 "general_operand" "rim,ri"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+			 (match_operand:HI 2 "general_operand" "rim,ri"))
+		 (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
 	(and:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (AND, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (AND, HImode, operands)"
   "and{w}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4598,14 +4625,15 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*andqi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and:QI
-			(match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
-			(match_operand:QI 2 "general_operand" "qim,qi,i"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (and:QI
+		   (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+		   (match_operand:QI 2 "general_operand" "qim,qi,i"))
+		 (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
 	(and:QI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (AND, QImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (AND, QImode, operands)"
   "@
    and{b}\\t{%2, %0|%0, %2}
    and{b}\\t{%2, %0|%0, %2}
@@ -4635,8 +4663,8 @@
 ;; often in fp comparisons.
 
 (define_insn "*andqi_ext_0_cc"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (and:SI
 	    (zero_extract:SI
 	      (match_operand 1 "ext_register_operand" "q")
@@ -4653,7 +4681,8 @@
 	    (const_int 8)
 	    (const_int 8))
 	  (match_dup 2)))]
-  "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
   "and{b}\\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4714,13 +4743,14 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*iorsi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-			      (match_operand:SI 2 "general_operand" "rim,ri"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
+			 (match_operand:SI 2 "general_operand" "rim,ri"))
+		 (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
 	(ior:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (IOR, SImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (IOR, SImode, operands)"
   "or{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4742,13 +4772,14 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*iorhi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-			      (match_operand:HI 2 "general_operand" "rim,ri"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+			 (match_operand:HI 2 "general_operand" "rim,ri"))
+		 (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
 	(ior:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (IOR, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (IOR, HImode, operands)"
   "or{w}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4774,13 +4805,14 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*iorqi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-			      (match_operand:QI 2 "general_operand" "qim,qi"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
+			 (match_operand:QI 2 "general_operand" "qim,qi"))
+		 (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
 	(ior:QI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (IOR, QImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (IOR, QImode, operands)"
   "or{b}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4807,13 +4839,14 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*xorsi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-			      (match_operand:SI 2 "general_operand" "rim,ri"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
+			 (match_operand:SI 2 "general_operand" "rim,ri"))
+		 (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
 	(xor:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (XOR, SImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (XOR, SImode, operands)"
   "xor{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4835,13 +4868,14 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*xorhi_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-			      (match_operand:HI 2 "general_operand" "rim,ri"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+			 (match_operand:HI 2 "general_operand" "rim,ri"))
+		 (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
 	(xor:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (XOR, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (XOR, HImode, operands)"
   "xor{w}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4867,14 +4901,15 @@
   [(set_attr "type" "alu")])
 
 (define_insn "*xorqi_cc_1"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
 		  (match_operand:QI 2 "general_operand" "qim,qi"))
 	  (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
 	(xor:QI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (XOR, QImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (XOR, QImode, operands)"
   "xor{b}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")])
 
@@ -4922,8 +4957,8 @@
    (clobber (reg:CC 17))]
   "reload_completed"
   [(parallel
-    [(set (reg:CCNO 17)
-	  (compare:CCNO (neg:SI (match_dup 2)) (const_int 0)))
+    [(set (reg:CCZ 17)
+	  (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
      (set (match_dup 0) (neg:SI (match_dup 2)))])
    (parallel
     [(set (match_dup 1)
@@ -4953,20 +4988,14 @@
   "neg{l}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn "*negsi2_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
-		 (const_int 0)))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(neg:SI (match_dup 1)))]
-  "ix86_unary_operator_ok (NEG, SImode, operands)"
-  "neg{l}\\t%0"
-  [(set_attr "type" "negnot")])
+;; The problem with neg is that it does not perform (compare x 0),
+;; it really performs (compare 0 x), which leaves us with the zero
+;; flag being the only useful item.
 
-(define_insn "*negsi2_cmp"
-  [(set (reg:CC 17)
-	(compare:CC (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
-		 (const_int 0)))
+(define_insn "*negsi2_cmpz"
+  [(set (reg:CCZ 17)
+	(compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
+		     (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(neg:SI (match_dup 1)))]
   "ix86_unary_operator_ok (NEG, SImode, operands)"
@@ -4988,20 +5017,10 @@
   "neg{w}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn "*neghi2_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
-		 (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-	(neg:HI (match_dup 1)))]
-  "ix86_unary_operator_ok (NEG, HImode, operands)"
-  "neg{w}\\t%0"
-  [(set_attr "type" "negnot")])
-
-(define_insn "*neghi2_cmp"
-  [(set (reg:CC 17)
-	(compare:CC (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
-		 (const_int 0)))
+(define_insn "*neghi2_cmpz"
+  [(set (reg:CCZ 17)
+	(compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
+		     (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
 	(neg:HI (match_dup 1)))]
   "ix86_unary_operator_ok (NEG, HImode, operands)"
@@ -5023,20 +5042,10 @@
   "neg{b}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn "*negqi2_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
-		 (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(neg:QI (match_dup 1)))]
-  "ix86_unary_operator_ok (NEG, QImode, operands)"
-  "neg{b}\\t%0"
-  [(set_attr "type" "negnot")])
-
-(define_insn "*negqi2_cmp"
-  [(set (reg:CC 17)
-	(compare:CC (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
-		 (const_int 0)))
+(define_insn "*negqi2_cmpz"
+  [(set (reg:CCZ 17)
+	(compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
+		     (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
 	(neg:QI (match_dup 1)))]
   "ix86_unary_operator_ok (NEG, QImode, operands)"
@@ -5416,22 +5425,23 @@
   [(set_attr "type" "negnot")])
 
 (define_insn "*one_cmplsi2_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
-		    (const_int 0)))
+  [(set (reg 17)
+	(compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
+		 (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(not:SI (match_dup 1)))]
-  "ix86_unary_operator_ok (NOT, SImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_unary_operator_ok (NOT, SImode, operands)"
   "#"
   [(set_attr "type" "alu1")])
 
 (define_split
-  [(set (reg:CCNO 17)
-	(compare:CCNO (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
+		 (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "")
 	(not:SI (match_dup 1)))]
-  ""
+  "ix86_match_ccmode (insn, CCNOmode)"
   [(parallel [(set (reg:CCNO 17)
 		   (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
 				 (const_int 0)))
@@ -5453,22 +5463,23 @@
   [(set_attr "type" "negnot")])
 
 (define_insn "*one_cmplhi2_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
+		 (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
 	(not:HI (match_dup 1)))]
-  "ix86_unary_operator_ok (NEG, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_unary_operator_ok (NEG, HImode, operands)"
   "#"
   [(set_attr "type" "alu1")])
 
 (define_split
-  [(set (reg:CCNO 17)
-	(compare:CCNO (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
+		 (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "")
 	(not:HI (match_dup 1)))]
-  ""
+  "ix86_match_ccmode (insn, CCNOmode)"
   [(parallel [(set (reg:CCNO 17)
 		   (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
 		      		 (const_int 0)))
@@ -5493,22 +5504,23 @@
   [(set_attr "type" "negnot")])
 
 (define_insn "*one_cmplqi2_2"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
-		    (const_int 0)))
+  [(set (reg 17)
+	(compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
+		 (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
 	(not:QI (match_dup 1)))]
-  "ix86_unary_operator_ok (NOT, QImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_unary_operator_ok (NOT, QImode, operands)"
   "#"
   [(set_attr "type" "alu1")])
 
 (define_split
-  [(set (reg:CCNO 17)
-	(compare:CCNO (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
+		 (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "")
 	(not:QI (match_dup 1)))]
-  ""
+  "ix86_match_ccmode (insn, CCNOmode)"
   [(parallel [(set (reg:CCNO 17)
 		   (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
 		      		 (const_int 0)))
@@ -5611,16 +5623,16 @@
    (set_attr "ppro_uops" "few")])
 
 (define_expand "x86_shift_adj_1"
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and:QI (match_operand:QI 2 "register_operand" "")
-			      (const_int 32))
-		      (const_int 0)))
+  [(set (reg:CCZ 17)
+	(compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
+			     (const_int 32))
+		     (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "")
-        (if_then_else:SI (ne (reg:CCNO 17) (const_int 0))
+        (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
 			 (match_operand:SI 1 "register_operand" "")
 			 (match_dup 0)))
    (set (match_dup 1)
-	(if_then_else:SI (ne (reg:CCNO 17) (const_int 0))
+	(if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
 			 (match_operand:SI 3 "register_operand" "r")
 			 (match_dup 1)))]
   "TARGET_CMOVE"
@@ -5636,9 +5648,9 @@
   rtx label = gen_label_rtx ();
   rtx tmp;
 
-  emit_insn (gen_testqi_1 (operands[2], GEN_INT (32)));
+  emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
 
-  tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
+  tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
   tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
   tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
 			      gen_rtx_LABEL_REF (VOIDmode, label),
@@ -5723,14 +5735,15 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*ashlsi3_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 		     (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(ashift:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
   "*
 {
   switch (get_attr_type (insn))
@@ -5799,14 +5812,15 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*ashlhi3_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
 		     (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
 	(ashift:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (ASHIFT, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
   "*
 {
   switch (get_attr_type (insn))
@@ -5889,14 +5903,15 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*ashlqi3_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 		     (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
 	(ashift:QI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (ASHIFT, QImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
   "*
 {
   switch (get_attr_type (insn))
@@ -6003,9 +6018,9 @@
   rtx label = gen_label_rtx ();
   rtx tmp;
 
-  emit_insn (gen_testqi_1 (operands[2], GEN_INT (32)));
+  emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
 
-  tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
+  tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
   tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
   tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
 			      gen_rtx_LABEL_REF (VOIDmode, label),
@@ -6058,14 +6073,15 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*ashrsi3_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 		       (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
   "@
    sar{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")])
@@ -6093,14 +6109,15 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*ashrhi3_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
 		       (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
 	(ashiftrt:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
   "@
    sar{w}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")])
@@ -6128,14 +6145,15 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*ashrqi3_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 		       (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
 	(ashiftrt:QI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
   "@
    sar{b}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")])
@@ -6220,14 +6238,15 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*lshrsi3_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 		       (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "@
    shr{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")])
@@ -6255,14 +6274,15 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*lshrhi3_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
 		       (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
 	(lshiftrt:HI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "@
    shr{w}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")])
@@ -6290,16 +6310,16 @@
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
 (define_insn "*lshrqi2_cmpno"
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 		       (match_operand:QI 2 "immediate_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
 	(lshiftrt:QI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
-  "@
-   shr{b}\\t{%2, %0|%0, %2}"
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
+  "shr{b}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")])
 
 ;; Rotate instructions
@@ -6930,11 +6950,11 @@
   "TARGET_USE_LOOP && reload_completed
    && ! (REGNO (operands[1]) == 2 && rtx_equal_p (operands[1], operands[2]))"
   [(set (match_dup 2) (match_dup 1))
-   (parallel [(set (reg:CCNO 17)
-		   (compare:CCNO (plus:SI (match_dup 2) (const_int -1))
+   (parallel [(set (reg:CCZ 17)
+		   (compare:CCZ (plus:SI (match_dup 2) (const_int -1))
 				 (const_int 0)))
 	      (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))])
-   (set (pc) (if_then_else (ne (reg:CCNO 17) (const_int 0))
+   (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
 			   (match_dup 0)
 			   (pc)))]
   "")
@@ -6952,12 +6972,12 @@
    (clobber (reg:CC 17))]
   "TARGET_USE_LOOP && reload_completed"
   [(set (match_dup 3) (match_dup 1))
-   (parallel [(set (reg:CCNO 17)
-		   (compare:CCNO (plus:SI (match_dup 3) (const_int -1))
-				 (const_int 0)))
+   (parallel [(set (reg:CCZ 17)
+		   (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
+				(const_int 0)))
 	      (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
    (set (match_dup 2) (match_dup 3))
-   (set (pc) (if_then_else (ne (reg:CCNO 17) (const_int 0))
+   (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
 			   (match_dup 0)
 			   (pc)))]
   "")
@@ -7333,7 +7353,7 @@
       emit_insn (gen_ffssi_1 (out, in));
       emit_insn (gen_rtx_SET (VOIDmode, out,
 		  gen_rtx_IF_THEN_ELSE (SImode, 
-		    gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG),
+		    gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
 				const0_rtx),
 		    tmp,
 		    out)));
@@ -7341,8 +7361,8 @@
       emit_move_insn (operands[0], out);
     }
 
-  /* Pentium bsf instruction is extremly slow.  Following code is recommended by
-     the Intel Optimizing Manual as resonable replacement:
+  /* Pentium bsf instruction is extremly slow.  The following code is
+     recommended by the Intel Optimizing Manual as a reasonable replacement:
            TEST    EAX,EAX
 	   JZ      SHORT BS2
 	   XOR     ECX,ECX
@@ -7382,7 +7402,7 @@
       emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
       emit_move_insn (out, hi);
       emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
-      emit_insn (gen_subsi3 (out, out, GEN_INT (0x3fe)));
+      emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
 
       emit_label (label);
       LABEL_NUSES (label) = 1;
@@ -7395,7 +7415,7 @@
       emit_insn (gen_ffssi_1 (out, in));
       emit_insn (gen_rtx_SET (VOIDmode, 
 		  gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
-		  gen_rtx_EQ (QImode, gen_rtx_REG (CCmode, FLAGS_REG),
+		  gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
 			      const0_rtx)));
       emit_insn (gen_negsi2 (tmp, tmp));
       emit_insn (gen_iorsi3 (out, out, tmp));
@@ -7405,12 +7425,10 @@
   DONE;  
 }")
 
-;; %%% The CCmode here is not strictly correct -- only Z is defined.
-;; But I don't think this can be used except for from above.
 (define_insn "ffssi_1"
-  [(set (reg:CC 17)
-        (compare:CC (match_operand:SI 1 "nonimmediate_operand" "rm")
-		    (const_int 0)))
+  [(set (reg:CCZ 17)
+        (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
+		     (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=r")
 	(unspec:SI [(match_dup 1)] 5))]
   ""
@@ -8950,13 +8968,14 @@
    GET_MODE (operands[3]) = SImode;")
 
 (define_split
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and (match_operand 1 "aligned_operand" "")
-			   (match_operand 2 "const_int_operand" ""))
-		      (const_int 0)))
+  [(set (reg 17)
+	(compare (and (match_operand 1 "aligned_operand" "")
+		      (match_operand 2 "const_int_operand" ""))
+		 (const_int 0)))
    (set (match_operand 0 "register_operand" "")
 	(and (match_dup 1) (match_dup 2)))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
+   && ix86_match_ccmode (insn, CCNOmode)
    && (GET_MODE (operands[0]) == HImode
        || (GET_MODE (operands[0]) == QImode 
 	   && (TARGET_PROMOTE_QImode || optimize_size)))"
@@ -8971,11 +8990,12 @@
    operands[1] = gen_lowpart (SImode, operands[1]);")
 
 (define_split
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and (match_operand 0 "aligned_operand" "")
-			   (match_operand 1 "const_int_operand" ""))
-		      (const_int 0)))]
+  [(set (reg 17)
+	(compare (and (match_operand 0 "aligned_operand" "")
+		      (match_operand 1 "const_int_operand" ""))
+		 (const_int 0)))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
+   && ix86_match_ccmode (insn, CCNOmode)
    && (GET_MODE (operands[0]) == HImode
        || (GET_MODE (operands[0]) == QImode 
 	   && (TARGET_PROMOTE_QImode || optimize_size)))"
@@ -9144,13 +9164,13 @@
 
 ;; Don't compare memory with zero, load and use a test instead.
 (define_peephole2
-  [(set (reg:CCNO 17)
-	(compare:CCNO (match_operand:SI 0 "memory_operand" "")
-	(const_int 0)))
+  [(set (reg 17)
+	(compare (match_operand:SI 0 "memory_operand" "")
+	         (const_int 0)))
    (match_scratch:SI 3 "r")]
-  "! optimize_size"
-   [(set (match_dup 3) (match_dup 0))
-    (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
+  "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
+  [(set (match_dup 3) (match_dup 0))
+   (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
   "")
 
 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer. 
@@ -9214,12 +9234,13 @@
 ;; versions if we're concerned about partial register stalls.
 
 (define_peephole2
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and:SI (match_operand:SI 0 "register_operand" "")
-			      (match_operand:SI 1 "immediate_operand" ""))
-		      (const_int 0)))]
-  "(true_regnum (operands[0]) != 0
-    || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
+  [(set (reg 17)
+	(compare (and:SI (match_operand:SI 0 "register_operand" "")
+			 (match_operand:SI 1 "immediate_operand" ""))
+		 (const_int 0)))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (true_regnum (operands[0]) != 0
+       || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
    && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
   [(parallel
      [(set (reg:CCNO 17)
@@ -9234,11 +9255,12 @@
 ;; on ! TARGET_PARTIAL_REG_STALL
 
 (define_peephole2
-  [(set (reg:CCNO 17)
-	(compare:CCNO (and:QI (match_operand:QI 0 "register_operand" "")
-			      (match_operand:QI 1 "immediate_operand" ""))
-		      (const_int 0)))]
+  [(set (reg 17)
+	(compare (and:QI (match_operand:QI 0 "register_operand" "")
+			 (match_operand:QI 1 "immediate_operand" ""))
+		 (const_int 0)))]
   "! TARGET_PARTIAL_REG_STALL
+   && ix86_match_ccmode (insn, CCNOmode)
    && true_regnum (operands[0]) != 0
    && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
   [(parallel
@@ -9251,8 +9273,8 @@
   "")
 
 (define_peephole2
-  [(set (reg:CCNO 17)
-	(compare:CCNO
+  [(set (reg 17)
+	(compare
 	  (and:SI
 	    (zero_extract:SI
 	      (match_operand 0 "ext_register_operand" "q")
@@ -9261,6 +9283,7 @@
 	    (match_operand 1 "const_int_operand" "n"))
 	  (const_int 0)))]
   "! TARGET_PARTIAL_REG_STALL
+   && ix86_match_ccmode (insn, CCNOmode)
    && true_regnum (operands[0]) != 0
    && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
   [(parallel [(set (reg:CCNO 17)