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riscv-gcc-1
Commit 14a082a3 by Kyrylo Tkachov Committed by Kyrylo Tkachov
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[ARM][4/7] Convert FP mnemonics to UAL | vcvt patterns 

	* config/arm/vfp.md (*extendsfdf2_vfp): Use UAL assembly syntax.
	(*truncdfsf2_vfp): Likewise.
	(*truncsisf2_vfp): Likewise.
	(*truncsidf2_vfp): Likewise.
	(fixuns_truncsfsi2): Likewise.
	(fixuns_truncdfsi2): Likewise.
	(*floatsisf2_vfp): Likewise.
	(*floatsidf2_vfp): Likewise.
	(floatunssisf2): Likewise.
	(floatunssidf2): Likewise.

	* gcc.target/arm/vfp-1.c: Updated expected assembly.

From-SVN: r215053
parent 14d9aa9f
Showing with 37 additions and 20 deletions
gcc/ChangeLog
2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/vfp.md (*extendsfdf2_vfp): Use UAL assembly syntax.
(*truncdfsf2_vfp): Likewise.
(*truncsisf2_vfp): Likewise.
(*truncsidf2_vfp): Likewise.
(fixuns_truncsfsi2): Likewise.
(fixuns_truncdfsi2): Likewise.
(*floatsisf2_vfp): Likewise.
(*floatsidf2_vfp): Likewise.
(floatunssisf2): Likewise.
(floatunssidf2): Likewise.
2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/vfp.md (*mulsf3_vfp): Use UAL assembly syntax.
(*muldf3_vfp): Likewise.
(*mulsf3negsf_vfp): Likewise.
gcc/config/arm/vfp.md
......@@ -953,7 +953,7 @@
[(set (match_operand:DF 0 "s_register_operand" "=w")
(float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fcvtds%?\\t%P0, %1"
"vcvt%?.f64.f32\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
......@@ -963,7 +963,7 @@
[(set (match_operand:SF 0 "s_register_operand" "=t")
(float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fcvtsd%?\\t%0, %P1"
"vcvt%?.f32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
......@@ -993,7 +993,7 @@
[(set (match_operand:SI 0 "s_register_operand" "=t")
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"ftosizs%?\\t%0, %1"
"vcvt%?.s32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
......@@ -1003,7 +1003,7 @@
[(set (match_operand:SI 0 "s_register_operand" "=t")
(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"ftosizd%?\\t%0, %P1"
"vcvt%?.s32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
......@@ -1014,7 +1014,7 @@
[(set (match_operand:SI 0 "s_register_operand" "=t")
(unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"ftouizs%?\\t%0, %1"
"vcvt%?.u32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
......@@ -1024,7 +1024,7 @@
[(set (match_operand:SI 0 "s_register_operand" "=t")
(unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"ftouizd%?\\t%0, %P1"
"vcvt%?.u32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
......@@ -1035,7 +1035,7 @@
[(set (match_operand:SF 0 "s_register_operand" "=t")
(float:SF (match_operand:SI 1 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fsitos%?\\t%0, %1"
"vcvt%?.f32.s32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
......@@ -1045,7 +1045,7 @@
[(set (match_operand:DF 0 "s_register_operand" "=w")
(float:DF (match_operand:SI 1 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fsitod%?\\t%P0, %1"
"vcvt%?.f64.s32\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
......@@ -1056,7 +1056,7 @@
[(set (match_operand:SF 0 "s_register_operand" "=t")
(unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fuitos%?\\t%0, %1"
"vcvt%?.f32.u32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
......@@ -1066,7 +1066,7 @@
[(set (match_operand:DF 0 "s_register_operand" "=w")
(unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fuitod%?\\t%P0, %1"
"vcvt%?.f64.u32\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
......
gcc/testsuite/ChangeLog
......@@ -8,6 +8,10 @@
2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/arm/vfp-1.c: Updated expected assembly.
2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/arm/pr51835.c: Update expected assembly.
* gcc.target/arm/vfp-1.c: Likewise.
* gcc.target/arm/vfp-ldmdbd.c: Likewise.
......
gcc/testsuite/gcc.target/arm/vfp-1.c
......@@ -94,34 +94,34 @@ volatile unsigned int u1;
void test_convert () {
/* extendsfdf2_vfp */
/* { dg-final { scan-assembler "fcvtds" } } */
/* { dg-final { scan-assembler "vcvt.f64.f32" } } */
d1 = f1;
/* truncdfsf2_vfp */
/* { dg-final { scan-assembler "fcvtsd" } } */
/* { dg-final { scan-assembler "vcvt.f32.f64" } } */
f1 = d1;
/* truncsisf2_vfp */
/* { dg-final { scan-assembler "ftosizs" } } */
/* { dg-final { scan-assembler "vcvt.s32.f32" } } */
i1 = f1;
/* truncsidf2_vfp */
/* { dg-final { scan-assembler "ftosizd" } } */
/* { dg-final { scan-assembler "vcvt.s32.f64" } } */
i1 = d1;
/* fixuns_truncsfsi2 */
/* { dg-final { scan-assembler "ftouizs" } } */
/* { dg-final { scan-assembler "vcvt.u32.f32" } } */
u1 = f1;
/* fixuns_truncdfsi2 */
/* { dg-final { scan-assembler "ftouizd" } } */
/* { dg-final { scan-assembler "vcvt.u32.f64" } } */
u1 = d1;
/* floatsisf2_vfp */
/* { dg-final { scan-assembler "fsitos" } } */
/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
f1 = i1;
/* floatsidf2_vfp */
/* { dg-final { scan-assembler "fsitod" } } */
/* { dg-final { scan-assembler "vcvt.f64.s32" } } */
d1 = i1;
/* floatunssisf2 */
/* { dg-final { scan-assembler "fuitos" } } */
/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
f1 = u1;
/* floatunssidf2 */
/* { dg-final { scan-assembler "fuitod" } } */
/* { dg-final { scan-assembler "vcvt.f64.u32" } } */
d1 = u1;
}
......
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