Skip to content

R
riscv-gcc-1
Commit 1472042a by Kazu Hirata Committed by Kazu Hirata
Options

h8300.md: Remove unnecessary parallels from all define_insn and define_split patterns. 

	* config/h8300/h8300.md: Remove unnecessary parallels from
	all define_insn and define_split patterns.

From-SVN: r77873
parent 24f29b06
Showing with 33 additions and 46 deletions
gcc/ChangeLog
2004-02-15 Kazu Hirata <kazu@cs.umass.edu> 2004-02-15 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.md: Remove unnecessary parallels from
all define_insn and define_split patterns.
2004-02-15 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.md: Remove explicit (set_attr "cc" * config/h8300/h8300.md: Remove explicit (set_attr "cc"
"clobber"). "clobber").
......
gcc/config/h8300/h8300.md
...@@ -121,30 +121,30 @@ ...@@ -121,30 +121,30 @@
;; movqi ;; movqi
(define_insn "pushqi1_h8300" (define_insn "pushqi1_h8300"
[(parallel [(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -2))) (plus:HI (reg:HI SP_REG) (const_int -2)))
(set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1))) (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
(match_operand:QI 0 "register_operand" "r"))])] (match_operand:QI 0 "register_operand" "r"))]
"TARGET_H8300 "TARGET_H8300
&& operands[0] != stack_pointer_rtx" && operands[0] != stack_pointer_rtx"
"mov.w\\t%T0,@-r7" "mov.w\\t%T0,@-r7"
[(set_attr "length" "2")]) [(set_attr "length" "2")])
(define_insn "pushqi1_h8300hs" (define_insn "pushqi1_h8300hs"
[(parallel [(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int -4))) (plus:SI (reg:SI SP_REG) (const_int -4)))
(set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3))) (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
(match_operand:QI 0 "register_operand" "r"))])] (match_operand:QI 0 "register_operand" "r"))]
"(TARGET_H8300H || TARGET_H8300S) "(TARGET_H8300H || TARGET_H8300S)
&& operands[0] != stack_pointer_rtx" && operands[0] != stack_pointer_rtx"
"mov.l\\t%S0,@-er7" "mov.l\\t%S0,@-er7"
[(set_attr "length" "4")]) [(set_attr "length" "4")])
(define_insn "pushqi1_h8300hs_normal" (define_insn "pushqi1_h8300hs_normal"
[(parallel [(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -4))) (plus:HI (reg:HI SP_REG) (const_int -4)))
(set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3))) (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
(match_operand:QI 0 "register_operand" "r"))])] (match_operand:QI 0 "register_operand" "r"))]
"(TARGET_H8300H || TARGET_H8300S) "(TARGET_H8300H || TARGET_H8300S)
&& operands[0] != stack_pointer_rtx" && operands[0] != stack_pointer_rtx"
"mov.l\\t%S0,@-er7" "mov.l\\t%S0,@-er7"
...@@ -236,20 +236,20 @@ ...@@ -236,20 +236,20 @@
"") "")
(define_insn "pushhi1_h8300hs" (define_insn "pushhi1_h8300hs"
[(parallel [(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int -4))) (plus:SI (reg:SI SP_REG) (const_int -4)))
(set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2))) (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
(match_operand:HI 0 "register_operand" "r"))])] (match_operand:HI 0 "register_operand" "r"))]
"(TARGET_H8300H || TARGET_H8300S) "(TARGET_H8300H || TARGET_H8300S)
&& operands[0] != stack_pointer_rtx" && operands[0] != stack_pointer_rtx"
"mov.l\\t%S0,@-er7" "mov.l\\t%S0,@-er7"
[(set_attr "length" "4")]) [(set_attr "length" "4")])
(define_insn "pushhi1_h8300hs_normal" (define_insn "pushhi1_h8300hs_normal"
[(parallel [(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -4))) (plus:HI (reg:HI SP_REG) (const_int -4)))
(set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2))) (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
(match_operand:HI 0 "register_operand" "r"))])] (match_operand:HI 0 "register_operand" "r"))]
"(TARGET_H8300H || TARGET_H8300S) "(TARGET_H8300H || TARGET_H8300S)
&& operands[0] != stack_pointer_rtx" && operands[0] != stack_pointer_rtx"
"mov.l\\t%S0,@-er7" "mov.l\\t%S0,@-er7"
...@@ -1879,13 +1879,12 @@ ...@@ -1879,13 +1879,12 @@
"") "")
(define_insn "stm_h8300s_2_advanced" (define_insn "stm_h8300s_2_advanced"
[(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int -8))) (plus:SI (reg:SI SP_REG) (const_int -8)))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
(match_operand:SI 0 "register_operand" "")) (match_operand:SI 0 "register_operand" ""))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
(match_operand:SI 1 "register_operand" ""))])] (match_operand:SI 1 "register_operand" ""))]
"TARGET_H8300S && !TARGET_NORMAL_MODE "TARGET_H8300S && !TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (2, operands)" && h8300_regs_ok_for_stm (2, operands)"
"stm.l\\t%S0-%S1,@-er7" "stm.l\\t%S0-%S1,@-er7"
...@@ -1893,13 +1892,12 @@ ...@@ -1893,13 +1892,12 @@
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "stm_h8300s_2_normal" (define_insn "stm_h8300s_2_normal"
[(parallel
[(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -8))) (plus:HI (reg:HI SP_REG) (const_int -8)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
(match_operand:SI 0 "register_operand" "")) (match_operand:SI 0 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
(match_operand:SI 1 "register_operand" ""))])] (match_operand:SI 1 "register_operand" ""))]
"TARGET_H8300S && TARGET_NORMAL_MODE "TARGET_H8300S && TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (2, operands)" && h8300_regs_ok_for_stm (2, operands)"
"stm.l\\t%S0-%S1,@-er7" "stm.l\\t%S0-%S1,@-er7"
...@@ -1921,7 +1919,6 @@ ...@@ -1921,7 +1919,6 @@
}") }")
(define_insn "stm_h8300s_3_advanced" (define_insn "stm_h8300s_3_advanced"
[(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int -12))) (plus:SI (reg:SI SP_REG) (const_int -12)))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
...@@ -1929,7 +1926,7 @@ ...@@ -1929,7 +1926,7 @@
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
(match_operand:SI 1 "register_operand" "")) (match_operand:SI 1 "register_operand" ""))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
(match_operand:SI 2 "register_operand" ""))])] (match_operand:SI 2 "register_operand" ""))]
"TARGET_H8300S && !TARGET_NORMAL_MODE "TARGET_H8300S && !TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (3, operands)" && h8300_regs_ok_for_stm (3, operands)"
"stm.l\\t%S0-%S2,@-er7" "stm.l\\t%S0-%S2,@-er7"
...@@ -1937,7 +1934,6 @@ ...@@ -1937,7 +1934,6 @@
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "stm_h8300s_3_normal" (define_insn "stm_h8300s_3_normal"
[(parallel
[(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -12))) (plus:HI (reg:HI SP_REG) (const_int -12)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
...@@ -1945,7 +1941,7 @@ ...@@ -1945,7 +1941,7 @@
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
(match_operand:SI 1 "register_operand" "")) (match_operand:SI 1 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
(match_operand:SI 2 "register_operand" ""))])] (match_operand:SI 2 "register_operand" ""))]
"TARGET_H8300S && TARGET_NORMAL_MODE "TARGET_H8300S && TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (3, operands)" && h8300_regs_ok_for_stm (3, operands)"
"stm.l\\t%S0-%S2,@-er7" "stm.l\\t%S0-%S2,@-er7"
...@@ -1970,7 +1966,6 @@ ...@@ -1970,7 +1966,6 @@
}") }")
(define_insn "stm_h8300s_4_advanced" (define_insn "stm_h8300s_4_advanced"
[(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int -16))) (plus:SI (reg:SI SP_REG) (const_int -16)))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
...@@ -1980,7 +1975,7 @@ ...@@ -1980,7 +1975,7 @@
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
(match_operand:SI 2 "register_operand" "")) (match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
(match_operand:SI 3 "register_operand" ""))])] (match_operand:SI 3 "register_operand" ""))]
"TARGET_H8300S && !TARGET_NORMAL_MODE "TARGET_H8300S && !TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (4, operands)" && h8300_regs_ok_for_stm (4, operands)"
"stm.l\\t%S0-%S3,@-er7" "stm.l\\t%S0-%S3,@-er7"
...@@ -1988,7 +1983,6 @@ ...@@ -1988,7 +1983,6 @@
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "stm_h8300s_4_normal" (define_insn "stm_h8300s_4_normal"
[(parallel
[(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -16))) (plus:HI (reg:HI SP_REG) (const_int -16)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
...@@ -1998,7 +1992,7 @@ ...@@ -1998,7 +1992,7 @@
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
(match_operand:SI 2 "register_operand" "")) (match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
(match_operand:SI 3 "register_operand" ""))])] (match_operand:SI 3 "register_operand" ""))]
"TARGET_H8300S && TARGET_NORMAL_MODE "TARGET_H8300S && TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (4, operands)" && h8300_regs_ok_for_stm (4, operands)"
"stm.l\\t%S0-%S3,@-er7" "stm.l\\t%S0-%S3,@-er7"
...@@ -2024,13 +2018,12 @@ ...@@ -2024,13 +2018,12 @@
}") }")
(define_insn "ldm_h8300s_2_advanced" (define_insn "ldm_h8300s_2_advanced"
[(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int 8))) (plus:SI (reg:SI SP_REG) (const_int 8)))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
(match_operand:SI 0 "register_operand" "")) (match_operand:SI 0 "register_operand" ""))
(set (mem:SI (reg:SI SP_REG)) (set (mem:SI (reg:SI SP_REG))
(match_operand:SI 1 "register_operand" ""))])] (match_operand:SI 1 "register_operand" ""))]
"TARGET_H8300S && !TARGET_NORMAL_MODE "TARGET_H8300S && !TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (2, operands)" && h8300_regs_ok_for_stm (2, operands)"
"ldm.l\\t@er7+,%S0-%S1" "ldm.l\\t@er7+,%S0-%S1"
...@@ -2038,13 +2031,12 @@ ...@@ -2038,13 +2031,12 @@
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "ldm_h8300s_2_normal" (define_insn "ldm_h8300s_2_normal"
[(parallel
[(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int 8))) (plus:HI (reg:HI SP_REG) (const_int 8)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
(match_operand:SI 0 "register_operand" "")) (match_operand:SI 0 "register_operand" ""))
(set (mem:SI (reg:HI SP_REG)) (set (mem:SI (reg:HI SP_REG))
(match_operand:SI 1 "register_operand" ""))])] (match_operand:SI 1 "register_operand" ""))]
"TARGET_H8300S && TARGET_NORMAL_MODE "TARGET_H8300S && TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (2, operands)" && h8300_regs_ok_for_stm (2, operands)"
"ldm.l\\t@er7+,%S0-%S1" "ldm.l\\t@er7+,%S0-%S1"
...@@ -2066,7 +2058,6 @@ ...@@ -2066,7 +2058,6 @@
}") }")
(define_insn "ldm_h8300s_3_advanced" (define_insn "ldm_h8300s_3_advanced"
[(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int 12))) (plus:SI (reg:SI SP_REG) (const_int 12)))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
...@@ -2074,7 +2065,7 @@ ...@@ -2074,7 +2065,7 @@
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
(match_operand:SI 1 "register_operand" "")) (match_operand:SI 1 "register_operand" ""))
(set (mem:SI (reg:SI SP_REG)) (set (mem:SI (reg:SI SP_REG))
(match_operand:SI 2 "register_operand" ""))])] (match_operand:SI 2 "register_operand" ""))]
"TARGET_H8300S && !TARGET_NORMAL_MODE "TARGET_H8300S && !TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (3, operands)" && h8300_regs_ok_for_stm (3, operands)"
"ldm.l\\t@er7+,%S0-%S2" "ldm.l\\t@er7+,%S0-%S2"
...@@ -2082,7 +2073,6 @@ ...@@ -2082,7 +2073,6 @@
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "ldm_h8300s_3_normal" (define_insn "ldm_h8300s_3_normal"
[(parallel
[(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int 12))) (plus:HI (reg:HI SP_REG) (const_int 12)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
...@@ -2090,7 +2080,7 @@ ...@@ -2090,7 +2080,7 @@
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
(match_operand:SI 1 "register_operand" "")) (match_operand:SI 1 "register_operand" ""))
(set (mem:SI (reg:HI SP_REG)) (set (mem:SI (reg:HI SP_REG))
(match_operand:SI 2 "register_operand" ""))])] (match_operand:SI 2 "register_operand" ""))]
"TARGET_H8300S && TARGET_NORMAL_MODE "TARGET_H8300S && TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (3, operands)" && h8300_regs_ok_for_stm (3, operands)"
"ldm.l\\t@er7+,%S0-%S2" "ldm.l\\t@er7+,%S0-%S2"
...@@ -2115,7 +2105,6 @@ ...@@ -2115,7 +2105,6 @@
}") }")
(define_insn "ldm_h8300s_4_advanced" (define_insn "ldm_h8300s_4_advanced"
[(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int 16))) (plus:SI (reg:SI SP_REG) (const_int 16)))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
...@@ -2125,7 +2114,7 @@ ...@@ -2125,7 +2114,7 @@
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
(match_operand:SI 2 "register_operand" "")) (match_operand:SI 2 "register_operand" ""))
(set (mem:SI (reg:SI SP_REG)) (set (mem:SI (reg:SI SP_REG))
(match_operand:SI 3 "register_operand" ""))])] (match_operand:SI 3 "register_operand" ""))]
"TARGET_H8300S && !TARGET_NORMAL_MODE "TARGET_H8300S && !TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (4, operands)" && h8300_regs_ok_for_stm (4, operands)"
"ldm.l\\t@er7+,%S0-%S3" "ldm.l\\t@er7+,%S0-%S3"
...@@ -2133,7 +2122,6 @@ ...@@ -2133,7 +2122,6 @@
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "ldm_h8300s_4_normal" (define_insn "ldm_h8300s_4_normal"
[(parallel
[(set (reg:HI SP_REG) [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int 16))) (plus:HI (reg:HI SP_REG) (const_int 16)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
...@@ -2143,7 +2131,7 @@ ...@@ -2143,7 +2131,7 @@
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4))) (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
(match_operand:SI 2 "register_operand" "")) (match_operand:SI 2 "register_operand" ""))
(set (mem:SI (reg:HI SP_REG)) (set (mem:SI (reg:HI SP_REG))
(match_operand:SI 3 "register_operand" ""))])] (match_operand:SI 3 "register_operand" ""))]
"TARGET_H8300S && !TARGET_NORMAL_MODE "TARGET_H8300S && !TARGET_NORMAL_MODE
&& h8300_regs_ok_for_stm (4, operands)" && h8300_regs_ok_for_stm (4, operands)"
"ldm.l\\t@er7+,%S0-%S3" "ldm.l\\t@er7+,%S0-%S3"
...@@ -2536,12 +2524,11 @@ ...@@ -2536,12 +2524,11 @@
;; the shift count dies, then we just use that register. ;; the shift count dies, then we just use that register.
(define_split (define_split
[(parallel
[(set (match_operand 0 "register_operand" "") [(set (match_operand 0 "register_operand" "")
(match_operator 2 "nshift_operator" (match_operator 2 "nshift_operator"
[(match_dup 0) [(match_dup 0)
(match_operand:QI 1 "register_operand" "")])) (match_operand:QI 1 "register_operand" "")]))
(clobber (match_operand:QI 3 "register_operand" ""))])] (clobber (match_operand:QI 3 "register_operand" ""))]
"flow2_completed "flow2_completed
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1]))" && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
[(set (cc0) [(set (cc0)
...@@ -2568,12 +2555,11 @@ ...@@ -2568,12 +2555,11 @@
operands[5] = gen_label_rtx ();") operands[5] = gen_label_rtx ();")
(define_split (define_split
[(parallel
[(set (match_operand 0 "register_operand" "") [(set (match_operand 0 "register_operand" "")
(match_operator 2 "nshift_operator" (match_operator 2 "nshift_operator"
[(match_dup 0) [(match_dup 0)
(match_operand:QI 1 "register_operand" "")])) (match_operand:QI 1 "register_operand" "")]))
(clobber (match_operand:QI 3 "register_operand" ""))])] (clobber (match_operand:QI 3 "register_operand" ""))]
"flow2_completed "flow2_completed
&& !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))" && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
[(set (match_dup 3) [(set (match_dup 3)
...@@ -3339,12 +3325,11 @@ ...@@ -3339,12 +3325,11 @@
"#") "#")
(define_split (define_split
[(parallel
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "") (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
(const_int 23)) (const_int 23))
(match_dup 0))) (match_dup 0)))
(clobber (match_operand:SI 2 "register_operand" ""))])] (clobber (match_operand:SI 2 "register_operand" ""))]
"(TARGET_H8300H || TARGET_H8300S) "(TARGET_H8300H || TARGET_H8300S)
&& flow2_completed && flow2_completed
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
...@@ -3360,12 +3345,11 @@ ...@@ -3360,12 +3345,11 @@
"operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));") "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
(define_split (define_split
[(parallel
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "") (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
(const_int 23)) (const_int 23))
(match_dup 0))) (match_dup 0)))
(clobber (match_operand:SI 2 "register_operand" ""))])] (clobber (match_operand:SI 2 "register_operand" ""))]
"(TARGET_H8300H || TARGET_H8300S) "(TARGET_H8300H || TARGET_H8300S)
&& flow2_completed && flow2_completed
&& !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
...@@ -3444,12 +3428,11 @@ ...@@ -3444,12 +3428,11 @@
"#") "#")
(define_split (define_split
[(parallel
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
(const_int 8388608)) (const_int 8388608))
(match_dup 0))) (match_dup 0)))
(clobber (match_operand:SI 2 "register_operand" ""))])] (clobber (match_operand:SI 2 "register_operand" ""))]
"(TARGET_H8300H || TARGET_H8300S) "(TARGET_H8300H || TARGET_H8300S)
&& flow2_completed && flow2_completed
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])) && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
...@@ -3465,12 +3448,11 @@ ...@@ -3465,12 +3448,11 @@
"operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));") "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
(define_split (define_split
[(parallel
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
(const_int 8388608)) (const_int 8388608))
(match_dup 0))) (match_dup 0)))
(clobber (match_operand:SI 2 "register_operand" ""))])] (clobber (match_operand:SI 2 "register_operand" ""))]
"(TARGET_H8300H || TARGET_H8300S) "(TARGET_H8300H || TARGET_H8300S)
&& flow2_completed && flow2_completed
&& !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment