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riscv-gcc-1
Commit 13da91fd by Richard Henderson Committed by Richard Henderson
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ia64.h (enum reg_class): Remove FR_INT_REGS, FR_FP_REGS, GR_AND_FR_INT_REGS, GR_AND_FR_FP_REGS. 

        * config/ia64/ia64.h (enum reg_class): Remove FR_INT_REGS, FR_FP_REGS,
        GR_AND_FR_INT_REGS, GR_AND_FR_FP_REGS.
        (REG_CLASS_NAMES): Likewise.
        (REG_CLASS_CONTENTS): Likewise.
        (FR_FP_REGNO_P, FR_INT_REGNO_P): Remove.
        (HARD_REGNO_MODE_OK): Remove references to them.
        (REGNO_REG_CLASS): Likewise.
        (REG_CLASS_FROM_LETTER): Likewise.
        (CLASS_MAX_NREGS): Likewise.
        (REGISTER_MOVE_COST): Likewise.
        * config/ia64/ia64.c (ia64_secondary_reload_class): Likewise.
        * config/ia64/ia64.md (*): Replace "e" constraints with "f".
        (movqi_internal): Special case moves from zero.
        (movhi_internal, movsi_internal): Likewise.
        (movdi_internal): Likewise.  Fill out "f" constraints.
        (movsf_internal): Fill out "r" constraints.
        (movdf_internal): Likewise.

From-SVN: r34530
parent ef384380
Showing with 119 additions and 161 deletions
gcc/ChangeLog
2000-06-13 Richard Henderson <rth@cygnus.com> 2000-06-13 Richard Henderson <rth@cygnus.com>
* config/ia64/ia64.h (enum reg_class): Remove FR_INT_REGS, FR_FP_REGS,
GR_AND_FR_INT_REGS, GR_AND_FR_FP_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(FR_FP_REGNO_P, FR_INT_REGNO_P): Remove.
(HARD_REGNO_MODE_OK): Remove references to them.
(REGNO_REG_CLASS): Likewise.
(REG_CLASS_FROM_LETTER): Likewise.
(CLASS_MAX_NREGS): Likewise.
(REGISTER_MOVE_COST): Likewise.
* config/ia64/ia64.c (ia64_secondary_reload_class): Likewise.
* config/ia64/ia64.md (*): Replace "e" constraints with "f".
(movqi_internal): Special case moves from zero.
(movhi_internal, movsi_internal): Likewise.
(movdi_internal): Likewise. Fill out "f" constraints.
(movsf_internal): Fill out "r" constraints.
(movdf_internal): Likewise.
2000-06-13 Richard Henderson <rth@cygnus.com>
* flow.c (insn_dead_p): Keep sets to PIC_OFFSET_TABLE_REGNUM * flow.c (insn_dead_p): Keep sets to PIC_OFFSET_TABLE_REGNUM
alive before reload. alive before reload.
......
gcc/config/ia64/ia64.c
...@@ -1969,7 +1969,7 @@ ia64_secondary_reload_class (class, mode, x) ...@@ -1969,7 +1969,7 @@ ia64_secondary_reload_class (class, mode, x)
because paradoxical subregs are not accepted by register_operand when because paradoxical subregs are not accepted by register_operand when
INSN_SCHEDULING is defined. Or alternatively, stop the paradoxical subreg INSN_SCHEDULING is defined. Or alternatively, stop the paradoxical subreg
stupidity in the *_operand functions in recog.c. */ stupidity in the *_operand functions in recog.c. */
if ((class == FR_REGS || class == FR_INT_REGS || class == FR_FP_REGS) if (class == FR_REGS
&& GET_CODE (x) == MEM && GET_CODE (x) == MEM
&& (GET_MODE (x) == SImode || GET_MODE (x) == HImode && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
|| GET_MODE (x) == QImode)) || GET_MODE (x) == QImode))
...@@ -1978,15 +1978,7 @@ ia64_secondary_reload_class (class, mode, x) ...@@ -1978,15 +1978,7 @@ ia64_secondary_reload_class (class, mode, x)
/* This can happen because of the ior/and/etc patterns that accept FP /* This can happen because of the ior/and/etc patterns that accept FP
registers as operands. If the third operand is a constant, then it registers as operands. If the third operand is a constant, then it
needs to be reloaded into a FP register. */ needs to be reloaded into a FP register. */
if ((class == FR_REGS || class == FR_INT_REGS || class == FR_FP_REGS) if (class == FR_REGS && GET_CODE (x) == CONST_INT)
&& GET_CODE (x) == CONST_INT)
return GR_REGS;
/* Moving a integer from an FP register to memory requires a general register
as an intermediary. This is not necessary if we are moving a DImode
subreg of a DFmode value from an FP register to memory, since stfd will
do the right thing in this case. */
if (class == FR_INT_REGS && GET_CODE (x) == MEM && GET_MODE (x) == DImode)
return GR_REGS; return GR_REGS;
/* ??? This happens if we cse/gcse a CCmode value across a call, and the /* ??? This happens if we cse/gcse a CCmode value across a call, and the
......
gcc/config/ia64/ia64.h
...@@ -545,10 +545,6 @@ while (0) ...@@ -545,10 +545,6 @@ while (0)
/* Ranges for the various kinds of registers. */ /* Ranges for the various kinds of registers. */
#define ADDL_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 3) #define ADDL_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 3)
#define GR_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 127) #define GR_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 127)
#define FR_FP_REGNO_P(REGNO) \
(((REGNO) >= 128 && (REGNO) <= 143) || ((REGNO) >= 152 && (REGNO) <= 223))
#define FR_INT_REGNO_P(REGNO) \
(((REGNO) >= 144 && (REGNO) <= 151) || ((REGNO) >= 224 && (REGNO) <= 255))
#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255) #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319) #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327) #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
...@@ -816,10 +812,7 @@ while (0) ...@@ -816,10 +812,7 @@ while (0)
that one). */ that one). */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \ #define HARD_REGNO_MODE_OK(REGNO, MODE) \
(FR_FP_REGNO_P (REGNO) ? ! INTEGRAL_MODE_P (MODE) \ (PR_REGNO_P (REGNO) ? (MODE) == CCmode : 1)
: FR_INT_REGNO_P (REGNO) ? ! FLOAT_MODE_P (MODE) \
: PR_REGNO_P (REGNO) ? (MODE) == CCmode \
: 1)
/* A C expression that is nonzero if it is desirable to choose register /* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1 allocation so as to avoid move instructions between a value of mode MODE1
...@@ -861,11 +854,6 @@ while (0) ...@@ -861,11 +854,6 @@ while (0)
register class, followed by one more enumeral value, `LIM_REG_CLASSES', register class, followed by one more enumeral value, `LIM_REG_CLASSES',
which is not a register class but rather tells how many classes there which is not a register class but rather tells how many classes there
are. */ are. */
/* ??? FP registers hold INT and FP values in different representations, so
we can't just use a subreg to convert between the two. We get around this
problem by segmenting the FP register set into two parts. One part (FR_INT)
only holds integer values, and one part (FR_FP) only hold FP values. Thus
we always know which representation is being used. */
/* ??? When compiling without optimization, it is possible for the only use of /* ??? When compiling without optimization, it is possible for the only use of
a pseudo to be a parameter load from the stack with a REG_EQUIV note. a pseudo to be a parameter load from the stack with a REG_EQUIV note.
Regclass handles this case specially and does not assign any costs to the Regclass handles this case specially and does not assign any costs to the
...@@ -879,11 +867,7 @@ enum reg_class ...@@ -879,11 +867,7 @@ enum reg_class
BR_REGS, BR_REGS,
ADDL_REGS, ADDL_REGS,
GR_REGS, GR_REGS,
FR_INT_REGS,
FR_FP_REGS,
FR_REGS, FR_REGS,
GR_AND_FR_INT_REGS,
GR_AND_FR_FP_REGS,
GR_AND_FR_REGS, GR_AND_FR_REGS,
ALL_REGS, ALL_REGS,
LIM_REG_CLASSES LIM_REG_CLASSES
...@@ -897,9 +881,8 @@ enum reg_class ...@@ -897,9 +881,8 @@ enum reg_class
/* An initializer containing the names of the register classes as C string /* An initializer containing the names of the register classes as C string
constants. These names are used in writing some of the debugging dumps. */ constants. These names are used in writing some of the debugging dumps. */
#define REG_CLASS_NAMES \ #define REG_CLASS_NAMES \
{ "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", "FR_INT_REGS", \ { "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", \
"FR_FP_REGS", "FR_REGS", "GR_AND_FR_INT_REGS", "GR_AND_FR_FP_REGS", \ "FR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
"GR_AND_FR_REGS", "ALL_REGS" }
/* An initializer containing the contents of the register classes, as integers /* An initializer containing the contents of the register classes, as integers
which are bit masks. The Nth integer specifies the contents of class N. which are bit masks. The Nth integer specifies the contents of class N.
...@@ -927,26 +910,10 @@ enum reg_class ...@@ -927,26 +910,10 @@ enum reg_class
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x300 }, \ 0x00000000, 0x00000000, 0x300 }, \
/* FR_INT_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00FF0000, 0x00000000, 0x00000000, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x000 }, \
/* FR_FP_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0xFF00FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, \
0x00000000, 0x00000000, 0x000 }, \
/* FR_REGS. */ \ /* FR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x000 }, \ 0x00000000, 0x00000000, 0x000 }, \
/* GR_AND_FR_INT_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00FF0000, 0x00000000, 0x00000000, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x300 }, \
/* GR_AND_FR_FP_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFF00FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, \
0x00000000, 0x00000000, 0x300 }, \
/* GR_AND_FR_REGS. */ \ /* GR_AND_FR_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
...@@ -966,8 +933,7 @@ enum reg_class ...@@ -966,8 +933,7 @@ enum reg_class
#define REGNO_REG_CLASS(REGNO) \ #define REGNO_REG_CLASS(REGNO) \
(ADDL_REGNO_P (REGNO) ? ADDL_REGS \ (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
: GENERAL_REGNO_P (REGNO) ? GR_REGS \ : GENERAL_REGNO_P (REGNO) ? GR_REGS \
: FR_FP_REGNO_P (REGNO) ? FR_FP_REGS \ : FR_REGNO_P (REGNO) ? FR_REGS \
: FR_INT_REGNO_P (REGNO) ? FR_INT_REGS \
: PR_REGNO_P (REGNO) ? PR_REGS \ : PR_REGNO_P (REGNO) ? PR_REGS \
: BR_REGNO_P (REGNO) ? BR_REGS \ : BR_REGNO_P (REGNO) ? BR_REGS \
: NO_REGS) : NO_REGS)
...@@ -990,8 +956,7 @@ enum reg_class ...@@ -990,8 +956,7 @@ enum reg_class
will not be passed to this macro; you do not need to handle it. */ will not be passed to this macro; you do not need to handle it. */
#define REG_CLASS_FROM_LETTER(CHAR) \ #define REG_CLASS_FROM_LETTER(CHAR) \
((CHAR) == 'f' ? FR_FP_REGS \ ((CHAR) == 'f' ? FR_REGS \
: (CHAR) == 'e' ? FR_INT_REGS \
: (CHAR) == 'a' ? ADDL_REGS \ : (CHAR) == 'a' ? ADDL_REGS \
: (CHAR) == 'b' ? BR_REGS \ : (CHAR) == 'b' ? BR_REGS \
: (CHAR) == 'c' ? PR_REGS \ : (CHAR) == 'c' ? PR_REGS \
...@@ -1042,8 +1007,7 @@ enum reg_class ...@@ -1042,8 +1007,7 @@ enum reg_class
#define CLASS_MAX_NREGS(CLASS, MODE) \ #define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == CCmode && (CLASS) == PR_REGS ? 2 \ ((MODE) == CCmode && (CLASS) == PR_REGS ? 2 \
: (((CLASS) == FR_REGS || (CLASS) == FR_FP_REGS \ : ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
|| (CLASS) == FR_INT_REGS) && (MODE) == XFmode) ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* If defined, gives a class of registers that cannot be used as the /* If defined, gives a class of registers that cannot be used as the
...@@ -1160,6 +1124,7 @@ enum reg_class ...@@ -1160,6 +1124,7 @@ enum reg_class
or a `MEM' representing a location in the stack. This enables DWARF2 or a `MEM' representing a location in the stack. This enables DWARF2
unwind info for C++ EH. */ unwind info for C++ EH. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0)) #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
/* ??? This is not defined because of three problems. /* ??? This is not defined because of three problems.
1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte. 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
...@@ -1925,8 +1890,6 @@ do { \ ...@@ -1925,8 +1890,6 @@ do { \
((FROM) == BR_REGS && (TO) == BR_REGS ? 8 \ ((FROM) == BR_REGS && (TO) == BR_REGS ? 8 \
: (((FROM) == BR_REGS && (TO) != GENERAL_REGS) \ : (((FROM) == BR_REGS && (TO) != GENERAL_REGS) \
|| ((TO) == BR_REGS && (FROM) != GENERAL_REGS)) ? 6 \ || ((TO) == BR_REGS && (FROM) != GENERAL_REGS)) ? 6 \
: (((FROM) == FR_FP_REGS && (TO) == FR_INT_REGS) \
|| ((FROM) == FR_INT_REGS && (TO) == FR_FP_REGS)) ? 4 \
: 2) : 2)
/* A C expression for the cost of moving data of mode M between a register and /* A C expression for the cost of moving data of mode M between a register and
......
gcc/config/ia64/ia64.md
...@@ -177,18 +177,19 @@ ...@@ -177,18 +177,19 @@
}") }")
(define_insn "*movqi_internal" (define_insn "*movqi_internal"
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m,r,*e") [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f")
(match_operand:QI 1 "move_operand" "r,J,m,r,*e,r"))] (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"! memory_operand (operands[0], QImode) "! memory_operand (operands[0], QImode)
|| ! memory_operand (operands[1], QImode)" || ! memory_operand (operands[1], QImode)"
"@ "@
mov %0 = %1 mov %0 = %r1
addl %0 = %1, r0 addl %0 = %1, r0
ld1%O1 %0 = %1%P1 ld1%O1 %0 = %1%P1
st1%Q0 %0 = %1%P0 st1%Q0 %0 = %r1%P0
getf.sig %0 = %1 getf.sig %0 = %1
setf.sig %0 = %1" setf.sig %0 = %r1
[(set_attr "type" "A,A,M,M,M,M")]) mov %0 = %1"
[(set_attr "type" "A,A,M,M,M,M,F")])
(define_expand "movhi" (define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "") [(set (match_operand:HI 0 "general_operand" "")
...@@ -203,18 +204,19 @@ ...@@ -203,18 +204,19 @@
}") }")
(define_insn "*movhi_internal" (define_insn "*movhi_internal"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r,*e") [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f")
(match_operand:HI 1 "move_operand" "r,J,m,r,*e,r"))] (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"! memory_operand (operands[0], HImode) "! memory_operand (operands[0], HImode)
|| !memory_operand (operands[1], HImode)" || !memory_operand (operands[1], HImode)"
"@ "@
mov %0 = %1 mov %0 = %r1
addl %0 = %1, r0 addl %0 = %1, r0
ld2%O1 %0 = %1%P1 ld2%O1 %0 = %1%P1
st2%Q0 %0 = %1%P0 st2%Q0 %0 = %r1%P0
getf.sig %0 = %1 getf.sig %0 = %1
setf.sig %0 = %1" setf.sig %0 = %r1
[(set_attr "type" "A,A,M,M,M,M")]) mov %0 = %1"
[(set_attr "type" "A,A,M,M,M,M,F")])
(define_expand "movsi" (define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "") [(set (match_operand:SI 0 "general_operand" "")
...@@ -229,22 +231,20 @@ ...@@ -229,22 +231,20 @@
}") }")
(define_insn "*movsi_internal" (define_insn "*movsi_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,r,*e,*e,r,*f") [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f")
(match_operand:SI 1 "move_operand" "r,J,i,m,r,*e,r,*e,*f,r"))] (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f"))]
"! memory_operand (operands[0], SImode) "! memory_operand (operands[0], SImode)
|| ! memory_operand (operands[1], SImode)" || ! memory_operand (operands[1], SImode)"
"@ "@
mov %0 = %1 mov %0 = %r1
addl %0 = %1, r0 addl %0 = %1, r0
movl %0 = %1 movl %0 = %1
ld4%O1 %0 = %1%P1 ld4%O1 %0 = %1%P1
st4%Q0 %0 = %1%P0 st4%Q0 %0 = %r1%P0
getf.sig %0 = %1 getf.sig %0 = %1
setf.sig %0 = %1 setf.sig %0 = %r1
mov %0 = %1 mov %0 = %1"
getf.s %0 = %1 [(set_attr "type" "A,A,L,M,M,M,M,F")])
setf.s %0 = %1"
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M")])
(define_expand "movdi" (define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "") [(set (match_operand:DI 0 "general_operand" "")
...@@ -287,25 +287,24 @@ ...@@ -287,25 +287,24 @@
operands[1] = copy_to_mode_reg (DImode, operands[1]); operands[1] = copy_to_mode_reg (DImode, operands[1]);
}") }")
;; ??? Emit stf8 for m/*e constraint.
(define_insn "*movdi_internal" (define_insn "*movdi_internal"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,r,*e,*e,r,*f,r,*b") [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f,*f, m, r,*b")
(match_operand:DI 1 "move_operand" "r,J,i,m,r,*e,r,*e,*f,r,*b,r"))] (match_operand:DI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f, m,*f,*b,rO"))]
"! memory_operand (operands[0], DImode) "! memory_operand (operands[0], DImode)
|| ! memory_operand (operands[1], DImode)" || ! memory_operand (operands[1], DImode)"
"@ "@
mov %0 = %1 mov %0 = %r1
addl %0 = %1, r0 addl %0 = %1, r0
movl %0 = %1 movl %0 = %1
ld8%O1 %0 = %1%P1 ld8%O1 %0 = %1%P1
st8%Q0 %0 = %1%P0 st8%Q0 %0 = %r1%P0
getf.sig %0 = %1 getf.sig %0 = %1
setf.sig %0 = %1 setf.sig %0 = %r1
mov %0 = %1 mov %0 = %1
getf.d %0 = %1 ldf8%O1 %0 = %1%P1
setf.d %0 = %1 stf8%Q0 %0 = %1%P0
mov %0 = %1 mov %0 = %1
mov %0 = %1" mov %0 = %r1"
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I")]) [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I")])
(define_expand "load_fptr" (define_expand "load_fptr"
...@@ -392,12 +391,9 @@ ...@@ -392,12 +391,9 @@
operands[1] = copy_to_mode_reg (SFmode, operands[1]); operands[1] = copy_to_mode_reg (SFmode, operands[1]);
}") }")
;; ??? The r/m alternative is apparently needed because of paradoxical subregs,
;; so it may no longer be necessary after scheduling is enabled.
(define_insn "*movsf_internal" (define_insn "*movsf_internal"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,*r,f,*r,*r") [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
(match_operand:SF 1 "general_operand" "fG,m,fG,fG,*r,*r,m"))] (match_operand:SF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
"! memory_operand (operands[0], SFmode) "! memory_operand (operands[0], SFmode)
|| ! memory_operand (operands[1], SFmode)" || ! memory_operand (operands[1], SFmode)"
"@ "@
...@@ -407,8 +403,9 @@ ...@@ -407,8 +403,9 @@
getf.s %0 = %F1 getf.s %0 = %F1
setf.s %0 = %1 setf.s %0 = %1
mov %0 = %1 mov %0 = %1
ld4%O1 %0 = %1" ld4%O1 %0 = %1%P1
[(set_attr "type" "F,M,M,M,M,A,M")]) st4%Q0 %0 = %1%P0"
[(set_attr "type" "F,M,M,M,M,A,M,M")])
(define_expand "movdf" (define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "") [(set (match_operand:DF 0 "general_operand" "")
...@@ -422,11 +419,9 @@ ...@@ -422,11 +419,9 @@
operands[1] = copy_to_mode_reg (DFmode, operands[1]); operands[1] = copy_to_mode_reg (DFmode, operands[1]);
}") }")
;; ??? movsf has a r/m alternative, movdf doesn't.
(define_insn "*movdf_internal" (define_insn "*movdf_internal"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,*r,f,*r") [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
(match_operand:DF 1 "general_operand" "fG,m,fG,fG,*r,*r"))] (match_operand:DF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
"! memory_operand (operands[0], DFmode) "! memory_operand (operands[0], DFmode)
|| ! memory_operand (operands[1], DFmode)" || ! memory_operand (operands[1], DFmode)"
"@ "@
...@@ -435,8 +430,10 @@ ...@@ -435,8 +430,10 @@
stfd %0 = %F1%P0 stfd %0 = %F1%P0
getf.d %0 = %F1 getf.d %0 = %F1
setf.d %0 = %1 setf.d %0 = %1
mov %0 = %1" mov %0 = %1
[(set_attr "type" "F,M,M,M,M,A")]) ld8%O1 %0 = %1%P1
st8%Q0 %0 = %1%P0"
[(set_attr "type" "F,M,M,M,M,A,M,M")])
(define_expand "movxf" (define_expand "movxf"
[(set (match_operand:XF 0 "general_operand" "") [(set (match_operand:XF 0 "general_operand" "")
...@@ -451,7 +448,7 @@ ...@@ -451,7 +448,7 @@
}") }")
(define_insn "*movxf_internal" (define_insn "*movxf_internal"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,m") [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f, m")
(match_operand:XF 1 "general_operand" "fG,m,fG"))] (match_operand:XF 1 "general_operand" "fG,m,fG"))]
"! memory_operand (operands[0], XFmode) "! memory_operand (operands[0], XFmode)
|| ! memory_operand (operands[1], XFmode)" || ! memory_operand (operands[1], XFmode)"
...@@ -485,8 +482,8 @@ ...@@ -485,8 +482,8 @@
[(set_attr "type" "I")]) [(set_attr "type" "I")])
(define_insn "extendsidi2" (define_insn "extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=r,*e") [(set (match_operand:DI 0 "register_operand" "=r,*f")
(sign_extend:DI (match_operand:SI 1 "register_operand" "r,*e")))] (sign_extend:DI (match_operand:SI 1 "register_operand" "r,*f")))]
"" ""
"@ "@
sxt4 %0 = %1 sxt4 %0 = %1
...@@ -514,8 +511,8 @@ ...@@ -514,8 +511,8 @@
[(set_attr "type" "I,M")]) [(set_attr "type" "I,M")])
(define_insn "zero_extendsidi2" (define_insn "zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r,*e") [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*e")))] (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
"" ""
"@ "@
zxt4 %0 = %1 zxt4 %0 = %1
...@@ -565,20 +562,20 @@ ...@@ -565,20 +562,20 @@
(define_insn "floatdixf2" (define_insn "floatdixf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(float:XF (match_operand:DI 1 "register_operand" "e")))] (float:XF (match_operand:DI 1 "register_operand" "f")))]
"" ""
"fcvt.xf %0 = %1" "fcvt.xf %0 = %1"
[(set_attr "type" "F")]) [(set_attr "type" "F")])
(define_insn "fix_truncsfdi2" (define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (match_operand:SF 1 "register_operand" "f")))] (fix:DI (match_operand:SF 1 "register_operand" "f")))]
"" ""
"fcvt.fx.trunc %0 = %1%B0" "fcvt.fx.trunc %0 = %1%B0"
[(set_attr "type" "F")]) [(set_attr "type" "F")])
(define_insn "fix_truncdfdi2" (define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (match_operand:DF 1 "register_operand" "f")))] (fix:DI (match_operand:DF 1 "register_operand" "f")))]
"" ""
"fcvt.fx.trunc %0 = %1%B0" "fcvt.fx.trunc %0 = %1%B0"
...@@ -588,27 +585,27 @@ ...@@ -588,27 +585,27 @@
(define_insn "floatunsdisf2" (define_insn "floatunsdisf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(unsigned_float:SF (match_operand:DI 1 "register_operand" "e")))] (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
"" ""
"fcvt.xuf.s %0 = %1%B0" "fcvt.xuf.s %0 = %1%B0"
[(set_attr "type" "F")]) [(set_attr "type" "F")])
(define_insn "floatunsdidf2" (define_insn "floatunsdidf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unsigned_float:DF (match_operand:DI 1 "register_operand" "e")))] (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
"" ""
"fcvt.xuf.d %0 = %1%B0" "fcvt.xuf.d %0 = %1%B0"
[(set_attr "type" "F")]) [(set_attr "type" "F")])
(define_insn "fixuns_truncsfdi2" (define_insn "fixuns_truncsfdi2"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=f")
(unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))] (unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))]
"" ""
"fcvt.fxu.trunc %0 = %1%B0" "fcvt.fxu.trunc %0 = %1%B0"
[(set_attr "type" "F")]) [(set_attr "type" "F")])
(define_insn "fixuns_truncdfdi2" (define_insn "fixuns_truncdfdi2"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=f")
(unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))] (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))]
"" ""
"fcvt.fxu.trunc %0 = %1%B0" "fcvt.fxu.trunc %0 = %1%B0"
...@@ -920,9 +917,9 @@ ...@@ -920,9 +917,9 @@
;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
(define_insn "*mulsi3_internal" (define_insn "*mulsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=e") [(set (match_operand:SI 0 "register_operand" "=f")
(mult:SI (match_operand:SI 1 "register_operand" "e") (mult:SI (match_operand:SI 1 "register_operand" "f")
(match_operand:SI 2 "nonmemory_operand" "e")))] (match_operand:SI 2 "nonmemory_operand" "f")))]
"" ""
"xma.l %0 = %1, %2, f0%B0" "xma.l %0 = %1, %2, f0%B0"
[(set_attr "type" "F")]) [(set_attr "type" "F")])
...@@ -1065,9 +1062,9 @@ ...@@ -1065,9 +1062,9 @@
[(set_attr "type" "A")]) [(set_attr "type" "A")])
(define_insn "muldi3" (define_insn "muldi3"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=f")
(mult:DI (match_operand:DI 1 "register_operand" "e") (mult:DI (match_operand:DI 1 "register_operand" "f")
(match_operand:DI 2 "register_operand" "e")))] (match_operand:DI 2 "register_operand" "f")))]
"" ""
"xma.l %0 = %1, %2, f0%B0" "xma.l %0 = %1, %2, f0%B0"
[(set_attr "type" "F")]) [(set_attr "type" "F")])
...@@ -1084,10 +1081,10 @@ ...@@ -1084,10 +1081,10 @@
;; ??? Maybe we should change how adds are canonicalized. ;; ??? Maybe we should change how adds are canonicalized.
(define_insn "*madddi3" (define_insn "*madddi3"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=f")
(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "e") (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
(match_operand:DI 2 "register_operand" "e")) (match_operand:DI 2 "register_operand" "f"))
(match_operand:DI 3 "register_operand" "e"))) (match_operand:DI 3 "register_operand" "f")))
(clobber (match_scratch:DI 4 "=X"))] (clobber (match_scratch:DI 4 "=X"))]
"" ""
"xma.l %0 = %1, %2, %3%B0" "xma.l %0 = %1, %2, %3%B0"
...@@ -1103,11 +1100,11 @@ ...@@ -1103,11 +1100,11 @@
(define_insn "*madddi3_elim" (define_insn "*madddi3_elim"
[(set (match_operand:DI 0 "register_operand" "=&r") [(set (match_operand:DI 0 "register_operand" "=&r")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "e") (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
(match_operand:DI 2 "register_operand" "e")) (match_operand:DI 2 "register_operand" "f"))
(match_operand:DI 3 "register_operand" "e")) (match_operand:DI 3 "register_operand" "f"))
(match_operand:DI 4 "nonmemory_operand" "rI"))) (match_operand:DI 4 "nonmemory_operand" "rI")))
(clobber (match_scratch:DI 5 "=e"))] (clobber (match_scratch:DI 5 "=f"))]
"reload_in_progress" "reload_in_progress"
"#" "#"
[(set_attr "type" "unknown")]) [(set_attr "type" "unknown")])
...@@ -1136,22 +1133,22 @@ ...@@ -1136,22 +1133,22 @@
;; to generate them. ;; to generate them.
(define_insn "smuldi3_highpart" (define_insn "smuldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=f")
(truncate:DI (truncate:DI
(lshiftrt:TI (lshiftrt:TI
(mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "e")) (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "f"))
(sign_extend:TI (match_operand:DI 2 "register_operand" "e"))) (sign_extend:TI (match_operand:DI 2 "register_operand" "f")))
(const_int 64))))] (const_int 64))))]
"" ""
"xma.h %0 = %1, %2, f0%B0" "xma.h %0 = %1, %2, f0%B0"
[(set_attr "type" "F")]) [(set_attr "type" "F")])
(define_insn "umuldi3_highpart" (define_insn "umuldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=e") [(set (match_operand:DI 0 "register_operand" "=f")
(truncate:DI (truncate:DI
(lshiftrt:TI (lshiftrt:TI
(mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "e")) (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "f"))
(zero_extend:TI (match_operand:DI 2 "register_operand" "e"))) (zero_extend:TI (match_operand:DI 2 "register_operand" "f")))
(const_int 64))))] (const_int 64))))]
"" ""
"xma.hu %0 = %1, %2, f0%B0" "xma.hu %0 = %1, %2, f0%B0"
...@@ -1735,9 +1732,9 @@ ...@@ -1735,9 +1732,9 @@
;; :::::::::::::::::::: ;; ::::::::::::::::::::
(define_insn "anddi3" (define_insn "anddi3"
[(set (match_operand:DI 0 "register_operand" "=r,*e") [(set (match_operand:DI 0 "register_operand" "=r,*f")
(and:DI (match_operand:DI 1 "register_operand" "%r,*e") (and:DI (match_operand:DI 1 "register_operand" "%r,*f")
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))] (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
"" ""
"@ "@
and %0 = %2, %1 and %0 = %2, %1
...@@ -1745,9 +1742,9 @@ ...@@ -1745,9 +1742,9 @@
[(set_attr "type" "A,F")]) [(set_attr "type" "A,F")])
(define_insn "*andnot" (define_insn "*andnot"
[(set (match_operand:DI 0 "register_operand" "=r,*e") [(set (match_operand:DI 0 "register_operand" "=r,*f")
(and:DI (not:DI (match_operand:DI 1 "register_operand" "r,*e")) (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,*f"))
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))] (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
"" ""
"@ "@
andcm %0 = %2, %1 andcm %0 = %2, %1
...@@ -1755,9 +1752,9 @@ ...@@ -1755,9 +1752,9 @@
[(set_attr "type" "A,F")]) [(set_attr "type" "A,F")])
(define_insn "iordi3" (define_insn "iordi3"
[(set (match_operand:DI 0 "register_operand" "=r,*e") [(set (match_operand:DI 0 "register_operand" "=r,*f")
(ior:DI (match_operand:DI 1 "register_operand" "%r,*e") (ior:DI (match_operand:DI 1 "register_operand" "%r,*f")
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))] (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
"" ""
"@ "@
or %0 = %2, %1 or %0 = %2, %1
...@@ -1765,9 +1762,9 @@ ...@@ -1765,9 +1762,9 @@
[(set_attr "type" "A,F")]) [(set_attr "type" "A,F")])
(define_insn "xordi3" (define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=r,*e") [(set (match_operand:DI 0 "register_operand" "=r,*f")
(xor:DI (match_operand:DI 1 "register_operand" "%r,*e") (xor:DI (match_operand:DI 1 "register_operand" "%r,*f")
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))] (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
"" ""
"@ "@
xor %0 = %2, %1 xor %0 = %2, %1
...@@ -3000,7 +2997,7 @@ ...@@ -3000,7 +2997,7 @@
(return) (return)
(pc)))] (pc)))]
"ia64_direct_return ()" "ia64_direct_return ()"
"(%%J0) br.ret%+.many rp" "(%J0) br.ret%+.many rp"
[(set_attr "type" "B") [(set_attr "type" "B")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -3012,7 +3009,7 @@ ...@@ -3012,7 +3009,7 @@
(pc) (pc)
(return)))] (return)))]
"ia64_direct_return ()" "ia64_direct_return ()"
"(%%j0) br.ret%+.many rp" "(%j0) br.ret%+.many rp"
[(set_attr "type" "B") [(set_attr "type" "B")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
...@@ -3132,13 +3129,13 @@ ...@@ -3132,13 +3129,13 @@
(define_insn "fr_spill" (define_insn "fr_spill"
[(set (match_operand:XF 0 "memory_operand" "=m") [(set (match_operand:XF 0 "memory_operand" "=m")
(unspec:XF [(match_operand:XF 1 "register_operand" "f*e")] 3))] (unspec:XF [(match_operand:XF 1 "register_operand" "f")] 3))]
"" ""
"stf.spill %0 = %1%P0" "stf.spill %0 = %1%P0"
[(set_attr "type" "M")]) [(set_attr "type" "M")])
(define_insn "fr_restore" (define_insn "fr_restore"
[(set (match_operand:XF 0 "register_operand" "=f*e") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "memory_operand" "m")] 4))] (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] 4))]
"" ""
"ldf.fill %0 = %1%P1" "ldf.fill %0 = %1%P1"
...@@ -3196,28 +3193,14 @@ ...@@ -3196,28 +3193,14 @@
[(unspec_volatile [(const_int 0)] 5) [(unspec_volatile [(const_int 0)] 5)
(use (match_operand:DI 0 "register_operand" "r"))] (use (match_operand:DI 0 "register_operand" "r"))]
"" ""
"flushrs\; \ "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
mov r19=ar.rsc\; \
;;\; \
and r19=0x1c,r19\; \
;;\; \
mov ar.rsc=r19\; \
;;\; \
mov ar.bspstore=%0\; \
;;\; \
or r19=0x3,r19\; \
;;\; \
loadrs\; \
invala\; \
;;\; \
mov ar.rsc=r19\;"
[(set_attr "type" "unknown") [(set_attr "type" "unknown")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
(define_insn "flushrs" (define_insn "flushrs"
[(unspec [(const_int 0)] 21)] [(unspec [(const_int 0)] 21)]
"" ""
";; \; flushrs" ";;\;flushrs"
[(set_attr "type" "M")]) [(set_attr "type" "M")])
;; :::::::::::::::::::: ;; ::::::::::::::::::::
......
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