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riscv-gcc-1
Commit 11ac38b2 by David Edelsohn Committed by David Edelsohn
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rs6000.c (rs6000_use_dfa_pipeline_interface): Delete. 

	* config/rs6000/rs6000.c (rs6000_use_dfa_pipeline_interface): Delete.
	(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Redefine a hook_int_void_1.
	(insvdi_rshift_rlwimi_p): New function.
	* config/rs6000/rs6000.md (insvdi_internal2/3): New patterns.
	(extendsfdf2): Convert to define_insn_and_split.
	* config/rs6000/rs6000-protos.h (insvdi_rshift_rlwimi_p): Prototype.

From-SVN: r83568
parent de46b2fe
Showing with 82 additions and 17 deletions
gcc/ChangeLog
2004-06-23 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.c (rs6000_use_dfa_pipeline_interface): Delete.
(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Redefine a hook_int_void_1.
(insvdi_rshift_rlwimi_p): New function.
* config/rs6000/rs6000.md (insvdi_internal2/3): New patterns.
(extendsfdf2): Convert to define_insn_and_split.
* config/rs6000/rs6000-protos.h (insvdi_rshift_rlwimi_p): Prototype.
2004-06-23 Andrew Pinski <apinski@apple.com>
* c-typeck.c (composite_type, <case ARRAY_TYPE>): Abort if we have
......
gcc/config/rs6000/rs6000-protos.h
......@@ -101,6 +101,7 @@ extern int includes_lshift_p (rtx, rtx);
extern int includes_rshift_p (rtx, rtx);
extern int includes_rldic_lshift_p (rtx, rtx);
extern int includes_rldicr_lshift_p (rtx, rtx);
extern int insvdi_rshift_rlwimi_p (rtx, rtx, rtx);
extern int registers_ok_for_quad_peep (rtx, rtx);
extern int mems_ok_for_quad_peep (rtx, rtx);
extern bool gpr_or_gpr_p (rtx, rtx);
......
gcc/config/rs6000/rs6000.c
......@@ -353,7 +353,6 @@ static void rs6000_xcoff_file_end (void);
#if TARGET_MACHO
static bool rs6000_binds_local_p (tree);
#endif
static int rs6000_use_dfa_pipeline_interface (void);
static int rs6000_variable_issue (FILE *, int, rtx, int);
static bool rs6000_rtx_costs (rtx, int, int, int *);
static int rs6000_adjust_cost (rtx, rtx, rtx, int);
......@@ -570,7 +569,7 @@ static const char alt_reg_names[][8] =
#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
#undef TARGET_SCHED_VARIABLE_ISSUE
#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
......@@ -8825,6 +8824,26 @@ includes_rldicr_lshift_p (rtx shiftop, rtx andop)
return 0;
}
/* Return 1 if operands will generate a valid arguments to rlwimi
instruction for insert with right shift in 64-bit mode. The mask may
not start on the first bit or stop on the last bit because wrap-around
effects of instruction do not correspond to semantics of RTL insn. */
int
insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
{
if (INTVAL (startop) < 64
&& INTVAL (startop) > 32
&& (INTVAL (sizeop) + INTVAL (startop) < 64)
&& (INTVAL (sizeop) + INTVAL (startop) > 33)
&& (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
&& (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
&& (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
return 1;
return 0;
}
/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
for lfq and stfq insns iff the registers are hard registers. */
......@@ -14179,12 +14198,6 @@ output_function_profiler (FILE *file, int labelno)
}
static int
rs6000_use_dfa_pipeline_interface (void)
{
return 1;
}
/* Power4 load update and store update instructions are cracked into a
load or store and an integer insn which are executed in the same cycle.
Branches have their own dispatch slot which does not count against the
......
gcc/config/rs6000/rs6000.md
......@@ -3090,6 +3090,46 @@
return \"rldimi %0,%3,%H1,%H2\";
}")
(define_insn "*insvdi_internal2"
[(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
(ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
(match_operand:SI 4 "const_int_operand" "i")))]
"TARGET_POWERPC64
&& insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
"*
{
int shift = INTVAL (operands[4]) & 63;
int start = (INTVAL (operands[2]) & 63) - 32;
int size = INTVAL (operands[1]) & 63;
operands[4] = GEN_INT (64 - shift - start - size);
operands[2] = GEN_INT (start);
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}")
(define_insn "*insvdi_internal3"
[(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
(lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
(match_operand:SI 4 "const_int_operand" "i")))]
"TARGET_POWERPC64
&& insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
"*
{
int shift = INTVAL (operands[4]) & 63;
int start = (INTVAL (operands[2]) & 63) - 32;
int size = INTVAL (operands[1]) & 63;
operands[4] = GEN_INT (64 - shift - start - size);
operands[2] = GEN_INT (start);
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}")
(define_expand "extzv"
[(set (match_operand 0 "gpc_reg_operand" "")
(zero_extract (match_operand 1 "gpc_reg_operand" "")
......@@ -4411,17 +4451,19 @@
;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point.
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
(define_insn_and_split "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"*
"@
#
fmr %0,%1"
"&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
[(const_int 0)]
{
if (REGNO (operands[0]) == REGNO (operands[1]))
return \"\";
else
return \"fmr %0,%1\";
}"
emit_note (NOTE_INSN_DELETED);
DONE;
}
[(set_attr "type" "fp")])
(define_insn "truncdfsf2"
......
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