mips.h (mips_output_conditional_branch): New function.

	* mips.h (mips_output_conditional_branch): New function.
	(mips_adjust_insn_length): Likewise.
	(ASSEMBLER_SCRATCH_REGNUM): New macro.
	(ADJUST_INSN_LENGTH): Likewise.
	* mips.c (print_operand): Add `F' and `W' for floating-point
	comparison opcodes.
	(machine_dependent_reorg): Adjust MIPS16 code; instruction-lengths
	are now in bytes.
	(mips_adjust_insn_length): New function.
	(mips_output_conditional_branch): New function.
	* mips.md (length): Adjust attribute definition to handle
	conditional branches.  	Change lengths to bytes, rather than
	instructions throughout.  Remove length attribute from
	instructions whose length is four bytes, and rely on the default
	instead.
	(dslot): Fix typo in comment.
	Reword conditional branch patterns to use
	mips_output_conditional_branch.

From-SVN: r27369

gcc/ChangeLog

+Sat Jun  5 12:11:24 1999  Mark Mitchell  <mark@codesourcery.com>
+
+	* mips.h (mips_output_conditional_branch): New function.
+	(mips_adjust_insn_length): Likewise.
+	(ASSEMBLER_SCRATCH_REGNUM): New macro.
+	(ADJUST_INSN_LENGTH): Likewise.
+	* mips.c (print_operand): Add `F' and `W' for floating-point
+	comparison opcodes.
+	(machine_dependent_reorg): Adjust MIPS16 code; instruction-lengths
+	are now in bytes.
+	(mips_adjust_insn_length): New function.
+	(mips_output_conditional_branch): New function.
+	* mips.md (length): Adjust attribute definition to handle
+	conditional branches.  	Change lengths to bytes, rather than
+	instructions throughout.  Remove length attribute from
+	instructions whose length is four bytes, and rely on the default
+	instead.
+	(dslot): Fix typo in comment.
+	Reword conditional branch patterns to use
+	mips_output_conditional_branch.
+
 Fri Jun  4 13:30:27 1999  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 
 	* alpha/osf.h (CPP_SUBTARGET_SPEC): Handle -threads.

gcc/config/mips/mips.h

@@ -233,6 +233,8 @@ extern int		mips16_gp_offset_p ();
 extern int		mips16_constant ();
 extern int		mips16_constant_after_function_p ();
 extern int		build_mips16_call_stub ();
+extern char  	       *mips_output_conditional_branch ();
+extern int              mips_adjust_insn_length ();
 
 /* Recognition functions that return if a condition is true.  */
 extern int		address_operand ();
@@ -1686,6 +1688,9 @@ extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
    a fixed register, and will not be used for anything else.  */
 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
 
+/* Temporary scratch register for use by the assembler.  */
+#define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
+
 /* $30 is not available on the mips16, so we use $17 as the frame
    pointer.  */
 #define HARD_FRAME_POINTER_REGNUM \
@@ -3770,6 +3775,14 @@ while (0)
   if (REG_NOTE_KIND (LINK) != 0)					\
     (COST) = 0; /* Anti or output dependence.  */
 
+/* If defined, modifies the length assigned to instruction INSN as a
+   function of the context in which it is used.  LENGTH is an lvalue
+   that contains the initially computed length of the insn and should
+   be updated with the correct length of the insn.  */
+#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
+  ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
+
+
 /* Optionally define this if you have added predicates to
    `MACHINE.c'.  This macro is called within an initializer of an
    array of structures.  The first field in the structure is the