[ARC] Code size modifications.

gcc/
2017-03-13  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_init): Use multiplier whenever we have it.
	(arc_conditional_register_usage): Use a different allocation order
	when optimizing for size.
	* common/config/arc/arc-common.c (arc_option_optimization_table):
	Section anchors default on when optimizing for size.

From-SVN: r246091

gcc/ChangeLog

 2017-03-13  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* config/arc/arc.c (arc_init): Use multiplier whenever we have it.
+	(arc_conditional_register_usage): Use a different allocation order
+	when optimizing for size.
+	* common/config/arc/arc-common.c (arc_option_optimization_table):
+	Section anchors default on when optimizing for size.
+
+2017-03-13  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* config/arc/arc.md (*tst_bitfield_tst): Fix pattern.
 
 2017-03-13  Claudiu Zissulescu  <claziss@synopsys.com>

gcc/common/config/arc/arc-common.c

@@ -46,6 +46,7 @@ arc_option_init_struct (struct gcc_options *opts)
 #define OPT_LEVELS_3_PLUS_SPEED_ONLY OPT_LEVELS_3_PLUS
 static const struct default_options arc_option_optimization_table[] =
   {
+    { OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 },
     { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
     { OPT_LEVELS_ALL, OPT_mRcq, NULL, 1 },
     { OPT_LEVELS_ALL, OPT_mRcw, NULL, 1 },

gcc/config/arc/arc.c

@@ -676,6 +676,12 @@ make_pass_arc_predicate_delay_insns (gcc::context *ctxt)
 static void
 arc_init (void)
 {
+  if (TARGET_V2)
+    {
+      /* I have the multiplier, then use it*/
+      if (TARGET_MPYW || TARGET_MULTI)
+	  arc_multcost = COSTS_N_INSNS (1);
+    }
   /* Note: arc_multcost is only used in rtx_cost if speed is true.  */
   if (arc_multcost < 0)
     switch (arc_tune)
@@ -1374,6 +1380,27 @@ arc_conditional_register_usage (void)
     }
   if (TARGET_Q_CLASS)
     {
+      if (optimize_size)
+	{
+	  reg_alloc_order[0] = 0;
+	  reg_alloc_order[1] = 1;
+	  reg_alloc_order[2] = 2;
+	  reg_alloc_order[3] = 3;
+	  reg_alloc_order[4] = 12;
+	  reg_alloc_order[5] = 13;
+	  reg_alloc_order[6] = 14;
+	  reg_alloc_order[7] = 15;
+	  reg_alloc_order[8] = 4;
+	  reg_alloc_order[9] = 5;
+	  reg_alloc_order[10] = 6;
+	  reg_alloc_order[11] = 7;
+	  reg_alloc_order[12] = 8;
+	  reg_alloc_order[13] = 9;
+	  reg_alloc_order[14] = 10;
+	  reg_alloc_order[15] = 11;
+	}
+      else
+	{
 	  reg_alloc_order[2] = 12;
 	  reg_alloc_order[3] = 13;
 	  reg_alloc_order[4] = 14;
@@ -1389,6 +1416,7 @@ arc_conditional_register_usage (void)
 	  reg_alloc_order[14] = 10;
 	  reg_alloc_order[15] = 11;
 	}
+    }
   if (TARGET_SIMD_SET)
     {
       int i;