[ARC] Update (u)maddsidi patterns.

The accumulator registers are freely used by the compiler. However,
there are a number of instructions which are having an intrinsic use
of these registers. Update patterns to inform the compiler which ones.

gcc/
2017-09-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (maddsidi4, maddsidi4_split): Update pattern.
	(umaddsidi4,umaddsidi4): Likewise.

gcc/testsuite
2017-09-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/tumaddsidi4.c: New test.

From-SVN: r255779

gcc/ChangeLog

 2017-12-18  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* config/arc/arc.md (maddsidi4, maddsidi4_split): Update pattern.
+	(umaddsidi4, umaddsidi_split): Likewise.
+
+2017-12-18  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* config/arc/arc.c (arc_legitimate_constant_p): Always check all
 	constants.
 

gcc/config/arc/arc.md

@@ -6155,13 +6155,25 @@
   [(set_attr "length" "0")])
 
 ;; MAC and DMPY instructions
-(define_insn_and_split "maddsidi4"
+(define_expand "maddsidi4"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "extend_operand"   "")
+   (match_operand:DI 3 "register_operand" "")]
+  "TARGET_PLUS_DMPY"
+  "{
+   emit_insn (gen_maddsidi4_split (operands[0], operands[1], operands[2], operands[3]));
+   DONE;
+  }")
+
+(define_insn_and_split "maddsidi4_split"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI
 	 (mult:DI
 	  (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
 	  (sign_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
-	 (match_operand:DI 3 "register_operand" "r")))]
+	 (match_operand:DI 3 "register_operand" "r")))
+   (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_DMPY"
   "#"
   "TARGET_PLUS_DMPY && reload_completed"
@@ -6243,13 +6255,25 @@
    (set_attr "predicable" "no")
    (set_attr "cond" "nocond")])
 
-(define_insn_and_split "umaddsidi4"
+(define_expand "umaddsidi4"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "extend_operand"   "")
+   (match_operand:DI 3 "register_operand" "")]
+  "TARGET_PLUS_DMPY"
+  "{
+   emit_insn (gen_umaddsidi4_split (operands[0], operands[1], operands[2], operands[3]));
+   DONE;
+  }")
+
+(define_insn_and_split "umaddsidi4_split"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI
 	 (mult:DI
 	  (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
 	  (zero_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
-	 (match_operand:DI 3 "register_operand" "r")))]
+	 (match_operand:DI 3 "register_operand" "r")))
+   (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_DMPY"
   "#"
   "TARGET_PLUS_DMPY && reload_completed"

gcc/testsuite/ChangeLog

 2017-12-18  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* gcc.target/arc/tumaddsidi4.c: New test.
+
+2017-12-18  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* gcc.target/arc/tls-1.c: New test.
 
 2017-12-18  Richard Biener  <rguenther@suse.de>

gcc/testsuite/gcc.target/arc/tumaddsidi4.c

+/* { dg-do compile } */
+/* { dg-options "-mcpu=archs -O1 -mmpy-option=plus_dmpy" } */
+
+/* Check how we generate umaddsidi4 patterns.  */
+long a;
+long long b;
+unsigned c, d;
+
+void fn1(void)
+{
+  b = d * (long long)c + a;
+}
+
+/* { dg-final { scan-assembler "macu 0,r" } } */