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riscv-gcc-1
Commit 0c15dfc1 by Jeff Law Committed by Jeff Law
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* config/mcore/mcore.c (mcore_gen_compare): Adjust fallthru comments. 

From-SVN: r241569
parent 1cd20a8f
Showing with 7 additions and 5 deletions
gcc/ChangeLog
2016-10-26 Jeff Law <law@redhat.com>
* config/mcore/mcore.c (mcore_gen_compare): Adjust fallthru comments.
* config/microblaze/microblaze.c (microblaze_function_arg): Adjust
fallthru comment.
......
gcc/config/mcore/mcore.c
......@@ -611,7 +611,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
case EQ: /* Use inverted condition, cmpne. */
code = NE;
invert = true;
/* Drop through. */
/* FALLTHRU */
case NE: /* Use normal condition, cmpne. */
if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
......@@ -621,7 +621,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
case LE: /* Use inverted condition, reversed cmplt. */
code = GT;
invert = true;
/* Drop through. */
/* FALLTHRU */
case GT: /* Use normal condition, reversed cmplt. */
if (GET_CODE (op1) == CONST_INT)
......@@ -631,7 +631,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
case GE: /* Use inverted condition, cmplt. */
code = LT;
invert = true;
/* Drop through. */
/* FALLTHRU */
case LT: /* Use normal condition, cmplt. */
if (GET_CODE (op1) == CONST_INT &&
......@@ -646,7 +646,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0);
code = LEU;
invert = true;
/* Drop through. */
/* FALLTHRU */
case LEU: /* Use normal condition, reversed cmphs. */
if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
......@@ -656,7 +656,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
case LTU: /* Use inverted condition, cmphs. */
code = GEU;
invert = true;
/* Drop through. */
/* FALLTHRU */
case GEU: /* Use normal condition, cmphs. */
if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
......
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