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riscv-gcc-1
Commit 0ae24cc8 by Vladimir Makarov Committed by Vladimir Makarov
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revert: rtl.h (struct rtx_def): ... 

2013-04-24  Vladimir Makarov  <vmakarov@redhat.com>

	Revert:
	2013-04-24  Vladimir Makarov  <vmakarov@redhat.com>
	* rtl.h (struct rtx_def): ...

From-SVN: r198266
parent ec98d010
Showing with 12 additions and 32 deletions
gcc/ChangeLog
2013-04-24 Vladimir Makarov <vmakarov@redhat.com>
Revert:
2013-04-24 Vladimir Makarov <vmakarov@redhat.com>
* rtl.h (struct rtx_def): ...
2013-04-24 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimizations/57046
* lra-constraints (split_reg): Set up lra_risky_transformations_p
for multi-reg splits.
......
gcc/lra-eliminations.c
......@@ -977,9 +977,6 @@ eliminate_regs_in_insn (rtx insn, bool replace_p)
}
}
if (! validate_p)
return;
/* Substitute the operands; the new values are in the substed_operand
array. */
for (i = 0; i < static_id->n_operands; i++)
......@@ -987,6 +984,8 @@ eliminate_regs_in_insn (rtx insn, bool replace_p)
for (i = 0; i < static_id->n_dups; i++)
*id->dup_loc[i] = substed_operand[(int) static_id->dup_num[i]];
if (validate_p)
{
/* If we had a move insn but now we don't, re-recognize it.
This will cause spurious re-recognition if the old move had a
PARALLEL since the new one still will, but we can't call
......@@ -994,6 +993,7 @@ eliminate_regs_in_insn (rtx insn, bool replace_p)
re-recognition won't hurt in this rare case. */
id = lra_update_insn_recog_data (insn);
static_id = id->insn_static_data;
}
}
/* Spill pseudos which are assigned to hard registers in SET. Add
......
gcc/lra-spills.c
......@@ -548,11 +548,6 @@ lra_spill (void)
for (i = 0; i < n; i++)
if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX)
assign_mem_slot (pseudo_regnos[i]);
if (n > 0 && crtl->stack_alignment_needed)
/* If we have a stack frame, we must align it now. The stack size
may be a part of the offset computation for register
elimination. */
assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
if (lra_dump_file != NULL)
{
for (i = 0; i < slots_num; i++)
......@@ -649,12 +644,10 @@ lra_final_code_change (void)
}
lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
struct lra_static_insn_data *static_id = id->insn_static_data;
bool insn_change_p = false;
for (i = id->insn_static_data->n_operands - 1; i >= 0; i--)
if ((DEBUG_INSN_P (insn) || ! static_id->operand[i].is_operator)
&& alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn)))
if (alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn)))
{
lra_update_dup (id, i);
insn_change_p = true;
......
gcc/lra.c
......@@ -2203,10 +2203,6 @@ lra (FILE *f)
timevar_push (TV_LRA);
/* Make sure that the last insn is a note. Some subsequent passes
need it. */
emit_note (NOTE_INSN_DELETED);
COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs);
init_reg_info ();
......@@ -2263,11 +2259,6 @@ lra (FILE *f)
bitmap_initialize (&lra_split_regs, &reg_obstack);
bitmap_initialize (&lra_optional_reload_pseudos, &reg_obstack);
live_p = false;
if (get_frame_size () != 0 && crtl->stack_alignment_needed)
/* If we have a stack frame, we must align it now. The stack size
may be a part of the offset computation for register
elimination. */
assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
for (;;)
{
for (;;)
......
gcc/recog.c
......@@ -1065,11 +1065,7 @@ register_operand (rtx op, enum machine_mode mode)
&& REGNO (sub) < FIRST_PSEUDO_REGISTER
&& REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
&& GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT
/* LRA can generate some invalid SUBREGS just for matched
operand reload presentation. LRA needs to treat them as
valid. */
&& ! LRA_SUBREG_P (op))
&& GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT)
return 0;
#endif
......
gcc/rtl.h
......@@ -265,8 +265,7 @@ struct GTY((chain_next ("RTX_NEXT (&%h)"),
1 in a SET that is for a return.
In a CODE_LABEL, part of the two-bit alternate entry field.
1 in a CONCAT is VAL_EXPR_IS_COPIED in var-tracking.c.
1 in a VALUE is SP_BASED_VALUE_P in cselib.c.
1 in a SUBREG generated by LRA for reload insns. */
1 in a VALUE is SP_BASED_VALUE_P in cselib.c. */
unsigned int jump : 1;
/* In a CODE_LABEL, part of the two-bit alternate entry field.
1 in a MEM if it cannot trap.
......@@ -1412,11 +1411,6 @@ do { \
((RTL_FLAG_CHECK1("SUBREG_PROMOTED_UNSIGNED_P", (RTX), SUBREG)->volatil) \
? -1 : (int) (RTX)->unchanging)
/* True if the subreg was generated by LRA for reload insns. Such
subregs are valid only during LRA. */
#define LRA_SUBREG_P(RTX) \
(RTL_FLAG_CHECK1("LRA_SUBREG_P", (RTX), SUBREG)->jump)
/* Access various components of an ASM_OPERANDS rtx. */
#define ASM_OPERANDS_TEMPLATE(RTX) XCSTR (RTX, 0, ASM_OPERANDS)
......
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