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Commit 09485a08 by Sofiane Naci Committed by Sofiane Naci
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arm.md (attribute "insn"): Move multiplication and division attributes to... 

	* config/arm/arm.md (attribute "insn"): Move multiplication and division
	attributes to...
	(attribute "type"): ... here.  Remove mult.
	(attribute "mul32"): New attribute.
	(attribute "mul64"): Add umaal.
	(*arm_mulsi3): Update attributes.
	(*arm_mulsi3_v6): Likewise.
	(*thumb_mulsi3): Likewise.
	(*thumb_mulsi3_v6): Likewise.
	(*mulsi3_compare0): Likewise.
	(*mulsi3_compare0_v6): Likewise.
	(*mulsi_compare0_scratch): Likewise.
	(*mulsi_compare0_scratch_v6): Likewise.
	(*mulsi3addsi): Likewise.
	(*mulsi3addsi_v6): Likewise.
	(*mulsi3addsi_compare0): Likewise.
	(*mulsi3addsi_compare0_v6): Likewise.
	(*mulsi3addsi_compare0_scratch): Likewise.
	(*mulsi3addsi_compare0_scratch_v6): Likewise.
	(*mulsi3subsi): Likewise.
	(*mulsidi3adddi): Likewise.
	(*mulsi3addsi_v6): Likewise.
	(*mulsidi3adddi_v6): Likewise.
	(*mulsidi3_nov6): Likewise.
	(*mulsidi3_v6): Likewise.
	(*umulsidi3_nov6): Likewise.
	(*umulsidi3_v6): Likewise.
	(*umulsidi3adddi): Likewise.
	(*umulsidi3adddi_v6): Likewise.
	(*smulsi3_highpart_nov6): Likewise.
	(*smulsi3_highpart_v6): Likewise.
	(*umulsi3_highpart_nov6): Likewise.
	(*umulsi3_highpart_v6): Likewise.
	(mulhisi3): Likewise.
	(*mulhisi3tb): Likewise.
	(*mulhisi3bt): Likewise.
	(*mulhisi3tt): Likewise.
	(maddhisi4): Likewise.
	(*maddhisi4tb): Likewise.
	(*maddhisi4tt): Likewise.
	(maddhidi4): Likewise.
	(*maddhidi4tb): Likewise.
	(*maddhidi4tt): Likewise.
	(divsi3): Likewise.
	(udivsi3): Likewise.
	* config/arm/thumb2.md (thumb2_mulsi_short): Update attributes.
	(thumb2_mulsi_short_compare0): Likewise.
	(thumb2_mulsi_short_compare0_scratch): Likewise.
	* config/arm/arm1020e.md (1020mult1): Update attribute change.
	(1020mult2): Likewise.
	(1020mult3): Likewise.
	(1020mult4): Likewise.
	(1020mult5): Likewise.
	(1020mult6): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_mult32): Update attribute change.
	(cortex_a15_mult64): Likewise.
	(cortex_a15_sdiv): Likewise.
	(cortex_a15_udiv): Likewise.
	* config/arm/arm1026ejs.md (mult1): Update attribute change.
	(mult2): Likewise.
	(mult3): Likewise.
	(mult4): Likewise.
	(mult5): Likewise.
	(mult6): Likewise.
	* config/arm/marvell-pj4.md (pj4_ir_mul): Update attribute change.
	(pj4_ir_div): Likewise.
	* config/arm/arm1136jfs.md (11_mult1): Update attribute change.
	(11_mult2): Likewise.
	(11_mult3): Likewise.
	(11_mult4): Likewise.
	(11_mult5): Likewise.
	(11_mult6): Likewise.
	(11_mult7): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_mul): Update attribute change.
	(cortex_a8_mla): Likewise.
	(cortex_a8_mull): Likewise.
	(cortex_a8_smulwy): Likewise.
	(cortex_a8_smlald): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Update attribute change.
	* config/arm/cortex-r4.md (cortex_r4_mul_4): Update attribute change.
	(cortex_r4_mul_3): Likewise.
	(cortex_r4_mla_4): Likewise.
	(cortex_r4_mla_3): Likewise.
	(cortex_r4_smlald): Likewise.
	(cortex_r4_mull): Likewise.
	(cortex_r4_sdiv): Likewise.
	(cortex_r4_udiv): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_mul): Update attribute change.
	(cortex_a7_idiv): Likewise.
	* config/arm/arm926ejs.md (9_mult1): Update attribute change.
	(9_mult2): Likewise.
	(9_mult3): Likewise.
	(9_mult4): Likewise.
	(9_mult5): Likewise.
	(9_mult6): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_mul): Update attribute change.
	(cortex_a53_sdiv): Likewise.
	(cortex_a53_udiv): Likewise.
	* config/arm/fa726te.md (726te_mult_op): Update attribute change.
	* config/arm/fmp626.md (mp626_mult1): Update attribute change.
	(mp626_mult2): Likewise.
	(mp626_mult3): Likewise.
	(mp626_mult4): Likewise.
	* config/arm/fa526.md (526_mult1): Update attribute change.
	(526_mult2): Likewise.
	* config/arm/arm-generic.md (mult): Update attribute change.
	(mult_ldsched_strongarm): Likewise.
	(mult_ldsched): Likewise.
	(multi_cycle): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_mul): Update attribute change.
	* config/arm/fa606te.md (606te_mult1): Update attribute change.
	(606te_mult2): Likewise.
	(606te_mult3): Likewise.
	(606te_mult4): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_mult16): Update attribute change.
	(cortex_a9_mac16): Likewise.
	(cortex_a9_multiply): Likewise.
	(cortex_a9_mac): Likewise.
	(cortex_a9_multiply_long): Likewise.
	* config/arm/fa626te.md (626te_mult1): Update attribute change.
	(626te_mult2): Likewise.
	(626te_mult3): Likewise.
	(626te_mult4): Likewise.

From-SVN: r200167
parent d5ac899c
Showing with 311 additions and 132 deletions
gcc/ChangeLog
2013-06-18 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/arm.md (attribute "insn"): Move multiplication and division
attributes to...
(attribute "type"): ... here. Remove mult.
(attribute "mul32"): New attribute.
(attribute "mul64"): Add umaal.
(*arm_mulsi3): Update attributes.
(*arm_mulsi3_v6): Likewise.
(*thumb_mulsi3): Likewise.
(*thumb_mulsi3_v6): Likewise.
(*mulsi3_compare0): Likewise.
(*mulsi3_compare0_v6): Likewise.
(*mulsi_compare0_scratch): Likewise.
(*mulsi_compare0_scratch_v6): Likewise.
(*mulsi3addsi): Likewise.
(*mulsi3addsi_v6): Likewise.
(*mulsi3addsi_compare0): Likewise.
(*mulsi3addsi_compare0_v6): Likewise.
(*mulsi3addsi_compare0_scratch): Likewise.
(*mulsi3addsi_compare0_scratch_v6): Likewise.
(*mulsi3subsi): Likewise.
(*mulsidi3adddi): Likewise.
(*mulsi3addsi_v6): Likewise.
(*mulsidi3adddi_v6): Likewise.
(*mulsidi3_nov6): Likewise.
(*mulsidi3_v6): Likewise.
(*umulsidi3_nov6): Likewise.
(*umulsidi3_v6): Likewise.
(*umulsidi3adddi): Likewise.
(*umulsidi3adddi_v6): Likewise.
(*smulsi3_highpart_nov6): Likewise.
(*smulsi3_highpart_v6): Likewise.
(*umulsi3_highpart_nov6): Likewise.
(*umulsi3_highpart_v6): Likewise.
(mulhisi3): Likewise.
(*mulhisi3tb): Likewise.
(*mulhisi3bt): Likewise.
(*mulhisi3tt): Likewise.
(maddhisi4): Likewise.
(*maddhisi4tb): Likewise.
(*maddhisi4tt): Likewise.
(maddhidi4): Likewise.
(*maddhidi4tb): Likewise.
(*maddhidi4tt): Likewise.
(divsi3): Likewise.
(udivsi3): Likewise.
* config/arm/thumb2.md (thumb2_mulsi_short): Update attributes.
(thumb2_mulsi_short_compare0): Likewise.
(thumb2_mulsi_short_compare0_scratch): Likewise.
* config/arm/arm1020e.md (1020mult1): Update attribute change.
(1020mult2): Likewise.
(1020mult3): Likewise.
(1020mult4): Likewise.
(1020mult5): Likewise.
(1020mult6): Likewise.
* config/arm/cortex-a15.md (cortex_a15_mult32): Update attribute change.
(cortex_a15_mult64): Likewise.
(cortex_a15_sdiv): Likewise.
(cortex_a15_udiv): Likewise.
* config/arm/arm1026ejs.md (mult1): Update attribute change.
(mult2): Likewise.
(mult3): Likewise.
(mult4): Likewise.
(mult5): Likewise.
(mult6): Likewise.
* config/arm/marvell-pj4.md (pj4_ir_mul): Update attribute change.
(pj4_ir_div): Likewise.
* config/arm/arm1136jfs.md (11_mult1): Update attribute change.
(11_mult2): Likewise.
(11_mult3): Likewise.
(11_mult4): Likewise.
(11_mult5): Likewise.
(11_mult6): Likewise.
(11_mult7): Likewise.
* config/arm/cortex-a8.md (cortex_a8_mul): Update attribute change.
(cortex_a8_mla): Likewise.
(cortex_a8_mull): Likewise.
(cortex_a8_smulwy): Likewise.
(cortex_a8_smlald): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Update attribute change.
* config/arm/cortex-r4.md (cortex_r4_mul_4): Update attribute change.
(cortex_r4_mul_3): Likewise.
(cortex_r4_mla_4): Likewise.
(cortex_r4_mla_3): Likewise.
(cortex_r4_smlald): Likewise.
(cortex_r4_mull): Likewise.
(cortex_r4_sdiv): Likewise.
(cortex_r4_udiv): Likewise.
* config/arm/cortex-a7.md (cortex_a7_mul): Update attribute change.
(cortex_a7_idiv): Likewise.
* config/arm/arm926ejs.md (9_mult1): Update attribute change.
(9_mult2): Likewise.
(9_mult3): Likewise.
(9_mult4): Likewise.
(9_mult5): Likewise.
(9_mult6): Likewise.
* config/arm/cortex-a53.md (cortex_a53_mul): Update attribute change.
(cortex_a53_sdiv): Likewise.
(cortex_a53_udiv): Likewise.
* config/arm/fa726te.md (726te_mult_op): Update attribute change.
* config/arm/fmp626.md (mp626_mult1): Update attribute change.
(mp626_mult2): Likewise.
(mp626_mult3): Likewise.
(mp626_mult4): Likewise.
* config/arm/fa526.md (526_mult1): Update attribute change.
(526_mult2): Likewise.
* config/arm/arm-generic.md (mult): Update attribute change.
(mult_ldsched_strongarm): Likewise.
(mult_ldsched): Likewise.
(multi_cycle): Likewise.
* config/arm/cortex-a5.md (cortex_a5_mul): Update attribute change.
* config/arm/fa606te.md (606te_mult1): Update attribute change.
(606te_mult2): Likewise.
(606te_mult3): Likewise.
(606te_mult4): Likewise.
* config/arm/cortex-a9.md (cortex_a9_mult16): Update attribute change.
(cortex_a9_mac16): Likewise.
(cortex_a9_multiply): Likewise.
(cortex_a9_mac): Likewise.
(cortex_a9_multiply_long): Likewise.
* config/arm/fa626te.md (626te_mult1): Update attribute change.
(626te_mult2): Likewise.
(626te_mult3): Likewise.
(626te_mult4): Likewise.
2013-06-18 Richard Biener <rguenther@suse.de>
PR lto/57334
......
gcc/config/arm/arm-generic.md
......@@ -114,7 +114,9 @@
(define_insn_reservation "mult" 16
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "no") (eq_attr "type" "mult")))
(and (eq_attr "ldsched" "no")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))
"core*16")
(define_insn_reservation "mult_ldsched_strongarm" 3
......@@ -122,7 +124,8 @@
(and (eq_attr "ldsched" "yes")
(and (eq_attr "tune"
"strongarm,strongarm110,strongarm1100,strongarm1110")
(eq_attr "type" "mult"))))
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes")))))
"core*2")
(define_insn_reservation "mult_ldsched" 4
......@@ -130,13 +133,17 @@
(and (eq_attr "ldsched" "yes")
(and (eq_attr "tune"
"!strongarm,strongarm110,strongarm1100,strongarm1110")
(eq_attr "type" "mult"))))
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes")))))
"core*4")
(define_insn_reservation "multi_cycle" 32
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "core_cycles" "multi")
(eq_attr "type" "!mult,load_byte,load1,load2,load3,load4,store1,store2,store3,store4")))
(and (eq_attr "type" "!load_byte,load1,load2,load3,load4,\
store1,store2,store3,store4")
(not (ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))))
"core*32")
(define_insn_reservation "single_cycle" 1
......
gcc/config/arm/arm.md
......@@ -250,7 +250,7 @@
;; scheduling information.
(define_attr "insn"
"mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,sat,other"
"mov,mvn,clz,mrs,msr,xtab,sat,other"
(const_string "other"))
; TYPE attribute is used to detect floating point instructions which, if
......@@ -274,7 +274,6 @@
; regs, but has a source operand shifted by a constant
; alu_shift_reg any data instruction that doesn't hit memory or fp
; regs, but has a source operand shifted by a register value
; mult a multiply instruction
; block blockage insn, this blocks all functional units
; float a floating point arithmetic operation (subject to expansion)
; fdivd DFmode floating point division
......@@ -304,7 +303,6 @@
simple_alu_shift,\
alu_shift,\
alu_shift_reg,\
mult,\
block,\
float,\
fdivd,\
......@@ -348,18 +346,57 @@
ffarithd,\
fcmps,\
fcmpd,\
fcpys"
fcpys,\
smulxy,\
smlaxy,\
smlalxy,\
smulwy,\
smlawx,\
mul,\
muls,\
mla,\
mlas,\
umull,\
umulls,\
umlal,\
umlals,\
smull,\
smulls,\
smlal,\
smlals,\
smlawy,\
smuad,\
smuadx,\
smlad,\
smladx,\
smusd,\
smusdx,\
smlsd,\
smlsdx,\
smmul,\
smmulr,\
smmla,\
umaal,\
smlald,\
smlsld,\
sdiv,\
udiv"
(const_string "alu_reg"))
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
(define_attr "mul32" "no,yes"
(if_then_else
(eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,\
umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
(const_string "mult")
(const_string "alu_reg")))
(eq_attr "type"
"smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\
smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld")
(const_string "yes")
(const_string "no")))
; Is this an (integer side) multiply with a 64-bit result?
(define_attr "mul64" "no,yes"
(if_then_else
(eq_attr "insn"
"smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
(eq_attr "type"
"smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals")
(const_string "yes")
(const_string "no")))
......@@ -1484,7 +1521,7 @@
(match_operand:SI 1 "s_register_operand" "%0,r")))]
"TARGET_32BIT && !arm_arch6"
"mul%?\\t%0, %2, %1"
[(set_attr "insn" "mul")
[(set_attr "type" "mul")
(set_attr "predicable" "yes")]
)
......@@ -1494,7 +1531,7 @@
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_32BIT && arm_arch6"
"mul%?\\t%0, %1, %2"
[(set_attr "insn" "mul")
[(set_attr "type" "mul")
(set_attr "predicable" "yes")]
)
......@@ -1515,7 +1552,7 @@
return \"mul\\t%0, %2\";
"
[(set_attr "length" "4,4,2")
(set_attr "insn" "mul")]
(set_attr "type" "muls")]
)
(define_insn "*thumb_mulsi3_v6"
......@@ -1528,7 +1565,7 @@
mul\\t%0, %1
mul\\t%0, %1"
[(set_attr "length" "2")
(set_attr "insn" "mul")]
(set_attr "type" "muls")]
)
(define_insn "*mulsi3_compare0"
......@@ -1542,7 +1579,7 @@
"TARGET_ARM && !arm_arch6"
"mul%.\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "insn" "muls")]
(set_attr "type" "muls")]
)
(define_insn "*mulsi3_compare0_v6"
......@@ -1556,7 +1593,7 @@
"TARGET_ARM && arm_arch6 && optimize_size"
"mul%.\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "insn" "muls")]
(set_attr "type" "muls")]
)
(define_insn "*mulsi_compare0_scratch"
......@@ -1569,7 +1606,7 @@
"TARGET_ARM && !arm_arch6"
"mul%.\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "insn" "muls")]
(set_attr "type" "muls")]
)
(define_insn "*mulsi_compare0_scratch_v6"
......@@ -1582,7 +1619,7 @@
"TARGET_ARM && arm_arch6 && optimize_size"
"mul%.\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "insn" "muls")]
(set_attr "type" "muls")]
)
;; Unnamed templates to match MLA instruction.
......@@ -1595,7 +1632,7 @@
(match_operand:SI 3 "s_register_operand" "r,r,0,0")))]
"TARGET_32BIT && !arm_arch6"
"mla%?\\t%0, %2, %1, %3"
[(set_attr "insn" "mla")
[(set_attr "type" "mla")
(set_attr "predicable" "yes")]
)
......@@ -1607,7 +1644,7 @@
(match_operand:SI 3 "s_register_operand" "r")))]
"TARGET_32BIT && arm_arch6"
"mla%?\\t%0, %2, %1, %3"
[(set_attr "insn" "mla")
[(set_attr "type" "mla")
(set_attr "predicable" "yes")]
)
......@@ -1625,7 +1662,7 @@
"TARGET_ARM && arm_arch6"
"mla%.\\t%0, %2, %1, %3"
[(set_attr "conds" "set")
(set_attr "insn" "mlas")]
(set_attr "type" "mlas")]
)
(define_insn "*mulsi3addsi_compare0_v6"
......@@ -1642,7 +1679,7 @@
"TARGET_ARM && arm_arch6 && optimize_size"
"mla%.\\t%0, %2, %1, %3"
[(set_attr "conds" "set")
(set_attr "insn" "mlas")]
(set_attr "type" "mlas")]
)
(define_insn "*mulsi3addsi_compare0_scratch"
......@@ -1657,7 +1694,7 @@
"TARGET_ARM && !arm_arch6"
"mla%.\\t%0, %2, %1, %3"
[(set_attr "conds" "set")
(set_attr "insn" "mlas")]
(set_attr "type" "mlas")]
)
(define_insn "*mulsi3addsi_compare0_scratch_v6"
......@@ -1672,7 +1709,7 @@
"TARGET_ARM && arm_arch6 && optimize_size"
"mla%.\\t%0, %2, %1, %3"
[(set_attr "conds" "set")
(set_attr "insn" "mlas")]
(set_attr "type" "mlas")]
)
(define_insn "*mulsi3subsi"
......@@ -1683,7 +1720,7 @@
(match_operand:SI 1 "s_register_operand" "r"))))]
"TARGET_32BIT && arm_arch_thumb2"
"mls%?\\t%0, %2, %1, %3"
[(set_attr "insn" "mla")
[(set_attr "type" "mla")
(set_attr "predicable" "yes")]
)
......@@ -1706,7 +1743,7 @@
(match_operand:DI 1 "s_register_operand" "0")))]
"TARGET_32BIT && arm_arch3m && !arm_arch6"
"smlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "insn" "smlal")
[(set_attr "type" "smlal")
(set_attr "predicable" "yes")]
)
......@@ -1719,7 +1756,7 @@
(match_operand:DI 1 "s_register_operand" "0")))]
"TARGET_32BIT && arm_arch6"
"smlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "insn" "smlal")
[(set_attr "type" "smlal")
(set_attr "predicable" "yes")]
)
......@@ -1745,7 +1782,7 @@
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
"TARGET_32BIT && arm_arch3m && !arm_arch6"
"smull%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "smull")
[(set_attr "type" "smull")
(set_attr "predicable" "yes")]
)
......@@ -1756,7 +1793,7 @@
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
"TARGET_32BIT && arm_arch6"
"smull%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "smull")
[(set_attr "type" "smull")
(set_attr "predicable" "yes")]
)
......@@ -1776,7 +1813,7 @@
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
"TARGET_32BIT && arm_arch3m && !arm_arch6"
"umull%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "umull")
[(set_attr "type" "umull")
(set_attr "predicable" "yes")]
)
......@@ -1787,7 +1824,7 @@
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
"TARGET_32BIT && arm_arch6"
"umull%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "umull")
[(set_attr "type" "umull")
(set_attr "predicable" "yes")]
)
......@@ -1810,7 +1847,7 @@
(match_operand:DI 1 "s_register_operand" "0")))]
"TARGET_32BIT && arm_arch3m && !arm_arch6"
"umlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "insn" "umlal")
[(set_attr "type" "umlal")
(set_attr "predicable" "yes")]
)
......@@ -1823,7 +1860,7 @@
(match_operand:DI 1 "s_register_operand" "0")))]
"TARGET_32BIT && arm_arch6"
"umlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "insn" "umlal")
[(set_attr "type" "umlal")
(set_attr "predicable" "yes")]
)
......@@ -1852,7 +1889,7 @@
(clobber (match_scratch:SI 3 "=&r,&r"))]
"TARGET_32BIT && arm_arch3m && !arm_arch6"
"smull%?\\t%3, %0, %2, %1"
[(set_attr "insn" "smull")
[(set_attr "type" "smull")
(set_attr "predicable" "yes")]
)
......@@ -1867,7 +1904,7 @@
(clobber (match_scratch:SI 3 "=r"))]
"TARGET_32BIT && arm_arch6"
"smull%?\\t%3, %0, %2, %1"
[(set_attr "insn" "smull")
[(set_attr "type" "smull")
(set_attr "predicable" "yes")]
)
......@@ -1896,7 +1933,7 @@
(clobber (match_scratch:SI 3 "=&r,&r"))]
"TARGET_32BIT && arm_arch3m && !arm_arch6"
"umull%?\\t%3, %0, %2, %1"
[(set_attr "insn" "umull")
[(set_attr "type" "umull")
(set_attr "predicable" "yes")]
)
......@@ -1911,7 +1948,7 @@
(clobber (match_scratch:SI 3 "=r"))]
"TARGET_32BIT && arm_arch6"
"umull%?\\t%3, %0, %2, %1"
[(set_attr "insn" "umull")
[(set_attr "type" "umull")
(set_attr "predicable" "yes")]
)
......@@ -1923,7 +1960,7 @@
(match_operand:HI 2 "s_register_operand" "r"))))]
"TARGET_DSP_MULTIPLY"
"smulbb%?\\t%0, %1, %2"
[(set_attr "insn" "smulxy")
[(set_attr "type" "smulxy")
(set_attr "predicable" "yes")]
)
......@@ -1936,7 +1973,7 @@
(match_operand:HI 2 "s_register_operand" "r"))))]
"TARGET_DSP_MULTIPLY"
"smultb%?\\t%0, %1, %2"
[(set_attr "insn" "smulxy")
[(set_attr "type" "smulxy")
(set_attr "predicable" "yes")]
)
......@@ -1949,7 +1986,7 @@
(const_int 16))))]
"TARGET_DSP_MULTIPLY"
"smulbt%?\\t%0, %1, %2"
[(set_attr "insn" "smulxy")
[(set_attr "type" "smulxy")
(set_attr "predicable" "yes")]
)
......@@ -1963,7 +2000,7 @@
(const_int 16))))]
"TARGET_DSP_MULTIPLY"
"smultt%?\\t%0, %1, %2"
[(set_attr "insn" "smulxy")
[(set_attr "type" "smulxy")
(set_attr "predicable" "yes")]
)
......@@ -1976,7 +2013,7 @@
(match_operand:SI 3 "s_register_operand" "r")))]
"TARGET_DSP_MULTIPLY"
"smlabb%?\\t%0, %1, %2, %3"
[(set_attr "insn" "smlaxy")
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")]
)
......@@ -1991,7 +2028,7 @@
(match_operand:SI 3 "s_register_operand" "r")))]
"TARGET_DSP_MULTIPLY"
"smlatb%?\\t%0, %1, %2, %3"
[(set_attr "insn" "smlaxy")
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")]
)
......@@ -2006,7 +2043,7 @@
(match_operand:SI 3 "s_register_operand" "r")))]
"TARGET_DSP_MULTIPLY"
"smlatt%?\\t%0, %1, %2, %3"
[(set_attr "insn" "smlaxy")
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")]
)
......@@ -2020,7 +2057,7 @@
(match_operand:DI 3 "s_register_operand" "0")))]
"TARGET_DSP_MULTIPLY"
"smlalbb%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "smlalxy")
[(set_attr "type" "smlalxy")
(set_attr "predicable" "yes")])
;; Note: there is no maddhidi4ibt because this one is canonical form
......@@ -2036,7 +2073,7 @@
(match_operand:DI 3 "s_register_operand" "0")))]
"TARGET_DSP_MULTIPLY"
"smlaltb%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "smlalxy")
[(set_attr "type" "smlalxy")
(set_attr "predicable" "yes")])
(define_insn "*maddhidi4tt"
......@@ -2053,7 +2090,7 @@
(match_operand:DI 3 "s_register_operand" "0")))]
"TARGET_DSP_MULTIPLY"
"smlaltt%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "smlalxy")
[(set_attr "type" "smlalxy")
(set_attr "predicable" "yes")])
(define_expand "mulsf3"
......@@ -4584,7 +4621,7 @@
"TARGET_IDIV"
"sdiv%?\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "insn" "sdiv")]
(set_attr "type" "sdiv")]
)
(define_insn "udivsi3"
......@@ -4594,7 +4631,7 @@
"TARGET_IDIV"
"udiv%?\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "insn" "udiv")]
(set_attr "type" "udiv")]
)
......
gcc/config/arm/arm1020e.md
......@@ -96,7 +96,7 @@
;; until after the memory stage.
(define_insn_reservation "1020mult1" 2
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "insn" "smulxy,smulwy"))
(eq_attr "type" "smulxy,smulwy"))
"1020a_e,1020a_m,1020a_w")
;; The "smlaxy" and "smlawx" instructions require two iterations through
......@@ -104,7 +104,7 @@
;; the execute stage.
(define_insn_reservation "1020mult2" 2
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "insn" "smlaxy,smlalxy,smlawx"))
(eq_attr "type" "smlaxy,smlalxy,smlawx"))
"1020a_e*2,1020a_m,1020a_w")
;; The "smlalxy", "mul", and "mla" instructions require two iterations
......@@ -112,7 +112,7 @@
;; the memory stage.
(define_insn_reservation "1020mult3" 3
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "insn" "smlalxy,mul,mla"))
(eq_attr "type" "smlalxy,mul,mla"))
"1020a_e*2,1020a_m,1020a_w")
;; The "muls" and "mlas" instructions loop in the execute stage for
......@@ -120,7 +120,7 @@
;; available after three iterations.
(define_insn_reservation "1020mult4" 3
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "insn" "muls,mlas"))
(eq_attr "type" "muls,mlas"))
"1020a_e*4,1020a_m,1020a_w")
;; Long multiply instructions that produce two registers of
......@@ -135,7 +135,7 @@
;; available after the memory cycle.
(define_insn_reservation "1020mult5" 4
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "insn" "umull,umlal,smull,smlal"))
(eq_attr "type" "umull,umlal,smull,smlal"))
"1020a_e*3,1020a_m,1020a_w")
;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
......@@ -143,7 +143,7 @@
;; The value result is available after four iterations.
(define_insn_reservation "1020mult6" 4
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "insn" "umulls,umlals,smulls,smlals"))
(eq_attr "type" "umulls,umlals,smulls,smlals"))
"1020a_e*5,1020a_m,1020a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/arm1026ejs.md
......@@ -96,7 +96,7 @@
;; until after the memory stage.
(define_insn_reservation "mult1" 2
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "insn" "smulxy,smulwy"))
(eq_attr "type" "smulxy,smulwy"))
"a_e,a_m,a_w")
;; The "smlaxy" and "smlawx" instructions require two iterations through
......@@ -104,7 +104,7 @@
;; the execute stage.
(define_insn_reservation "mult2" 2
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "insn" "smlaxy,smlalxy,smlawx"))
(eq_attr "type" "smlaxy,smlalxy,smlawx"))
"a_e*2,a_m,a_w")
;; The "smlalxy", "mul", and "mla" instructions require two iterations
......@@ -112,7 +112,7 @@
;; the memory stage.
(define_insn_reservation "mult3" 3
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "insn" "smlalxy,mul,mla"))
(eq_attr "type" "smlalxy,mul,mla"))
"a_e*2,a_m,a_w")
;; The "muls" and "mlas" instructions loop in the execute stage for
......@@ -120,7 +120,7 @@
;; available after three iterations.
(define_insn_reservation "mult4" 3
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "insn" "muls,mlas"))
(eq_attr "type" "muls,mlas"))
"a_e*4,a_m,a_w")
;; Long multiply instructions that produce two registers of
......@@ -135,7 +135,7 @@
;; available after the memory cycle.
(define_insn_reservation "mult5" 4
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "insn" "umull,umlal,smull,smlal"))
(eq_attr "type" "umull,umlal,smull,smlal"))
"a_e*3,a_m,a_w")
;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
......@@ -143,7 +143,7 @@
;; The value result is available after four iterations.
(define_insn_reservation "mult6" 4
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "insn" "umulls,umlals,smulls,smlals"))
(eq_attr "type" "umulls,umlals,smulls,smlals"))
"a_e*5,a_m,a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/arm1136jfs.md
......@@ -129,13 +129,13 @@
;; Multiply and multiply-accumulate results are available after four stages.
(define_insn_reservation "11_mult1" 4
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "insn" "mul,mla"))
(eq_attr "type" "mul,mla"))
"e_1*2,e_2,e_3,e_wb")
;; The *S variants set the condition flags, which requires three more cycles.
(define_insn_reservation "11_mult2" 4
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "insn" "muls,mlas"))
(eq_attr "type" "muls,mlas"))
"e_1*2,e_2,e_3,e_wb")
(define_bypass 3 "11_mult1,11_mult2"
......@@ -160,13 +160,13 @@
;; the two multiply-accumulate instructions.
(define_insn_reservation "11_mult3" 5
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "insn" "smull,umull,smlal,umlal"))
(eq_attr "type" "smull,umull,smlal,umlal"))
"e_1*3,e_2,e_3,e_wb*2")
;; The *S variants set the condition flags, which requires three more cycles.
(define_insn_reservation "11_mult4" 5
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "insn" "smulls,umulls,smlals,umlals"))
(eq_attr "type" "smulls,umulls,smlals,umlals"))
"e_1*3,e_2,e_3,e_wb*2")
(define_bypass 4 "11_mult3,11_mult4"
......@@ -190,7 +190,8 @@
;; cycles.
(define_insn_reservation "11_mult5" 3
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "insn" "smulxy,smlaxy,smulwy,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx"))
(eq_attr "type" "smulxy,smlaxy,smulwy,smlawy,smuad,smuadx,smlad,smladx,\
smusd,smusdx,smlsd,smlsdx"))
"e_1,e_2,e_3,e_wb")
(define_bypass 2 "11_mult5"
......@@ -211,14 +212,14 @@
;; The same idea, then the 32-bit result is added to a 64-bit quantity.
(define_insn_reservation "11_mult6" 4
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "insn" "smlalxy"))
(eq_attr "type" "smlalxy"))
"e_1*2,e_2,e_3,e_wb*2")
;; Signed 32x32 multiply, then the most significant 32 bits are extracted
;; and are available after the memory stage.
(define_insn_reservation "11_mult7" 4
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "insn" "smmul,smmulr"))
(eq_attr "type" "smmul,smmulr"))
"e_1*2,e_2,e_3,e_wb")
(define_bypass 3 "11_mult6,11_mult7"
......
gcc/config/arm/arm926ejs.md
......@@ -81,32 +81,32 @@
(define_insn_reservation "9_mult1" 3
(and (eq_attr "tune" "arm926ejs")
(eq_attr "insn" "smlalxy,mul,mla"))
(eq_attr "type" "smlalxy,mul,mla"))
"e*2,m,w")
(define_insn_reservation "9_mult2" 4
(and (eq_attr "tune" "arm926ejs")
(eq_attr "insn" "muls,mlas"))
(eq_attr "type" "muls,mlas"))
"e*3,m,w")
(define_insn_reservation "9_mult3" 4
(and (eq_attr "tune" "arm926ejs")
(eq_attr "insn" "umull,umlal,smull,smlal"))
(eq_attr "type" "umull,umlal,smull,smlal"))
"e*3,m,w")
(define_insn_reservation "9_mult4" 5
(and (eq_attr "tune" "arm926ejs")
(eq_attr "insn" "umulls,umlals,smulls,smlals"))
(eq_attr "type" "umulls,umlals,smulls,smlals"))
"e*4,m,w")
(define_insn_reservation "9_mult5" 2
(and (eq_attr "tune" "arm926ejs")
(eq_attr "insn" "smulxy,smlaxy,smlawx"))
(eq_attr "type" "smulxy,smlaxy,smlawx"))
"e,m,w")
(define_insn_reservation "9_mult6" 3
(and (eq_attr "tune" "arm926ejs")
(eq_attr "insn" "smlalxy"))
(eq_attr "type" "smlalxy"))
"e*2,m,w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/cortex-a15.md
......@@ -87,28 +87,26 @@
;; 32-bit multiplies
(define_insn_reservation "cortex_a15_mult32" 3
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "mult")
(and (eq_attr "neon_type" "none")
(eq_attr "mul64" "no"))))
(and (eq_attr "mul32" "yes")
(eq_attr "neon_type" "none")))
"ca15_issue1,ca15_mx")
;; 64-bit multiplies
(define_insn_reservation "cortex_a15_mult64" 4
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "mult")
(and (eq_attr "neon_type" "none")
(eq_attr "mul64" "yes"))))
(and (eq_attr "mul64" "yes")
(eq_attr "neon_type" "none")))
"ca15_issue1,ca15_mx*2")
;; Integer divide
(define_insn_reservation "cortex_a15_udiv" 9
(and (eq_attr "tune" "cortexa15")
(eq_attr "insn" "udiv"))
(eq_attr "type" "udiv"))
"ca15_issue1,ca15_mx")
(define_insn_reservation "cortex_a15_sdiv" 10
(and (eq_attr "tune" "cortexa15")
(eq_attr "insn" "sdiv"))
(eq_attr "type" "sdiv"))
"ca15_issue1,ca15_mx")
;; Block all issue pipes for a cycle
......
gcc/config/arm/cortex-a5.md
......@@ -80,7 +80,8 @@
(define_insn_reservation "cortex_a5_mul" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "mult"))
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes")))
"cortex_a5_ex1")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/cortex-a53.md
......@@ -89,7 +89,8 @@
(define_insn_reservation "cortex_a53_mul" 3
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "mult"))
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes")))
"cortex_a53_single_issue")
;; A multiply with a single-register result or an MLA, followed by an
......@@ -103,12 +104,12 @@
;; Punt with a high enough latency for divides.
(define_insn_reservation "cortex_a53_udiv" 8
(and (eq_attr "tune" "cortexa53")
(eq_attr "insn" "udiv"))
(eq_attr "type" "udiv"))
"(cortex_a53_slot0+cortex_a53_idiv),cortex_a53_idiv*7")
(define_insn_reservation "cortex_a53_sdiv" 9
(and (eq_attr "tune" "cortexa53")
(eq_attr "insn" "sdiv"))
(eq_attr "type" "sdiv"))
"(cortex_a53_slot0+cortex_a53_idiv),cortex_a53_idiv*8")
......
gcc/config/arm/cortex-a7.md
......@@ -127,8 +127,9 @@
(define_insn_reservation "cortex_a7_mul" 2
(and (eq_attr "tune" "cortexa7")
(and (eq_attr "type" "mult")
(eq_attr "neon_type" "none")))
(and (eq_attr "neon_type" "none")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))
"cortex_a7_both")
;; Forward the result of a multiply operation to the accumulator
......@@ -140,7 +141,7 @@
;; The latency depends on the operands, so we use an estimate here.
(define_insn_reservation "cortex_a7_idiv" 5
(and (eq_attr "tune" "cortexa7")
(eq_attr "insn" "udiv,sdiv"))
(eq_attr "type" "udiv,sdiv"))
"cortex_a7_both*5")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/cortex-a8.md
......@@ -139,22 +139,22 @@
(define_insn_reservation "cortex_a8_mul" 6
(and (eq_attr "tune" "cortexa8")
(eq_attr "insn" "mul,smulxy,smmul"))
(eq_attr "type" "mul,smulxy,smmul"))
"cortex_a8_multiply_2")
(define_insn_reservation "cortex_a8_mla" 6
(and (eq_attr "tune" "cortexa8")
(eq_attr "insn" "mla,smlaxy,smlawy,smmla,smlad,smlsd"))
(eq_attr "type" "mla,smlaxy,smlawy,smmla,smlad,smlsd"))
"cortex_a8_multiply_2")
(define_insn_reservation "cortex_a8_mull" 7
(and (eq_attr "tune" "cortexa8")
(eq_attr "insn" "smull,umull,smlal,umlal,umaal,smlalxy"))
(eq_attr "type" "smull,umull,smlal,umlal,umaal,smlalxy"))
"cortex_a8_multiply_3")
(define_insn_reservation "cortex_a8_smulwy" 5
(and (eq_attr "tune" "cortexa8")
(eq_attr "insn" "smulwy,smuad,smusd"))
(eq_attr "type" "smulwy,smuad,smusd"))
"cortex_a8_multiply")
;; smlald and smlsld are multiply-accumulate instructions but do not
......@@ -162,7 +162,7 @@
;; cannot go in cortex_a8_mla above. (See below for bypass details.)
(define_insn_reservation "cortex_a8_smlald" 6
(and (eq_attr "tune" "cortexa8")
(eq_attr "insn" "smlald,smlsld"))
(eq_attr "type" "smlald,smlsld"))
"cortex_a8_multiply_2")
;; A multiply with a single-register result or an MLA, followed by an
......
gcc/config/arm/cortex-a9.md
......@@ -130,29 +130,29 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
;; We get 16*16 multiply / mac results in 3 cycles.
(define_insn_reservation "cortex_a9_mult16" 3
(and (eq_attr "tune" "cortexa9")
(eq_attr "insn" "smulxy"))
(eq_attr "type" "smulxy"))
"cortex_a9_mult16")
;; The 16*16 mac is slightly different that it
;; reserves M1 and M2 in the same cycle.
(define_insn_reservation "cortex_a9_mac16" 3
(and (eq_attr "tune" "cortexa9")
(eq_attr "insn" "smlaxy"))
(eq_attr "type" "smlaxy"))
"cortex_a9_mac16")
(define_insn_reservation "cortex_a9_multiply" 4
(and (eq_attr "tune" "cortexa9")
(eq_attr "insn" "mul,smmul,smmulr"))
(eq_attr "type" "mul,smmul,smmulr"))
"cortex_a9_mult")
(define_insn_reservation "cortex_a9_mac" 4
(and (eq_attr "tune" "cortexa9")
(eq_attr "insn" "mla,smmla"))
(eq_attr "type" "mla,smmla"))
"cortex_a9_mac")
(define_insn_reservation "cortex_a9_multiply_long" 5
(and (eq_attr "tune" "cortexa9")
(eq_attr "insn" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
(eq_attr "type" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
"cortex_a9_mult_long")
;; An instruction with a result in E2 can be forwarded
......
gcc/config/arm/cortex-m4.md
......@@ -31,7 +31,10 @@
;; ALU and multiply is one cycle.
(define_insn_reservation "cortex_m4_alu" 1
(and (eq_attr "tune" "cortexm4")
(eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg,mult"))
(ior (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,\
alu_shift,alu_shift_reg")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))
"cortex_m4_ex")
;; Byte, half-word and word load is two cycles.
......
gcc/config/arm/cortex-r4.md
......@@ -128,32 +128,32 @@
(define_insn_reservation "cortex_r4_mul_4" 4
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "insn" "mul,smmul"))
(eq_attr "type" "mul,smmul"))
"cortex_r4_mul_2")
(define_insn_reservation "cortex_r4_mul_3" 3
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "insn" "smulxy,smulwy,smuad,smusd"))
(eq_attr "type" "smulxy,smulwy,smuad,smusd"))
"cortex_r4_mul")
(define_insn_reservation "cortex_r4_mla_4" 4
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "insn" "mla,smmla"))
(eq_attr "type" "mla,smmla"))
"cortex_r4_mul_2")
(define_insn_reservation "cortex_r4_mla_3" 3
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "insn" "smlaxy,smlawy,smlad,smlsd"))
(eq_attr "type" "smlaxy,smlawy,smlad,smlsd"))
"cortex_r4_mul")
(define_insn_reservation "cortex_r4_smlald" 3
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "insn" "smlald,smlsld"))
(eq_attr "type" "smlald,smlsld"))
"cortex_r4_mul")
(define_insn_reservation "cortex_r4_mull" 4
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "insn" "smull,umull,umlal,umaal"))
(eq_attr "type" "smull,umull,umlal,umaal"))
"cortex_r4_mul_2")
;; A multiply or an MLA with a single-register result, followed by an
......@@ -196,12 +196,12 @@
;; This gives a latency of nine for udiv and ten for sdiv.
(define_insn_reservation "cortex_r4_udiv" 9
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "insn" "udiv"))
(eq_attr "type" "udiv"))
"cortex_r4_div_9")
(define_insn_reservation "cortex_r4_sdiv" 10
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "insn" "sdiv"))
(eq_attr "type" "sdiv"))
"cortex_r4_div_10")
;; Branches. We assume correct prediction.
......
gcc/config/arm/fa526.md
......@@ -76,12 +76,12 @@
(define_insn_reservation "526_mult1" 2
(and (eq_attr "tune" "fa526")
(eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy"))
(eq_attr "type" "smlalxy,smulxy,smlaxy,smlalxy"))
"fa526_core")
(define_insn_reservation "526_mult2" 5
(and (eq_attr "tune" "fa526")
(eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\
(eq_attr "type" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\
umlals,smulls,smlals,smlawx"))
"fa526_core*4")
......
gcc/config/arm/fa606te.md
......@@ -71,22 +71,22 @@
(define_insn_reservation "606te_mult1" 2
(and (eq_attr "tune" "fa606te")
(eq_attr "insn" "smlalxy"))
(eq_attr "type" "smlalxy"))
"fa606te_core")
(define_insn_reservation "606te_mult2" 3
(and (eq_attr "tune" "fa606te")
(eq_attr "insn" "smlaxy,smulxy,smulwy,smlawy"))
(eq_attr "type" "smlaxy,smulxy,smulwy,smlawy"))
"fa606te_core*2")
(define_insn_reservation "606te_mult3" 4
(and (eq_attr "tune" "fa606te")
(eq_attr "insn" "mul,mla,muls,mlas"))
(eq_attr "type" "mul,mla,muls,mlas"))
"fa606te_core*3")
(define_insn_reservation "606te_mult4" 5
(and (eq_attr "tune" "fa606te")
(eq_attr "insn" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals"))
(eq_attr "type" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals"))
"fa606te_core*4")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/fa626te.md
......@@ -82,22 +82,22 @@
(define_insn_reservation "626te_mult1" 2
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "insn" "smulwy,smlawy,smulxy,smlaxy"))
(eq_attr "type" "smulwy,smlawy,smulxy,smlaxy"))
"fa626te_core")
(define_insn_reservation "626te_mult2" 2
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "insn" "mul,mla"))
(eq_attr "type" "mul,mla"))
"fa626te_core")
(define_insn_reservation "626te_mult3" 3
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "insn" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx"))
(eq_attr "type" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx"))
"fa626te_core*2")
(define_insn_reservation "626te_mult4" 4
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "insn" "smulls,smlals,umulls,umlals"))
(eq_attr "type" "smulls,smlals,umulls,umlals"))
"fa626te_core*3")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/fa726te.md
......@@ -115,7 +115,7 @@
(define_insn_reservation "726te_mult_op" 3
(and (eq_attr "tune" "fa726te")
(eq_attr "insn" "smlalxy,mul,mla,muls,mlas,umull,umlal,smull,smlal,\
(eq_attr "type" "smlalxy,mul,mla,muls,mlas,umull,umlal,smull,smlal,\
umulls,umlals,smulls,smlals,smlawx,smulxy,smlaxy"))
"fa726te_issue+fa726te_mac_pipe")
......
gcc/config/arm/fmp626.md
......@@ -77,22 +77,22 @@
(define_insn_reservation "mp626_mult1" 2
(and (eq_attr "tune" "fmp626")
(eq_attr "insn" "smulwy,smlawy,smulxy,smlaxy"))
(eq_attr "type" "smulwy,smlawy,smulxy,smlaxy"))
"fmp626_core")
(define_insn_reservation "mp626_mult2" 2
(and (eq_attr "tune" "fmp626")
(eq_attr "insn" "mul,mla"))
(eq_attr "type" "mul,mla"))
"fmp626_core")
(define_insn_reservation "mp626_mult3" 3
(and (eq_attr "tune" "fmp626")
(eq_attr "insn" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx"))
(eq_attr "type" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx"))
"fmp626_core*2")
(define_insn_reservation "mp626_mult4" 4
(and (eq_attr "tune" "fmp626")
(eq_attr "insn" "smulls,smlals,umulls,umlals"))
(eq_attr "type" "smulls,smlals,umulls,umlals"))
"fmp626_core*3")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/marvell-pj4.md
......@@ -95,10 +95,14 @@
"pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
(define_insn_reservation "pj4_ir_mul" 3
(and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "mult")) "pj4_is,pj4_mul,nothing*2,pj4_cp")
(and (eq_attr "tune" "marvell_pj4")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes")))
"pj4_is,pj4_mul,nothing*2,pj4_cp")
(define_insn_reservation "pj4_ir_div" 20
(and (eq_attr "tune" "marvell_pj4") (eq_attr "insn" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp")
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp")
;; Branches and calls.
......
gcc/config/arm/thumb2.md
......@@ -1063,7 +1063,7 @@
"mul%!\\t%0, %2, %0"
[(set_attr "predicable" "yes")
(set_attr "length" "2")
(set_attr "insn" "muls")])
(set_attr "type" "muls")])
(define_insn "*thumb2_mulsi_short_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
......@@ -1076,7 +1076,7 @@
"TARGET_THUMB2 && optimize_size"
"muls\\t%0, %2, %0"
[(set_attr "length" "2")
(set_attr "insn" "muls")])
(set_attr "type" "muls")])
(define_insn "*thumb2_mulsi_short_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
......@@ -1088,7 +1088,7 @@
"TARGET_THUMB2 && optimize_size"
"muls\\t%0, %2, %0"
[(set_attr "length" "2")
(set_attr "insn" "muls")])
(set_attr "type" "muls")])
(define_insn "*thumb2_cbz"
[(set (pc) (if_then_else
......
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