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riscv-gcc-1
Commit 07c0852e by Uros Bizjak
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i386.md (attribute isa): New. 

	* config/i386/i386.md (attribute isa): New.
	(attribute enabled): New.
	(setcc_<mode>_sse): Merge from *{avx,sse}_setcc<mode>.
	(*fop_<mode>_comm_mixed): Merge with *fop_<mode>_comm_mixed_avx.
	(*fop_<mode>_comm_sse): Merge with *fop_<mode>_comm_avx.
	(*fop_<mode>_1_mixed): Merge with *fop_<mode>_1_mixed_avx.
	(*fop_<mode>_1_sse): Merge with *fop_<mode>_1_avx.
	(<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
	(*ieee_smin<mode>3): Merge with *avx_ieee_smin<mode>3.
	(*ieee_smax<mode>3): Merge with *avx_ieee_smax<mode>3.

	* config/i386/sse.md (VF): New mode iterator.
	(VF1): Ditto.
	(VF2): Ditto.
	(VF_128): Ditto.
	(SSEMODEF4): Remove.
	(attribute sse): Handle V8SF and V4DF modes.
	(<absneg:code><mode>2): Use VF mode iterator.
	(*absneg<mode>2): Merge from *{avx,sse}_absneg<mode>2.  Use VF
	mode iterator.
	(<plusminus_insn><mode>3): Use VF mode iterator.
	(*<plusminus_insn><mode>3): Merge with *avx_<plusminus_insn><mode>3.
	Use VF mode iterator.
	(<sse>_vm<plusminus_insn><mode>3): Merge with
	*avx_vm<plusminus_insn><mode>3.  Use VF_128 mode iterator.
	(mul<mode>3): Use VF mode iterator.
	(*mul<mode>3): Merge with *avx_mul<mode>3.  Use VF mode iterator.
	(<sse>_vmmul<mode>3): Merge with *avx_vmmul<mode>3.  Use VF_128
	mode iterator.
	(div<VF2:mode>3): Merge from divv2df3 and divv4df3.
	(div<VF1:mode>3): Merge from divv4sf3 and divv8sf3.
	(<sse>_div<mode>3): Merge with *avx_div<mode>3.  Use VF mode iterator.
	(<sse>_vmdiv<mode>3): Merge with *avx_vmdiv<mode>3.  Use VF_128
	mode iterator.
	(<sse>_rcp<mode>2): Merge from avx_rcpv8sf2 and sse_rcpv4sf2.
	Use VF1 mode iterator.
	(sse_vmrcpv4sf2): Merge with *avx_vmrcpv4sf2.
	(sqrt<VF2:mode>2): New expander.
	(sqrt<VF1:mode>2): Merge from sqrtv4sf2 and sqrtv8sf2.
	(<sse>_sqrt<mode>2): Merge from avx_sqrtv8sf2, sse_sqrtv4sf, sqrtv4df2
	and sqrtv2df2.  Use VF mode iterator.
	(<sse>_vmsqrt<mode>2): Merge with *avx_vmsqrt<mode>2.  Use VF_128
	mode iterator.
	(rsqrt<VF1:mode>2): Merge from rsqrtv4sf2 and rsqrtv8sf2.
	(<sse>_rsqrt<mode>2): Merge from avx_rsqrtv8sf2 and sse_rsqrt4sf2.
	Use VF1 mode iterator.
	(sse_vmrsqrtv4sf2): Merge with *avx_vmrsqrtv4sf2.
	(<smaxmin:code><mode>3): Use VF mode iterator.
	(*<smaxmin:code><mode>3_finite): Merge with
	*avx_<smaxmin:code><mode>3_finite.  Use VF mode iterator.
	(*<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
	(<sse>_vm<smaxmin:code><mode>2): Merge with
	*avx_vm<smaxmin:code><mode>2.  Use VF_128 mode iterator.
	(*ieee_smin<mode>3): Merge with *avx_ieee_smin<mode>3.  Use VF
	mode iterator.
	(*ieee_smax<mode>3): Merge with *avx_ieee_smax<mode>3.  Use VF
	mode iterator.
	(sse3_addsubv2df3): Merge with *avx_addsubv2df3.
	(sse3_addsubv4sf3): Merge with *avx_addsubv4sf3.
	(sse3_h<plusminus_insn>v2df3): Merge with *avx_h<plusminus_insn>v2df3.
	(sse3_h<plusminus_insn>v4sf3): Merge with *avx_h<plusminus_insn>v4sf3.
	(avx_cmp<mode>3): Rename from avx_cmp<ssemodesuffix><mode>3.  Use
	VF mode iterator.
	(avx_vmcmp<mode>3): Rename from avx_cmp<ssescalarmodesuffix><mode>3.
	Use VF_128 mode iterator.
	(<sse>_maskcmp<mode>3): Merge with *avx_maskcmp<mode>3.  Use VF
	mode iterator.
	(<sse>_vmmaskcmp<mode>3): Merge with *avx_vmmaskcmp<mode>3.  Use
	VF_128 mode iterator.
	(vcond<mode>): Use VF mode iterator.
	* config/i386/predicates.md (sse_comparison_operator): Merge with
	avx_comparison_float_operator.  Do not declare as special_predicate.
	* config/i386/i386.c (struct builtin_description): Update for renamed
	compare patterns.
	(ix86_expand_args_builtin): Ditto.
	(ix86_expand_sse_compare_mask): Ditto.

From-SVN: r172028
parent ff5d142c
Showing with 101 additions and 32 deletions
gcc/ChangeLog
2011-04-06 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (attribute isa): New.
(attribute enabled): New.
(setcc_<mode>_sse): Merge from *{avx,sse}_setcc<mode>.
(*fop_<mode>_comm_mixed): Merge with *fop_<mode>_comm_mixed_avx.
(*fop_<mode>_comm_sse): Merge with *fop_<mode>_comm_avx.
(*fop_<mode>_1_mixed): Merge with *fop_<mode>_1_mixed_avx.
(*fop_<mode>_1_sse): Merge with *fop_<mode>_1_avx.
(<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
(*ieee_smin<mode>3): Merge with *avx_ieee_smin<mode>3.
(*ieee_smax<mode>3): Merge with *avx_ieee_smax<mode>3.
* config/i386/sse.md (VF): New mode iterator.
(VF1): Ditto.
(VF2): Ditto.
(VF_128): Ditto.
(SSEMODEF4): Remove.
(attribute sse): Handle V8SF and V4DF modes.
(<absneg:code><mode>2): Use VF mode iterator.
(*absneg<mode>2): Merge from *{avx,sse}_absneg<mode>2. Use VF
mode iterator.
(<plusminus_insn><mode>3): Use VF mode iterator.
(*<plusminus_insn><mode>3): Merge with *avx_<plusminus_insn><mode>3.
Use VF mode iterator.
(<sse>_vm<plusminus_insn><mode>3): Merge with
*avx_vm<plusminus_insn><mode>3. Use VF_128 mode iterator.
(mul<mode>3): Use VF mode iterator.
(*mul<mode>3): Merge with *avx_mul<mode>3. Use VF mode iterator.
(<sse>_vmmul<mode>3): Merge with *avx_vmmul<mode>3. Use VF_128
mode iterator.
(div<VF2:mode>3): Merge from divv2df3 and divv4df3.
(div<VF1:mode>3): Merge from divv4sf3 and divv8sf3.
(<sse>_div<mode>3): Merge with *avx_div<mode>3. Use VF mode iterator.
(<sse>_vmdiv<mode>3): Merge with *avx_vmdiv<mode>3. Use VF_128
mode iterator.
(<sse>_rcp<mode>2): Merge from avx_rcpv8sf2 and sse_rcpv4sf2.
Use VF1 mode iterator.
(sse_vmrcpv4sf2): Merge with *avx_vmrcpv4sf2.
(sqrt<VF2:mode>2): New expander.
(sqrt<VF1:mode>2): Merge from sqrtv4sf2 and sqrtv8sf2.
(<sse>_sqrt<mode>2): Merge from avx_sqrtv8sf2, sse_sqrtv4sf, sqrtv4df2
and sqrtv2df2. Use VF mode iterator.
(<sse>_vmsqrt<mode>2): Merge with *avx_vmsqrt<mode>2. Use VF_128
mode iterator.
(rsqrt<VF1:mode>2): Merge from rsqrtv4sf2 and rsqrtv8sf2.
(<sse>_rsqrt<mode>2): Merge from avx_rsqrtv8sf2 and sse_rsqrt4sf2.
Use VF1 mode iterator.
(sse_vmrsqrtv4sf2): Merge with *avx_vmrsqrtv4sf2.
(<smaxmin:code><mode>3): Use VF mode iterator.
(*<smaxmin:code><mode>3_finite): Merge with
*avx_<smaxmin:code><mode>3_finite. Use VF mode iterator.
(*<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
(<sse>_vm<smaxmin:code><mode>2): Merge with
*avx_vm<smaxmin:code><mode>2. Use VF_128 mode iterator.
(*ieee_smin<mode>3): Merge with *avx_ieee_smin<mode>3. Use VF
mode iterator.
(*ieee_smax<mode>3): Merge with *avx_ieee_smax<mode>3. Use VF
mode iterator.
(sse3_addsubv2df3): Merge with *avx_addsubv2df3.
(sse3_addsubv4sf3): Merge with *avx_addsubv4sf3.
(sse3_h<plusminus_insn>v2df3): Merge with *avx_h<plusminus_insn>v2df3.
(sse3_h<plusminus_insn>v4sf3): Merge with *avx_h<plusminus_insn>v4sf3.
(avx_cmp<mode>3): Rename from avx_cmp<ssemodesuffix><mode>3. Use
VF mode iterator.
(avx_vmcmp<mode>3): Rename from avx_cmp<ssescalarmodesuffix><mode>3.
Use VF_128 mode iterator.
(<sse>_maskcmp<mode>3): Merge with *avx_maskcmp<mode>3. Use VF
mode iterator.
(<sse>_vmmaskcmp<mode>3): Merge with *avx_vmmaskcmp<mode>3. Use
VF_128 mode iterator.
(vcond<mode>): Use VF mode iterator.
* config/i386/predicates.md (sse_comparison_operator): Merge with
avx_comparison_float_operator. Do not declare as special_predicate.
* config/i386/i386.c (struct builtin_description): Update for renamed
compare patterns.
(ix86_expand_args_builtin): Ditto.
(ix86_expand_sse_compare_mask): Ditto.
2011-04-06 Richard Guenther <rguenther@suse.de> 2011-04-06 Richard Guenther <rguenther@suse.de>
* tree-inline.c (estimate_num_insns): For calls simply account * tree-inline.c (estimate_num_insns): For calls simply account
...@@ -618,7 +697,7 @@ ...@@ -618,7 +697,7 @@
* config.gcc (*-*-mingw*): Allow as option the * config.gcc (*-*-mingw*): Allow as option the
posix threading model. posix threading model.
* config/i386/mingw32.h ( SPEC_PTHREAD1, SPEC_PTHREAD2): * config/i386/mingw32.h (SPEC_PTHREAD1, SPEC_PTHREAD2):
New macros defined dependent to TARGET_USE_PTHREAD_BY_DEFAULT New macros defined dependent to TARGET_USE_PTHREAD_BY_DEFAULT
definition. definition.
(CPP_SPEC): Add pthread/no-pthread handling. (CPP_SPEC): Add pthread/no-pthread handling.
......
gcc/config/i386/i386.c
...@@ -25342,12 +25342,12 @@ static const struct builtin_description bdesc_args[] = ...@@ -25342,12 +25342,12 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
...@@ -26994,12 +26994,12 @@ ix86_expand_args_builtin (const struct builtin_description *d, ...@@ -26994,12 +26994,12 @@ ix86_expand_args_builtin (const struct builtin_description *d,
error ("the last argument must be a 1-bit immediate"); error ("the last argument must be a 1-bit immediate");
return const0_rtx; return const0_rtx;
case CODE_FOR_avx_cmpsdv2df3: case CODE_FOR_avx_vmcmpv2df3:
case CODE_FOR_avx_cmpssv4sf3: case CODE_FOR_avx_vmcmpv4sf3:
case CODE_FOR_avx_cmppdv2df3: case CODE_FOR_avx_cmpv2df3:
case CODE_FOR_avx_cmppsv4sf3: case CODE_FOR_avx_cmpv4sf3:
case CODE_FOR_avx_cmppdv4df3: case CODE_FOR_avx_cmpv4df3:
case CODE_FOR_avx_cmppsv8sf3: case CODE_FOR_avx_cmpv8sf3:
error ("the last argument must be a 5-bit immediate"); error ("the last argument must be a 5-bit immediate");
return const0_rtx; return const0_rtx;
...@@ -32359,6 +32359,7 @@ static rtx ...@@ -32359,6 +32359,7 @@ static rtx
ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1, ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
bool swap_operands) bool swap_operands)
{ {
rtx (*insn)(rtx, rtx, rtx, rtx);
enum machine_mode mode = GET_MODE (op0); enum machine_mode mode = GET_MODE (op0);
rtx mask = gen_reg_rtx (mode); rtx mask = gen_reg_rtx (mode);
...@@ -32369,13 +32370,10 @@ ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1, ...@@ -32369,13 +32370,10 @@ ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
op1 = tmp; op1 = tmp;
} }
if (mode == DFmode) insn = mode == DFmode ? gen_setcc_df_sse : gen_setcc_sf_sse;
emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
gen_rtx_fmt_ee (code, mode, op0, op1)));
else
emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
gen_rtx_fmt_ee (code, mode, op0, op1)));
emit_insn (insn (mask, op0, op1,
gen_rtx_fmt_ee (code, mode, op0, op1)));
return mask; return mask;
} }
gcc/config/i386/predicates.md
...@@ -969,19 +969,11 @@ ...@@ -969,19 +969,11 @@
;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns. ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
;; The first set are supported directly; the second set can't be done with ;; The first set are supported directly; the second set can't be done with
;; full IEEE support, i.e. NaNs. ;; full IEEE support, i.e. NaNs.
;;
;; ??? It would seem that we have a lot of uses of this predicate that pass (define_predicate "sse_comparison_operator"
;; it the wrong mode. We got away with this because the old function didn't (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
;; check the mode at all. Mirror that for now by calling this a special (and (match_code "ge,gt,uneq,unle,unlt,ltgt")
;; predicate. (match_test "TARGET_AVX"))))
(define_special_predicate "sse_comparison_operator"
(match_code "eq,lt,le,unordered,ne,unge,ungt,ordered"))
;; Return true if OP is a comparison operator that can be issued by
;; avx predicate generation instructions
(define_predicate "avx_comparison_float_operator"
(match_code "ne,eq,ge,gt,le,lt,unordered,ordered,uneq,unge,ungt,unle,unlt,ltgt"))
(define_predicate "ix86_comparison_int_operator" (define_predicate "ix86_comparison_int_operator"
(match_code "ne,eq,ge,gt,le,lt")) (match_code "ne,eq,ge,gt,le,lt"))
......
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