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riscv-gcc-1
Commit 065bbfe6 by Jeff Law
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h8300.c (notice_update_cc): Use CC_SET_ZN and CC_SET_ZNV. 

        * h8300.c (notice_update_cc): Use CC_SET_ZN and CC_SET_ZNV.
        (shift_one, shift_two): Set CC_NO_CARRY as needed.  Remove
        references to CC_OVERFLOW_0.
        (emit_a_shift): Similarly.
        * h8300.h (CC_OVERFLOW_0): Remove.
        * h8300.md: Use set_zn and set_znv for cc0 tracking.
        (bCC): Restore the comparison is CC_OVERFLOW_UNUSABLE is set and
        the comparison needs the overflow bits.

From-SVN: r14020
parent d116300b
Showing with 92 additions and 76 deletions
gcc/config/h8300/h8300.c
...@@ -1597,15 +1597,7 @@ notice_update_cc (body, insn) ...@@ -1597,15 +1597,7 @@ notice_update_cc (body, insn)
cc_status.value1 = 0; cc_status.value1 = 0;
break; break;
case CC_SET: case CC_SET_ZN:
/* Insn sets the Z,N,V flags of CC to recog_operand[0].
C may or may not be set to 0 but that's ok
because alter_cond will change tests to use EQ/NE. */
CC_STATUS_INIT;
cc_status.value1 = recog_operand[0];
break;
case CC_SET_ZN_C0:
/* Insn sets the Z,N flags of CC to recog_operand[0]. /* Insn sets the Z,N flags of CC to recog_operand[0].
The V flag is unusable. The C flag may or may not be known but The V flag is unusable. The C flag may or may not be known but
that's ok because alter_cond will change tests to use EQ/NE. */ that's ok because alter_cond will change tests to use EQ/NE. */
...@@ -1614,6 +1606,15 @@ notice_update_cc (body, insn) ...@@ -1614,6 +1606,15 @@ notice_update_cc (body, insn)
cc_status.value1 = recog_operand[0]; cc_status.value1 = recog_operand[0];
break; break;
case CC_SET_ZNV:
/* Insn sets the Z,N,V flags of CC to recog_operand[0].
The C flag may or may not be known but that's ok because
alter_cond will change tests to use EQ/NE. */
CC_STATUS_INIT;
cc_status.flags |= CC_NO_CARRY;
cc_status.value1 = recog_operand[0];
break;
case CC_COMPARE: case CC_COMPARE:
/* The insn is a compare instruction. */ /* The insn is a compare instruction. */
CC_STATUS_INIT; CC_STATUS_INIT;
...@@ -1907,13 +1908,13 @@ static const struct shift_insn shift_one[2][3][3] = ...@@ -1907,13 +1908,13 @@ static const struct shift_insn shift_one[2][3][3] =
{ {
/* SHIFT_ASHIFT */ /* SHIFT_ASHIFT */
{ {
{ "shll\t%X0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shll\t%X0", CC_NO_CARRY },
{ "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
{ "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 } { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
}, },
/* SHIFT_LSHIFTRT */ /* SHIFT_LSHIFTRT */
{ {
{ "shlr\t%X0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shlr\t%X0", CC_NO_CARRY },
{ "shlr\t%t0\n\trotxr\t%s0", 0 }, { "shlr\t%t0\n\trotxr\t%s0", 0 },
{ "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 } { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
}, },
...@@ -1928,15 +1929,15 @@ static const struct shift_insn shift_one[2][3][3] = ...@@ -1928,15 +1929,15 @@ static const struct shift_insn shift_one[2][3][3] =
{ {
/* SHIFT_ASHIFT */ /* SHIFT_ASHIFT */
{ {
{ "shll.b\t%X0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shll.b\t%X0", CC_NO_CARRY },
{ "shll.w\t%T0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shll.w\t%T0", CC_NO_CARRY },
{ "shll.l\t%S0", CC_OVERFLOW_0 | CC_NO_CARRY } { "shll.l\t%S0", CC_NO_CARRY }
}, },
/* SHIFT_LSHIFTRT */ /* SHIFT_LSHIFTRT */
{ {
{ "shlr.b\t%X0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shlr.b\t%X0", CC_NO_CARRY },
{ "shlr.w\t%T0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shlr.w\t%T0", CC_NO_CARRY },
{ "shlr.l\t%S0", CC_OVERFLOW_0 | CC_NO_CARRY } { "shlr.l\t%S0", CC_NO_CARRY }
}, },
/* SHIFT_ASHIFTRT */ /* SHIFT_ASHIFTRT */
{ {
...@@ -1951,15 +1952,15 @@ static const struct shift_insn shift_two[3][3] = ...@@ -1951,15 +1952,15 @@ static const struct shift_insn shift_two[3][3] =
{ {
/* SHIFT_ASHIFT */ /* SHIFT_ASHIFT */
{ {
{ "shll.b\t#2,%X0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shll.b\t#2,%X0", CC_NO_CARRY },
{ "shll.w\t#2,%T0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shll.w\t#2,%T0", CC_NO_CARRY },
{ "shll.l\t#2,%S0", CC_OVERFLOW_0 | CC_NO_CARRY } { "shll.l\t#2,%S0", CC_NO_CARRY }
}, },
/* SHIFT_LSHIFTRT */ /* SHIFT_LSHIFTRT */
{ {
{ "shlr.b\t#2,%X0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shlr.b\t#2,%X0", CC_NO_CARRY },
{ "shlr.w\t#2,%T0", CC_OVERFLOW_0 | CC_NO_CARRY }, { "shlr.w\t#2,%T0", CC_NO_CARRY },
{ "shlr.l\t#2,%S0", CC_OVERFLOW_0 | CC_NO_CARRY } { "shlr.l\t#2,%S0", CC_NO_CARRY }
}, },
/* SHIFT_ASHIFTRT */ /* SHIFT_ASHIFTRT */
{ {
...@@ -2658,7 +2659,7 @@ emit_a_shift (insn, operands) ...@@ -2658,7 +2659,7 @@ emit_a_shift (insn, operands)
sprintf (insn_buf, "and #%d,%%X0", sprintf (insn_buf, "and #%d,%%X0",
mask, n); mask, n);
cc_status.value1 = operands[0]; cc_status.value1 = operands[0];
cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY; cc_status.flags |= CC_NO_CARRY;
break; break;
case HImode: case HImode:
sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0", sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0",
...@@ -2674,7 +2675,7 @@ emit_a_shift (insn, operands) ...@@ -2674,7 +2675,7 @@ emit_a_shift (insn, operands)
"bwl"[shift_mode], mask, "bwl"[shift_mode], mask,
mode == QImode ? 'X' : mode == HImode ? 'T' : 'S'); mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
cc_status.value1 = operands[0]; cc_status.value1 = operands[0];
cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY; cc_status.flags |= CC_NO_CARRY;
} }
output_asm_insn (insn_buf, operands); output_asm_insn (insn_buf, operands);
return ""; return "";
......
gcc/config/h8300/h8300.h
...@@ -999,8 +999,6 @@ h8300_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS) ...@@ -999,8 +999,6 @@ h8300_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN) #define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
/* The mov,and,or,xor insns always set V to 0. */
#define CC_OVERFLOW_0 0400
/* The add insns don't set overflow in a usable way. */ /* The add insns don't set overflow in a usable way. */
#define CC_OVERFLOW_UNUSABLE 01000 #define CC_OVERFLOW_UNUSABLE 01000
/* The mov,and,or,xor insns don't set carry. That's ok though as the /* The mov,and,or,xor insns don't set carry. That's ok though as the
...@@ -1009,7 +1007,6 @@ h8300_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS) ...@@ -1009,7 +1007,6 @@ h8300_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
CC_NO_OVERFLOW defined for this purpose. Rename it to something more CC_NO_OVERFLOW defined for this purpose. Rename it to something more
understandable. */ understandable. */
#define CC_NO_CARRY CC_NO_OVERFLOW #define CC_NO_CARRY CC_NO_OVERFLOW
/* ??? Use CC_Z_IN_NOT_C for bld insns? */
/* Control the assembler format that we output. */ /* Control the assembler format that we output. */
......
gcc/config/h8300/h8300.md
...@@ -86,13 +86,11 @@ ...@@ -86,13 +86,11 @@
;; none_0hit - insn does not affect cc but it does modify operand 0 ;; none_0hit - insn does not affect cc but it does modify operand 0
;; This attribute is used to keep track of when operand 0 changes. ;; This attribute is used to keep track of when operand 0 changes.
;; See the description of NOTICE_UPDATE_CC for more info. ;; See the description of NOTICE_UPDATE_CC for more info.
;; set - insn sets flags z,n,v. c are set to 0. ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
;; (c may not really be set to 0 but that's ok, we don't need it anyway). ;; set_zn - insn sets z,n to usable values; v,c are unknown.
;; set_zn_c0 - insn sets z,n to usable values. v is unknown. c may or may not
;; be known (if it isn't that's ok, we don't need it anyway).
;; compare - compare instruction ;; compare - compare instruction
;; clobber - value of cc is unknown ;; clobber - value of cc is unknown
(define_attr "cc" "none,none_0hit,set,set_zn_c0,compare,clobber" (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
(const_string "clobber")) (const_string "clobber"))
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
...@@ -113,7 +111,7 @@ ...@@ -113,7 +111,7 @@
return \"push.l %S1\"; return \"push.l %S1\";
}" }"
[(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))) [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,r,m") [(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,r,m")
...@@ -131,7 +129,7 @@ ...@@ -131,7 +129,7 @@
[(const_int 2) (const_int 2) (const_int 2) (const_int 2) [(const_int 2) (const_int 2) (const_int 2) (const_int 2)
(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))]) (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")]) (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_expand "movqi" (define_expand "movqi"
[(set (match_operand:QI 0 "general_operand_dst" "") [(set (match_operand:QI 0 "general_operand_dst" "")
...@@ -159,7 +157,7 @@ ...@@ -159,7 +157,7 @@
[(set_attr_alternative "length" [(set_attr_alternative "length"
[(const_int 2) (const_int 2) (const_int 2) [(const_int 2) (const_int 2) (const_int 2)
(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))]) (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0")]) (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
;; movhi ;; movhi
...@@ -177,7 +175,7 @@ ...@@ -177,7 +175,7 @@
return \"push.l %S1\"; return \"push.l %S1\";
}" }"
[(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))) [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m") [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
...@@ -195,7 +193,7 @@ ...@@ -195,7 +193,7 @@
[(const_int 2) (const_int 2) (const_int 2) (const_int 4) [(const_int 2) (const_int 2) (const_int 2) (const_int 4)
(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))]) (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")]) (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_expand "movhi" (define_expand "movhi"
[(set (match_operand:HI 0 "general_operand_dst" "") [(set (match_operand:HI 0 "general_operand_dst" "")
...@@ -223,7 +221,7 @@ ...@@ -223,7 +221,7 @@
[(set_attr_alternative "length" [(set_attr_alternative "length"
[(const_int 2) (const_int 2) (const_int 4) [(const_int 2) (const_int 2) (const_int 4)
(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))]) (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0")]) (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
;; movsi ;; movsi
...@@ -440,7 +438,7 @@ ...@@ -440,7 +438,7 @@
return \"mov.l %S1,%S0\"; return \"mov.l %S1,%S0\";
}" }"
[(set_attr "length" "2,2,10,10,4,4,2,6,4") [(set_attr "length" "2,2,10,10,4,4,2,6,4")
(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,none_0hit,none_0hit,set_zn_c0")]) (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
(define_insn "movsf_h8300h" (define_insn "movsf_h8300h"
[(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r") [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
...@@ -456,7 +454,7 @@ ...@@ -456,7 +454,7 @@
mov.l %S1,%S0 mov.l %S1,%S0
mov.l %S1,%S0" mov.l %S1,%S0"
[(set_attr "length" "2,2,10,10,4,4") [(set_attr "length" "2,2,10,10,4,4")
(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")]) (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
;; TEST INSTRUCTIONS ;; TEST INSTRUCTIONS
...@@ -469,7 +467,7 @@ ...@@ -469,7 +467,7 @@
"" ""
"btst %Z1,%R0" "btst %Z1,%R0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_insn "" (define_insn ""
[(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU") [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
...@@ -478,7 +476,7 @@ ...@@ -478,7 +476,7 @@
"" ""
"btst %Z1,%Y0" "btst %Z1,%Y0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_insn "" (define_insn ""
[(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU") [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
...@@ -487,7 +485,7 @@ ...@@ -487,7 +485,7 @@
"" ""
"btst %Z1,%Y0" "btst %Z1,%Y0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_insn "" (define_insn ""
[(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r") [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
...@@ -496,7 +494,7 @@ ...@@ -496,7 +494,7 @@
"" ""
"btst %Z1,%R0" "btst %Z1,%R0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_insn "" (define_insn ""
[(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r") [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
...@@ -505,7 +503,7 @@ ...@@ -505,7 +503,7 @@
"" ""
"btst %Z1,%Y0" "btst %Z1,%Y0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_insn "" (define_insn ""
[(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r") [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
...@@ -514,28 +512,28 @@ ...@@ -514,28 +512,28 @@
"" ""
"btst %Z1,%Y0" "btst %Z1,%Y0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_insn "tstqi" (define_insn "tstqi"
[(set (cc0) (match_operand:QI 0 "register_operand" "r"))] [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
"" ""
"mov.b %X0,%X0" "mov.b %X0,%X0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_insn "tsthi" (define_insn "tsthi"
[(set (cc0) (match_operand:HI 0 "register_operand" "r"))] [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
"" ""
"mov.w %T0,%T0" "mov.w %T0,%T0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_insn "tstsi" (define_insn "tstsi"
[(set (cc0) (match_operand:SI 0 "register_operand" "r"))] [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
"TARGET_H8300H || TARGET_H8300S" "TARGET_H8300H || TARGET_H8300S"
"mov.l %S0,%S0" "mov.l %S0,%S0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_insn "cmpqi" (define_insn "cmpqi"
[(set (cc0) [(set (cc0)
...@@ -597,7 +595,7 @@ ...@@ -597,7 +595,7 @@
"" ""
"add.b %X2,%X0" "add.b %X2,%X0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set")]) (set_attr "cc" "set_zn")])
(define_expand "addhi3" (define_expand "addhi3"
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
...@@ -631,7 +629,7 @@ ...@@ -631,7 +629,7 @@
add.w %T2,%T0 add.w %T2,%T0
mov.w %T1,%T0\;add.w %T2,%T0" mov.w %T1,%T0\;add.w %T2,%T0"
[(set_attr "length" "4,2,6") [(set_attr "length" "4,2,6")
(set_attr "cc" "clobber,set,set")]) (set_attr "cc" "clobber,set_zn,set_zn")])
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r,r") [(set (match_operand:HI 0 "register_operand" "=r,r")
...@@ -642,7 +640,7 @@ ...@@ -642,7 +640,7 @@
add.w %T2,%T0 add.w %T2,%T0
add.w %T2,%T0" add.w %T2,%T0"
[(set_attr "length" "4,2") [(set_attr "length" "4,2")
(set_attr "cc" "set,set")]) (set_attr "cc" "set_zn,set_zn")])
(define_expand "addsi3" (define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -687,7 +685,7 @@ ...@@ -687,7 +685,7 @@
add.l %S2,%S0 add.l %S2,%S0
add.l %S2,%S0" add.l %S2,%S0"
[(set_attr "length" "6,2") [(set_attr "length" "6,2")
(set_attr "cc" "set,set")]) (set_attr "cc" "set_zn,set_zn")])
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
;; SUBTRACT INSTRUCTIONS ;; SUBTRACT INSTRUCTIONS
...@@ -702,7 +700,7 @@ ...@@ -702,7 +700,7 @@
sub.b %X2,%X0 sub.b %X2,%X0
add.b %G2,%X0" add.b %G2,%X0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set")]) (set_attr "cc" "set_zn")])
(define_expand "subhi3" (define_expand "subhi3"
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
...@@ -740,7 +738,7 @@ ...@@ -740,7 +738,7 @@
sub.w %T2,%T0 sub.w %T2,%T0
add.b %E2,%s0\;addx %F2,%t0" add.b %E2,%s0\;addx %F2,%t0"
[(set_attr "length" "2,4") [(set_attr "length" "2,4")
(set_attr "cc" "set,clobber")]) (set_attr "cc" "set_zn,clobber")])
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r,&r") [(set (match_operand:HI 0 "register_operand" "=r,&r")
...@@ -751,7 +749,7 @@ ...@@ -751,7 +749,7 @@
sub.w %T2,%T0 sub.w %T2,%T0
sub.w %T2,%T0" sub.w %T2,%T0"
[(set_attr "length" "2,4") [(set_attr "length" "2,4")
(set_attr "cc" "set,set")]) (set_attr "cc" "set_zn,set_zn")])
(define_expand "subsi3" (define_expand "subsi3"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -798,7 +796,7 @@ ...@@ -798,7 +796,7 @@
sub.l %S2,%S0 sub.l %S2,%S0
sub.l %S2,%S0" sub.l %S2,%S0"
[(set_attr "length" "2,6") [(set_attr "length" "2,6")
(set_attr "cc" "set,set")]) (set_attr "cc" "set_zn,set_zn")])
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
;; MULTIPLY INSTRUCTIONS ;; MULTIPLY INSTRUCTIONS
...@@ -813,7 +811,7 @@ ...@@ -813,7 +811,7 @@
"TARGET_H8300H || TARGET_H8300S" "TARGET_H8300H || TARGET_H8300S"
"mulxs.b %X2,%T0" "mulxs.b %X2,%T0"
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_insn "mulhisi3" (define_insn "mulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -822,7 +820,7 @@ ...@@ -822,7 +820,7 @@
"TARGET_H8300H || TARGET_H8300S" "TARGET_H8300H || TARGET_H8300S"
"mulxs.w %T2,%S0" "mulxs.w %T2,%S0"
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_insn "umulqihi3" (define_insn "umulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r") [(set (match_operand:HI 0 "register_operand" "=r")
...@@ -985,7 +983,7 @@ ...@@ -985,7 +983,7 @@
and %X2,%X0 and %X2,%X0
bclr %W2,%R0" bclr %W2,%R0"
[(set_attr "length" "2,4") [(set_attr "length" "2,4")
(set_attr "cc" "set_zn_c0,none_0hit")]) (set_attr "cc" "set_znv,none_0hit")])
(define_expand "andqi3" (define_expand "andqi3"
[(set (match_operand:QI 0 "bit_operand" "") [(set (match_operand:QI 0 "bit_operand" "")
...@@ -1089,7 +1087,7 @@ ...@@ -1089,7 +1087,7 @@
or %X2,%X0 or %X2,%X0
bset %V2,%R0" bset %V2,%R0"
[(set_attr "length" "2,4") [(set_attr "length" "2,4")
(set_attr "cc" "set_zn_c0,none_0hit")]) (set_attr "cc" "set_znv,none_0hit")])
(define_expand "iorqi3" (define_expand "iorqi3"
[(set (match_operand:QI 0 "bit_operand" "=r,U") [(set (match_operand:QI 0 "bit_operand" "=r,U")
...@@ -1175,7 +1173,7 @@ ...@@ -1175,7 +1173,7 @@
xor %X2,%X0 xor %X2,%X0
bnot %V2,%R0" bnot %V2,%R0"
[(set_attr "length" "2,4") [(set_attr "length" "2,4")
(set_attr "cc" "set_zn_c0,none_0hit")]) (set_attr "cc" "set_znv,none_0hit")])
(define_expand "xorqi3" (define_expand "xorqi3"
[(set (match_operand:QI 0 "bit_operand" "=r,U") [(set (match_operand:QI 0 "bit_operand" "=r,U")
...@@ -1258,7 +1256,7 @@ ...@@ -1258,7 +1256,7 @@
"" ""
"neg %X0" "neg %X0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_expand "neghi2" (define_expand "neghi2"
[(set (match_operand:HI 0 "register_operand" "=r") [(set (match_operand:HI 0 "register_operand" "=r")
...@@ -1288,7 +1286,7 @@ ...@@ -1288,7 +1286,7 @@
"TARGET_H8300H || TARGET_H8300S" "TARGET_H8300H || TARGET_H8300S"
"neg %T0" "neg %T0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
(define_expand "negsi2" (define_expand "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -1318,7 +1316,7 @@ ...@@ -1318,7 +1316,7 @@
"TARGET_H8300H || TARGET_H8300S" "TARGET_H8300H || TARGET_H8300S"
"neg %S0" "neg %S0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_zn")])
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
;; NOT INSTRUCTIONS ;; NOT INSTRUCTIONS
...@@ -1330,7 +1328,7 @@ ...@@ -1330,7 +1328,7 @@
"" ""
"not %X0" "not %X0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_insn "one_cmplhi2" (define_insn "one_cmplhi2"
[(set (match_operand:HI 0 "register_operand" "=r") [(set (match_operand:HI 0 "register_operand" "=r")
...@@ -1474,6 +1472,16 @@ ...@@ -1474,6 +1472,16 @@
"" ""
"* "*
{ {
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
&& (GET_CODE (operands[1]) == GT
|| GET_CODE (operands[1]) == GE
|| GET_CODE (operands[1]) == LE
|| GET_CODE (operands[1]) == LT))
{
cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
return 0;
}
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"b%j1 %l0\"; return \"b%j1 %l0\";
else if (get_attr_length (insn) == 4) else if (get_attr_length (insn) == 4)
...@@ -1493,6 +1501,16 @@ ...@@ -1493,6 +1501,16 @@
"" ""
"* "*
{ {
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
&& (GET_CODE (operands[1]) == GT
|| GET_CODE (operands[1]) == GE
|| GET_CODE (operands[1]) == LE
|| GET_CODE (operands[1]) == LT))
{
cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
return 0;
}
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"b%k1 %l0\"; return \"b%k1 %l0\";
else if (get_attr_length (insn) == 4) else if (get_attr_length (insn) == 4)
...@@ -1689,7 +1707,7 @@ ...@@ -1689,7 +1707,7 @@
extu.l %S0 extu.l %S0
mov.w %T1,%T0\;extu.l %S0" mov.w %T1,%T0\;extu.l %S0"
[(set_attr "length" "2,4") [(set_attr "length" "2,4")
(set_attr "cc" "set_zn_c0,set_zn_c0")]) (set_attr "cc" "set_znv,set_znv")])
(define_expand "extendqihi2" (define_expand "extendqihi2"
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
...@@ -1715,7 +1733,7 @@ ...@@ -1715,7 +1733,7 @@
exts.w %T0 exts.w %T0
mov.b %R1,%s0\;exts.w %T0" mov.b %R1,%s0\;exts.w %T0"
[(set_attr "length" "2,4") [(set_attr "length" "2,4")
(set_attr "cc" "set_zn_c0,set_zn_c0")]) (set_attr "cc" "set_znv,set_znv")])
;; The compiler can synthesize a 300H variant of this which is ;; The compiler can synthesize a 300H variant of this which is
;; just as efficient as one that we'd create ;; just as efficient as one that we'd create
...@@ -1772,7 +1790,7 @@ ...@@ -1772,7 +1790,7 @@
exts.l %S0 exts.l %S0
mov.w %T1,%T0\;exts.l %S0" mov.w %T1,%T0\;exts.l %S0"
[(set_attr "length" "2,4") [(set_attr "length" "2,4")
(set_attr "cc" "set_zn_c0,set_zn_c0")]) (set_attr "cc" "set_znv,set_znv")])
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
;; SHIFTS ;; SHIFTS
...@@ -2242,7 +2260,7 @@ ...@@ -2242,7 +2260,7 @@
"(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])" "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
"mov.w @(%u4,%T1),%T0" "mov.w @(%u4,%T1),%T0"
[(set_attr "length" "6") [(set_attr "length" "6")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_peephole (define_peephole
[(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r") [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r")
...@@ -2254,7 +2272,7 @@ ...@@ -2254,7 +2272,7 @@
"(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])" "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
"mov.w %T0,@(%u4,%T1)" "mov.w %T0,@(%u4,%T1)"
[(set_attr "length" "6") [(set_attr "length" "6")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
;; Notice a move which could be post incremented. ;; Notice a move which could be post incremented.
...@@ -2265,7 +2283,7 @@ ...@@ -2265,7 +2283,7 @@
"REGNO(operands[1]) != REGNO(operands[0])" "REGNO(operands[1]) != REGNO(operands[0])"
"mov.b @%T1+,%X0" "mov.b @%T1+,%X0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_peephole (define_peephole
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
...@@ -2274,7 +2292,7 @@ ...@@ -2274,7 +2292,7 @@
"REGNO(operands[1]) != REGNO(operands[0])" "REGNO(operands[1]) != REGNO(operands[0])"
"mov.w @%T1+,%T0" "mov.w @%T1+,%T0"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
;; Notice a move which could be predecremented. ;; Notice a move which could be predecremented.
...@@ -2286,7 +2304,7 @@ ...@@ -2286,7 +2304,7 @@
"REGNO(operands[1]) != REGNO(operands[0])" "REGNO(operands[1]) != REGNO(operands[0])"
"mov.b %X0,@-%T1" "mov.b %X0,@-%T1"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
(define_peephole (define_peephole
[(set (match_operand:HI 1 "register_operand" "") [(set (match_operand:HI 1 "register_operand" "")
...@@ -2296,5 +2314,5 @@ ...@@ -2296,5 +2314,5 @@
"REGNO(operands[1]) != REGNO(operands[0])" "REGNO(operands[1]) != REGNO(operands[0])"
"mov.w %T0,@-%T1" "mov.w %T0,@-%T1"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "cc" "set_zn_c0")]) (set_attr "cc" "set_znv")])
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