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Commit 0609abda by Trevor Saunders Committed by Trevor Saunders
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remove mep-* support 

libgcc/ChangeLog:

2016-06-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* config.host: Remove support for mep-*.
	* config/mep/lib1funcs.S: Remove.
	* config/mep/lib2funcs.c: Remove.
	* config/mep/t-mep: Remove.
	* config/mep/tramp.c: Remove.

gcc/ChangeLog:

2016-06-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* common/config/mep/mep-common.c: Remove.
	* config.gcc: Remove mep-* support.
	* config/mep/constraints.md: Remove.
	* config/mep/default.h: Remove.
	* config/mep/intrinsics.h: Remove.
	* config/mep/intrinsics.md: Remove.
	* config/mep/ivc2-template.h: Remove.
	* config/mep/mep-c5.cpu: Remove.
	* config/mep/mep-core.cpu: Remove.
	* config/mep/mep-default.cpu: Remove.
	* config/mep/mep-ext-cop.cpu: Remove.
	* config/mep/mep-intrin.h: Remove.
	* config/mep/mep-ivc2.cpu: Remove.
	* config/mep/mep-pragma.c: Remove.
	* config/mep/mep-protos.h: Remove.
	* config/mep/mep.c: Remove.
	* config/mep/mep.cpu: Remove.
	* config/mep/mep.h: Remove.
	* config/mep/mep.md: Remove.
	* config/mep/mep.opt: Remove.
	* config/mep/predicates.md: Remove.
	* config/mep/t-mep: Remove.
	* doc/install.texi: Remove mep-* documentation.
	* doc/md.texi: Likewise.

gcc/testsuite/ChangeLog:

2016-06-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* gcc.dg/tree-ssa/forwprop-28.c: Remove mep-* support.
	* gcc.dg/tree-ssa/reassoc-32.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-33.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-34.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-35.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-36.c: Likewise.
	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c: Likewise.
	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-2.c: Likewise.
	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-3.c: Likewise.
	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c: Likewise.
	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c: Likewise.
	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c: Likewise.
	* gcc.dg/tree-ssa/ssa-thread-11.c: Likewise.
	* gcc.dg/tree-ssa/vrp87.c: Likewise.
	* lib/target-supports.exp: Likewise.

contrib/ChangeLog:

2016-06-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* config-list.mk: Stop testing mep-elf.

libstdc++-v3/ChangeLog:

2016-06-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* configure.host: Remove mep-* support.

From-SVN: r237666
parent 3e326935
Showing with 77 additions and 8834 deletions
contrib/ChangeLog
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* config-list.mk: Stop testing mep-elf.
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* config-list.mk: Stop testing avr-rtems.
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
......
contrib/config-list.mk
......@@ -57,7 +57,7 @@ LIST = aarch64-elf aarch64-linux-gnu aarch64-rtems \
lm32-rtems lm32-uclinux m32c-rtems m32c-elf m32r-elf m32rle-elf \
m32r-linux m32rle-linux m68k-elf m68k-netbsdelf \
m68k-openbsd m68k-uclinux m68k-linux m68k-rtems \
mcore-elf mep-elfOPT-enable-obsolete microblaze-linux microblaze-elf \
mcore-elf microblaze-linux microblaze-elf \
mips-netbsd \
mips64el-st-linux-gnu mips64octeon-linux mipsisa64r2-linux \
mipsisa32r2-linux-gnu mipsisa64r2-sde-elf mipsisa32-elfoabi \
......
gcc/ChangeLog
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* common/config/mep/mep-common.c: Remove.
* config.gcc: Remove mep-* support.
* config/mep/constraints.md: Remove.
* config/mep/default.h: Remove.
* config/mep/intrinsics.h: Remove.
* config/mep/intrinsics.md: Remove.
* config/mep/ivc2-template.h: Remove.
* config/mep/mep-c5.cpu: Remove.
* config/mep/mep-core.cpu: Remove.
* config/mep/mep-default.cpu: Remove.
* config/mep/mep-ext-cop.cpu: Remove.
* config/mep/mep-intrin.h: Remove.
* config/mep/mep-ivc2.cpu: Remove.
* config/mep/mep-pragma.c: Remove.
* config/mep/mep-protos.h: Remove.
* config/mep/mep.c: Remove.
* config/mep/mep.cpu: Remove.
* config/mep/mep.h: Remove.
* config/mep/mep.md: Remove.
* config/mep/mep.opt: Remove.
* config/mep/predicates.md: Remove.
* config/mep/t-mep: Remove.
* doc/install.texi: Remove mep-* documentation.
* doc/md.texi: Likewise.
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* config.gcc: Remove support for avr-rtems.
* config/avr/gen-avr-mmcu-specs.c: Likewise.
* config/avr/rtems.h: Remove.
......
gcc/common/config/mep/mep-common.c deleted 100644 → 0
/* Common hooks for Toshiba Media Processor.
Copyright (C) 2001-2016 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
static const struct default_options mep_option_optimization_table[] =
{
/* The first scheduling pass often increases register pressure and
tends to result in more spill code. Only run it when
specifically asked. */
{ OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
/* Using $fp doesn't gain us much, even when debugging is
important. */
{ OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
static bool
mep_handle_option (struct gcc_options *opts,
struct gcc_options *opts_set ATTRIBUTE_UNUSED,
const struct cl_decoded_option *decoded,
location_t loc ATTRIBUTE_UNUSED)
{
size_t code = decoded->opt_index;
switch (code)
{
case OPT_mall_opts:
opts->x_target_flags |= MEP_ALL_OPTS;
break;
case OPT_mno_opts:
opts->x_target_flags &= ~ MEP_ALL_OPTS;
break;
case OPT_mcop64:
opts->x_target_flags |= MASK_COP;
opts->x_target_flags |= MASK_64BIT_CR_REGS;
break;
case OPT_mivc2:
opts->x_target_flags |= MASK_COP;
opts->x_target_flags |= MASK_64BIT_CR_REGS;
opts->x_target_flags |= MASK_VLIW;
opts->x_target_flags |= MASK_OPT_VL64;
opts->x_target_flags |= MASK_IVC2;
/* Remaining handling of this option deferred. */
break;
default:
break;
}
return TRUE;
}
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION mep_handle_option
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE mep_option_optimization_table
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
gcc/config.gcc
......@@ -236,7 +236,7 @@ md_file=
# Obsolete configurations.
case ${target} in
mep-* \
nothing \
)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration ${target} is obsolete." >&2
......@@ -1918,17 +1918,6 @@ mcore-*-elf)
tmake_file=mcore/t-mcore
inhibit_libc=true
;;
mep-*-*)
tm_file="dbxelf.h elfos.h ${tm_file} newlib-stdint.h"
tmake_file=mep/t-mep
c_target_objs="mep-pragma.o"
cxx_target_objs="mep-pragma.o"
if test -d "${srcdir}/../newlib/libc/include" &&
test "x$with_headers" = x; then
with_headers=yes
fi
use_gcc_stdint=wrap
;;
microblaze*-linux*)
case $target in
microblazeel-*)
......
gcc/config/mep/constraints.md deleted 100644 → 0
;; Toshiba Media Processor Machine constraints
;; Copyright (C) 2009-2016 Free Software Foundation, Inc.
;; Contributed by Red Hat Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
(define_register_constraint "a" "SP_REGS"
"The $sp register.")
(define_register_constraint "b" "TP_REGS"
"The $tp register.")
(define_register_constraint "c" "CONTROL_REGS"
"Any control register.")
(define_register_constraint "d" "HILO_REGS"
"Either the $hi or the $lo register.")
(define_register_constraint "em" "LOADABLE_CR_REGS"
"Coprocessor registers that can be directly loaded ($c0-$c15).")
(define_register_constraint "ex" "mep_have_copro_copro_moves_p ? CR_REGS : NO_REGS"
"Coprocessor registers that can be moved to each other.")
(define_register_constraint "er" "mep_have_core_copro_moves_p ? CR_REGS : NO_REGS"
"Coprocessor registers that can be moved to core registers.")
(define_register_constraint "h" "HI_REGS"
"The $hi register.")
(define_register_constraint "j" "RPC_REGS"
"The $rpc register.")
(define_register_constraint "l" "LO_REGS"
"The $lo register.")
(define_register_constraint "t" "TPREL_REGS"
"Registers which can be used in $tp-relative addressing.")
(define_register_constraint "v" "GP_REGS"
"The $gp register.")
(define_register_constraint "x" "CR_REGS"
"The coprocessor registers.")
(define_register_constraint "y" "CCR_REGS"
"The coprocessor control registers.")
(define_register_constraint "z" "R0_REGS"
"The $0 register.")
(define_register_constraint "A" "USER0_REGS"
"User-defined register set A.")
(define_register_constraint "B" "USER1_REGS"
"User-defined register set B.")
(define_register_constraint "C" "USER2_REGS"
"User-defined register set C.")
(define_register_constraint "D" "USER3_REGS"
"User-defined register set D.")
(define_constraint "I"
"Offsets for $gp-rel addressing."
(and (match_code "const_int")
(match_test "ival >= -32768 && ival < 32768")))
(define_constraint "J"
"Constants that can be used directly with boolean insns."
(and (match_code "const_int")
(match_test "ival >= 0 && ival < 65536")))
(define_constraint "K"
"Constants that can be moved directly to registers."
(and (match_code "const_int")
(match_test "ival >= 0 && ival < 0x01000000")))
(define_constraint "L"
"Small constants that can be added to registers."
(and (match_code "const_int")
(match_test "ival >= -32 && ival < 32")))
(define_constraint "M"
"Long shift counts."
(and (match_code "const_int")
(match_test "ival >= 0 && ival < 32")))
(define_constraint "N"
"Small constants that can be compared to registers."
(and (match_code "const_int")
(match_test "ival >= 0 && ival < 16")))
(define_constraint "O"
"Constants that can be loaded into the top half of registers."
(and (match_code "const_int")
(match_test "!(ival & 0xffff) && ival >= -2147483647-1 && ival <= 2147483647")))
(define_constraint "S"
"Signed 8-bit immediates."
(and (match_code "const_int")
(match_test "ival >= -128 && ival < 127")))
;; This must only be used with mep_call_address_operand() as the predicate.
(define_constraint "R"
"@internal
Near symbols that can be used as addresses for CALL."
(not (match_code "reg")))
(define_constraint "T"
"Symbols encoded for $tp-rel or $gp-rel addressing."
(ior (ior
(and (match_code "unspec")
(match_code "symbol_ref" "a"))
(and (match_code "const")
(and (match_code "unspec" "0")
(match_code "symbol_ref" "0a"))))
(and (match_code "const")
(and (match_code "plus" "0")
(and (match_code "unspec" "00")
(match_code "symbol_ref" "00a"))))))
(define_constraint "U"
"Non-constant addresses for loading/saving coprocessor registers."
(and (match_code "mem")
(match_test "! CONSTANT_P (XEXP (op, 0))")))
(define_constraint "W"
"The top half of a symbol's value."
(and (match_code "high")
(match_code "symbol_ref" "0")))
(define_constraint "Y"
"A register indirect address without offset."
(and (match_code "mem")
(match_code "reg" "0")))
(define_constraint "Z"
"Symbolic references to the control bus."
(and (and (match_code "mem")
(match_code "symbol_ref" "0"))
(match_test "mep_section_tag (op) == 'c'")))
gcc/config/mep/default.h deleted 100644 → 0
/* Header created by MeP-Integrator */
#undef __section
#define __section(_secname) __attribute__((section(#_secname)))
#undef mep_nop
#define mep_nop() __asm__ volatile ("nop")
#pragma GCC coprocessor available $c0...$c31
#pragma GCC coprocessor call_saved $c6...$c7
#include <intrinsics.h>
gcc/config/mep/intrinsics.h deleted 100644 → 0
/* DO NOT EDIT: This file is automatically generated by CGEN.
Any changes you make will be discarded when it is next regenerated.
*/
/* GCC defines these internally, as follows...
#if __MEP_CONFIG_CP_DATA_BUS_WIDTH == 64
typedef long long cp_data_bus_int;
#else
typedef long cp_data_bus_int;
#endif
typedef char cp_v8qi __attribute__((vector_size(8)));
typedef unsigned char cp_v8uqi __attribute__((vector_size(8)));
typedef short cp_v4hi __attribute__((vector_size(8)));
typedef unsigned short cp_v4uhi __attribute__((vector_size(8)));
typedef int cp_v2si __attribute__((vector_size(8)));
typedef unsigned int cp_v2usi __attribute__((vector_size(8)));
*/
// default
void mep_cpfmadila1_h (cp_v4hi, cp_v4hi, long, long); // volatile
void mep_cpfmadiua1_h (cp_v4hi, cp_v4hi, long, long); // volatile
void mep_cpfmadia1_b (cp_v8qi, cp_v8qi, long, long); // volatile
void mep_cpfmadia1u_b (cp_v8uqi, cp_v8uqi, long, long); // volatile
void mep_cpfmulila1_h (cp_v4hi, cp_v4hi, long, long); // volatile
void mep_cpfmuliua1_h (cp_v4hi, cp_v4hi, long, long); // volatile
void mep_cpfmulia1_b (cp_v8qi, cp_v8qi, long, long); // volatile
void mep_cpfmulia1u_b (cp_v8uqi, cp_v8uqi, long, long); // volatile
void mep_cpamadila1_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpamadiua1_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpamadia1_b (cp_v8qi, cp_v8qi, long); // volatile
void mep_cpamadia1u_b (cp_v8uqi, cp_v8uqi, long); // volatile
void mep_cpamulila1_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpamuliua1_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpamulia1_b (cp_v8qi, cp_v8qi, long); // volatile
void mep_cpamulia1u_b (cp_v8uqi, cp_v8uqi, long); // volatile
void mep_cpfmadila1s1_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpfmadiua1s1_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpfmadia1s1_b (cp_v8qi, cp_v8qi, long); // volatile
void mep_cpfmadia1s1u_b (cp_v8uqi, cp_v8uqi, long); // volatile
void mep_cpfmulila1s1_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpfmuliua1s1_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpfmulia1s1_b (cp_v8qi, cp_v8qi, long); // volatile
void mep_cpfmulia1s1u_b (cp_v8uqi, cp_v8uqi, long); // volatile
void mep_cpfmadila1s0_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpfmadiua1s0_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpfmadia1s0_b (cp_v8qi, cp_v8qi, long); // volatile
void mep_cpfmadia1s0u_b (cp_v8uqi, cp_v8uqi, long); // volatile
void mep_cpfmulila1s0_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpfmuliua1s0_h (cp_v4hi, cp_v4hi, long); // volatile
void mep_cpfmulia1s0_b (cp_v8qi, cp_v8qi, long); // volatile
void mep_cpfmulia1s0u_b (cp_v8uqi, cp_v8uqi, long); // volatile
void mep_cpacswp (); // volatile
void mep_cpaccpa1 (); // volatile
void mep_cpacsuma1 (); // volatile
void mep_c1nop (); // volatile
void mep_cpfacla0s1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpfacua0s1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpfaca0s1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpfaca0s1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpfsftbla0s1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpfsftbua0s1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpfsftba0s1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpfsftba0s1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpfacla0s0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpfacua0s0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpfaca0s0_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpfaca0s0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpfsftbla0s0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpfsftbua0s0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpfsftba0s0_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpfsftba0s0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpsllia0 (long); // volatile
void mep_cpsraia0 (long); // volatile
void mep_cpsrlia0 (long); // volatile
void mep_cpslla0 (cp_data_bus_int); // volatile
void mep_cpsraa0 (cp_data_bus_int); // volatile
void mep_cpsrla0 (cp_data_bus_int); // volatile
void mep_cpaccpa0 (); // volatile
void mep_cpacsuma0 (); // volatile
cp_v2si mep_cpmovhla0_w (); // volatile
cp_v2si mep_cpmovhua0_w (); // volatile
cp_v2si mep_cppackla0_w (); // volatile
cp_v2si mep_cppackua0_w (); // volatile
cp_v4hi mep_cppackla0_h (); // volatile
cp_v4hi mep_cppackua0_h (); // volatile
cp_v8qi mep_cppacka0_b (); // volatile
cp_v8uqi mep_cppacka0u_b (); // volatile
cp_v2si mep_cpmovlla0_w (); // volatile
cp_v2si mep_cpmovlua0_w (); // volatile
cp_v2si mep_cpmovula0_w (); // volatile
cp_v2si mep_cpmovuua0_w (); // volatile
cp_v4hi mep_cpmovla0_h (); // volatile
cp_v4hi mep_cpmovua0_h (); // volatile
cp_v8qi mep_cpmova0_b (); // volatile
void mep_cpsetla0_w (cp_v2si, cp_v2si); // volatile
void mep_cpsetua0_w (cp_v2si, cp_v2si); // volatile
void mep_cpseta0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsadla0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsadua0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsada0_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpsada0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpabsla0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpabsua0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpabsa0_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpabsa0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpsubacla0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsubacua0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsubaca0_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpsubaca0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpsubla0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsubua0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsuba0_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpsuba0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpaddacla0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpaddacua0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpaddaca0_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpaddaca0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpaddla0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpaddua0_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpadda0_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpadda0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_c0nop (); // volatile
void mep_cpsmsbslla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsmsbslua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsmsbslla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsmsbslua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsmadslla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsmadslua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsmadslla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsmadslua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmulslla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpmulslua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpmulslla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmulslua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsmsbla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsmsbua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsmsbla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsmsbua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsmadla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsmadua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsmadla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsmadua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmsbla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpmsbua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpmsbla1u_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpmsbua1u_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpmsbla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmsbua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmadla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpmadua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpmadla1u_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpmadua1u_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpmadla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmadua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmada1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpmada1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpmulla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpmulua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpmulla1u_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpmulua1u_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpmulla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmulua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpmula1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpmula1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpssda1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpssda1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpssqa1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpssqa1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpsllia1 (long); // volatile
void mep_cpsraia1 (long); // volatile
void mep_cpsrlia1 (long); // volatile
void mep_cpslla1 (cp_data_bus_int); // volatile
void mep_cpsraa1 (cp_data_bus_int); // volatile
void mep_cpsrla1 (cp_data_bus_int); // volatile
cp_v2si mep_cpmovhla1_w (); // volatile
cp_v2si mep_cpmovhua1_w (); // volatile
cp_v2si mep_cppackla1_w (); // volatile
cp_v2si mep_cppackua1_w (); // volatile
cp_v4hi mep_cppackla1_h (); // volatile
cp_v4hi mep_cppackua1_h (); // volatile
cp_v8qi mep_cppacka1_b (); // volatile
cp_v8uqi mep_cppacka1u_b (); // volatile
cp_v2si mep_cpmovlla1_w (); // volatile
cp_v2si mep_cpmovlua1_w (); // volatile
cp_v2si mep_cpmovula1_w (); // volatile
cp_v2si mep_cpmovuua1_w (); // volatile
cp_v4hi mep_cpmovla1_h (); // volatile
cp_v4hi mep_cpmovua1_h (); // volatile
cp_v8qi mep_cpmova1_b (); // volatile
void mep_cpsetla1_w (cp_v2si, cp_v2si); // volatile
void mep_cpsetua1_w (cp_v2si, cp_v2si); // volatile
void mep_cpseta1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsadla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsadua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsada1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpsada1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpabsla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpabsua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpabsa1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpabsa1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpsubacla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsubacua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsubaca1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpsubaca1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpsubla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsubua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpsuba1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpsuba1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpaddacla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpaddacua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpaddaca1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpaddaca1u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpaddla1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpaddua1_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpadda1_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpadda1u_b (cp_v8uqi, cp_v8uqi); // volatile
cp_data_bus_int mep_cdmovi (long);
cp_data_bus_int mep_cdmoviu (long);
cp_v2si mep_cpmovi_w (long);
cp_v2usi mep_cpmoviu_w (long);
cp_v4hi mep_cpmovi_h (long);
cp_v4uhi mep_cpmoviu_h (long);
cp_v8qi mep_cpmovi_b (long);
cp_data_bus_int mep_cdclipi3 (cp_data_bus_int, long);
cp_data_bus_int mep_cdclipiu3 (cp_data_bus_int, long);
cp_v2si mep_cpclipi3_w (cp_v2si, long);
cp_v2si mep_cpclipiu3_w (cp_v2si, long);
cp_v2si mep_cpslai3_w (cp_v2si, long); // volatile
cp_v4hi mep_cpslai3_h (cp_v4hi, long); // volatile
cp_data_bus_int mep_cdslli3 (cp_data_bus_int, long);
cp_v2si mep_cpslli3_w (cp_v2si, long);
cp_v4hi mep_cpslli3_h (cp_v4hi, long);
cp_v8qi mep_cpslli3_b (cp_v8qi, long);
cp_data_bus_int mep_cdsrai3 (cp_data_bus_int, long);
cp_v2si mep_cpsrai3_w (cp_v2si, long);
cp_v4hi mep_cpsrai3_h (cp_v4hi, long);
cp_v8qi mep_cpsrai3_b (cp_v8qi, long);
cp_data_bus_int mep_cdsrli3 (cp_data_bus_int, long);
cp_v2si mep_cpsrli3_w (cp_v2si, long);
cp_v4hi mep_cpsrli3_h (cp_v4hi, long);
cp_v8qi mep_cpsrli3_b (cp_v8qi, long);
void mep_cpocmpge_w (cp_v2si, cp_v2si); // volatile
void mep_cpocmpgeu_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpocmpge_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpocmpge_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpocmpgeu_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpocmpgt_w (cp_v2si, cp_v2si); // volatile
void mep_cpocmpgtu_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpocmpgt_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpocmpgt_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpocmpgtu_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpocmpne_w (cp_v2si, cp_v2si); // volatile
void mep_cpocmpne_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpocmpne_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpocmpeq_w (cp_v2si, cp_v2si); // volatile
void mep_cpocmpeq_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpocmpeq_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpacmpge_w (cp_v2si, cp_v2si); // volatile
void mep_cpacmpgeu_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpacmpge_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpacmpge_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpacmpgeu_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpacmpgt_w (cp_v2si, cp_v2si); // volatile
void mep_cpacmpgtu_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpacmpgt_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpacmpgt_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpacmpgtu_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpacmpne_w (cp_v2si, cp_v2si); // volatile
void mep_cpacmpne_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpacmpne_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpacmpeq_w (cp_v2si, cp_v2si); // volatile
void mep_cpacmpeq_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpacmpeq_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpcmpge_w (cp_v2si, cp_v2si); // volatile
void mep_cpcmpgeu_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpcmpge_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpcmpge_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpcmpgeu_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpcmpgt_w (cp_v2si, cp_v2si); // volatile
void mep_cpcmpgtu_w (cp_v2usi, cp_v2usi); // volatile
void mep_cpcmpgt_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpcmpgt_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpcmpgtu_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_cpcmpne_w (cp_v2si, cp_v2si); // volatile
void mep_cpcmpne_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpcmpne_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpcmpeq_w (cp_v2si, cp_v2si); // volatile
void mep_cpcmpeq_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpcmpeq_b (cp_v8qi, cp_v8qi); // volatile
void mep_cpcmpeqz_b (cp_v8qi, cp_v8qi); // volatile
cp_data_bus_int mep_cdcastw (cp_data_bus_int);
cp_data_bus_int mep_cdcastuw (cp_data_bus_int);
cp_v2si mep_cpcasth_w (cp_v2si);
cp_v2si mep_cpcastuh_w (cp_v2si);
cp_v2si mep_cpcastb_w (cp_v2si);
cp_v2si mep_cpcastub_w (cp_v2si);
cp_v4hi mep_cpcastb_h (cp_v4hi);
cp_v4hi mep_cpcastub_h (cp_v4hi);
cp_v4hi mep_cpextl_h (cp_v4hi);
cp_v4uhi mep_cpextlu_h (cp_v4uhi);
cp_v8qi mep_cpextl_b (cp_v8qi);
cp_v8uqi mep_cpextlu_b (cp_v8uqi);
cp_v4uhi mep_cpextu_h (cp_v4uhi);
cp_v4uhi mep_cpextuu_h (cp_v4uhi);
cp_v8uqi mep_cpextu_b (cp_v8uqi);
cp_v8uqi mep_cpextuu_b (cp_v8uqi);
cp_v2si mep_cpbcast_w (cp_v2si);
cp_v4hi mep_cpbcast_h (cp_v4hi);
cp_v8qi mep_cpbcast_b (cp_v8qi);
void mep_cpccadd_b (cp_v8qi*); // volatile
cp_v2si mep_cphadd_w (cp_v2si);
cp_v4hi mep_cphadd_h (cp_v4hi);
cp_v8qi mep_cphadd_b (cp_v8qi);
cp_v8uqi mep_cphaddu_b (cp_v8uqi);
cp_v2si mep_cpnorm_w (cp_v2si);
cp_v4hi mep_cpnorm_h (cp_v4hi);
cp_v2si mep_cpldz_w (cp_v2si);
cp_v4hi mep_cpldz_h (cp_v4hi);
cp_v2si mep_cpabsz_w (cp_v2si);
cp_v4hi mep_cpabsz_h (cp_v4hi);
cp_v8qi mep_cpabsz_b (cp_v8qi);
void mep_cpmovtocc (cp_data_bus_int); // volatile
void mep_cpmovtocsar1 (cp_data_bus_int); // volatile
void mep_cpmovtocsar0 (cp_data_bus_int); // volatile
cp_data_bus_int mep_cpmovfrcc (); // volatile
cp_data_bus_int mep_cpmovfrcsar1 (); // volatile
cp_data_bus_int mep_cpmovfrcsar0 (); // volatile
cp_v2si mep_cpmin3_w (cp_v2si, cp_v2si);
cp_v2si mep_cpminu3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpmin3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpmin3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpminu3_b (cp_v8qi, cp_v8qi);
cp_v2si mep_cpmax3_w (cp_v2si, cp_v2si);
cp_v2si mep_cpmaxu3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpmax3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpmax3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpmaxu3_b (cp_v8qi, cp_v8qi);
cp_v4hi mep_cpabs3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpabs3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpabsu3_b (cp_v8qi, cp_v8qi);
cp_v2si mep_cpaddsr3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpaddsr3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpaddsr3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpaddsru3_b (cp_v8qi, cp_v8qi);
cp_v2si mep_cpave3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpave3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpave3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpaveu3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpextlsub3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpextlsubu3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpextusub3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpextusubu3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpextladd3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpextladdu3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpextuadd3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpextuaddu3_b (cp_v8qi, cp_v8qi);
cp_v2si mep_cpssub3_w (cp_v2si, cp_v2si); // volatile
cp_v4hi mep_cpssub3_h (cp_v4hi, cp_v4hi); // volatile
cp_v2si mep_cpsadd3_w (cp_v2si, cp_v2si); // volatile
cp_v4hi mep_cpsadd3_h (cp_v4hi, cp_v4hi); // volatile
cp_v2si mep_cpsla3_w (cp_v2si, cp_v2si); // volatile
cp_v4hi mep_cpsla3_h (cp_v4hi, cp_v4hi); // volatile
cp_data_bus_int mep_cdsll3 (cp_data_bus_int, cp_data_bus_int);
cp_v2si mep_cpssll3_w (cp_v2si, cp_v2si);
cp_v2si mep_cpsll3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpssll3_h (cp_v4hi, cp_v4hi);
cp_v4hi mep_cpsll3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpssll3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpsll3_b (cp_v8qi, cp_v8qi);
cp_data_bus_int mep_cdsra3 (cp_data_bus_int, cp_data_bus_int);
cp_v2si mep_cpssra3_w (cp_v2si, cp_v2si);
cp_v2si mep_cpsra3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpssra3_h (cp_v4hi, cp_v4hi);
cp_v4hi mep_cpsra3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpssra3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpsra3_b (cp_v8qi, cp_v8qi);
cp_data_bus_int mep_cdsrl3 (cp_data_bus_int, cp_data_bus_int);
cp_v2si mep_cpssrl3_w (cp_v2si, cp_v2si);
cp_v2si mep_cpsrl3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpssrl3_h (cp_v4hi, cp_v4hi);
cp_v4hi mep_cpsrl3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpssrl3_b (cp_v8qi, cp_v8qi);
cp_v8qi mep_cpsrl3_b (cp_v8qi, cp_v8qi);
cp_v4hi mep_cppack_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cppack_b (cp_v8qi, cp_v8qi);
cp_v8uqi mep_cppacku_b (cp_v8uqi, cp_v8uqi);
cp_v2si mep_cpunpackl_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpunpackl_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpunpackl_b (cp_v8qi, cp_v8qi);
cp_v2usi mep_cpunpacku_w (cp_v2usi, cp_v2usi);
cp_v4uhi mep_cpunpacku_h (cp_v4uhi, cp_v4uhi);
cp_v8uqi mep_cpunpacku_b (cp_v8uqi, cp_v8uqi);
cp_data_bus_int mep_cpfsftbs1 (cp_data_bus_int, cp_data_bus_int); // volatile
cp_data_bus_int mep_cpfsftbs0 (cp_data_bus_int, cp_data_bus_int); // volatile
cp_data_bus_int mep_cpfsftbi (cp_data_bus_int, cp_data_bus_int, long);
cp_data_bus_int mep_cpsel (cp_data_bus_int, cp_data_bus_int); // volatile
cp_vector mep_cpxor3 (cp_vector, cp_vector);
cp_vector mep_cpnor3 (cp_vector, cp_vector);
cp_vector mep_cpor3 (cp_vector, cp_vector);
cp_vector mep_cpand3 (cp_vector, cp_vector);
cp_data_bus_int mep_cdsub3 (cp_data_bus_int, cp_data_bus_int);
cp_v2si mep_cpsub3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpsub3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpsub3_b (cp_v8qi, cp_v8qi);
cp_data_bus_int mep_cdadd3 (cp_data_bus_int, cp_data_bus_int);
cp_v2si mep_cpadd3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpadd3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpadd3_b (cp_v8qi, cp_v8qi);
void mep_bsrv (void *);
void mep_jsrv (long);
void mep_synccp (); // volatile
void mep_bcpaf (long, void *);
void mep_bcpat (long, void *);
void mep_bcpne (long, void *);
void mep_bcpeq (long, void *);
void mep_lmcpm1 (cp_data_bus_int*, long **, long);
void mep_smcpm1 (cp_data_bus_int, long **, long);
void mep_lwcpm1 (cp_data_bus_int*, long **, long);
void mep_swcpm1 (cp_data_bus_int, long **, long);
void mep_lhcpm1 (cp_data_bus_int*, long **, long);
void mep_shcpm1 (cp_data_bus_int, long **, long);
void mep_lbcpm1 (cp_data_bus_int*, long **, long);
void mep_sbcpm1 (cp_data_bus_int, long **, long);
void mep_lmcpm0 (cp_data_bus_int*, long **, long);
void mep_smcpm0 (cp_data_bus_int, long **, long);
void mep_lwcpm0 (cp_data_bus_int*, long **, long);
void mep_swcpm0 (cp_data_bus_int, long **, long);
void mep_lhcpm0 (cp_data_bus_int*, long **, long);
void mep_shcpm0 (cp_data_bus_int, long **, long);
void mep_lbcpm0 (cp_data_bus_int*, long **, long);
void mep_sbcpm0 (cp_data_bus_int, long **, long);
void mep_lmcpa (cp_data_bus_int*, long **, long);
void mep_smcpa (cp_data_bus_int, long **, long);
void mep_lwcpa (cp_data_bus_int*, long **, long);
void mep_swcpa (cp_data_bus_int, long **, long);
void mep_lhcpa (cp_data_bus_int*, long **, long);
void mep_shcpa (cp_data_bus_int, long **, long);
void mep_lbcpa (cp_data_bus_int*, long **, long);
void mep_sbcpa (cp_data_bus_int, long **, long);
void mep_lmcp16 (cp_data_bus_int*, long, long *);
void mep_smcp16 (cp_data_bus_int, long, long *); // volatile
void mep_lwcp16 (cp_data_bus_int*, long, long *);
void mep_swcp16 (cp_data_bus_int, long, long *);
void mep_lmcpi (cp_data_bus_int*, long **);
void mep_smcpi (cp_data_bus_int, long **);
void mep_lwcpi (cp_data_bus_int*, long **);
void mep_swcpi (cp_data_bus_int, long **);
void mep_lmcp (cp_data_bus_int*, long *);
void mep_smcp (cp_data_bus_int, long *); // volatile
void mep_lwcp (cp_data_bus_int*, long *);
void mep_swcp (cp_data_bus_int, long *);
void mep_ssubu (long*, long);
void mep_saddu (long*, long);
void mep_ssub (long*, long);
void mep_sadd (long*, long);
void mep_clipu (long*, long);
void mep_clip (long*, long);
void mep_maxu (long*, long);
void mep_minu (long*, long);
void mep_max (long*, long);
void mep_min (long*, long);
void mep_ave (long*, long);
void mep_abs (long*, long);
void mep_ldz (long*, long);
void mep_dbreak (); // volatile
void mep_dret ();
void mep_divu (long, long);
void mep_div (long, long);
void mep_maddru (long*, long);
void mep_maddr (long*, long);
void mep_maddu (long, long);
void mep_madd (long, long);
void mep_mulru (long*, long);
void mep_mulr (long*, long);
void mep_mulu (long, long);
void mep_mul (long, long);
void mep_cache (long, long *); // volatile
void mep_tas (long*, long *);
void mep_btstm (long*, long *, long);
void mep_bnotm (long *, long);
void mep_bclrm (long *, long);
void mep_bsetm (long *, long);
void mep_ldcb (long*, long); // volatile
void mep_stcb (long, long); // volatile
void mep_syncm (); // volatile
void mep_break (); // volatile
void mep_swi (long); // volatile
void mep_sleep (); // volatile
void mep_halt (); // volatile
void mep_reti ();
void mep_ei (); // volatile
void mep_di (); // volatile
void mep_ldc (long*, long); // volatile
void mep_ldc_lo (long*);
void mep_ldc_hi (long*);
void mep_ldc_lp (long*);
void mep_stc (long, long); // volatile
void mep_stc_lo (long);
void mep_stc_hi (long);
void mep_stc_lp (long);
void mep_erepeat (void *);
void mep_repeat (long, void *);
void mep_ret ();
void mep_jsr (long);
void mep_jmp24 (void *);
void mep_jmp (long);
void mep_bsr24 (void *);
void mep_bsr12 (void *);
void mep_bne (long, long, void *);
void mep_beq (long, long, void *);
void mep_bgei (long, long, void *);
void mep_blti (long, long, void *);
void mep_bnei (long, long, void *);
void mep_beqi (long, long, void *);
void mep_bnez (long, void *);
void mep_beqz (long, void *);
void mep_bra (void *);
void mep_fsft (long*, long); // volatile
void mep_sll3 (long*, long, long);
void mep_slli (long*, long);
void mep_srli (long*, long);
void mep_srai (long*, long);
void mep_sll (long*, long);
void mep_srl (long*, long);
void mep_sra (long*, long);
void mep_xor3 (long*, long, long);
void mep_and3 (long*, long, long);
void mep_or3 (long*, long, long);
void mep_nor (long*, long);
void mep_xor (long*, long);
void mep_and (long*, long);
void mep_or (long*, long);
void mep_sltu3x (long*, long, long);
void mep_slt3x (long*, long, long);
void mep_add3x (long*, long, long);
void mep_sl2ad3 (long*, long, long);
void mep_sl1ad3 (long*, long, long);
void mep_sltu3i (long*, long, long);
void mep_slt3i (long*, long, long);
void mep_sltu3 (long*, long, long);
void mep_slt3 (long*, long, long);
void mep_neg (long*, long);
void mep_sbvck3 (long*, long, long);
void mep_sub (long*, long);
void mep_advck3 (long*, long, long);
void mep_add3i (long*, long);
void mep_add (long*, long);
void mep_add3 (long*, long, long);
void mep_movh (long*, long);
void mep_movu16 (long*, long);
void mep_movu24 (long*, long);
void mep_movi16 (long*, long);
void mep_movi8 (long*, long);
void mep_mov (long*, long);
void mep_ssarb (long, long); // volatile
void mep_extuh (long*);
void mep_extub (long*);
void mep_exth (long*);
void mep_extb (long*);
void mep_lw24 (long*, long);
void mep_sw24 (long, long);
void mep_lhu16 (long*, long, long *);
void mep_lbu16 (long*, long, long *);
void mep_lw16 (long*, long, long *);
void mep_lh16 (long*, long, long *);
void mep_lb16 (long*, long, long *);
void mep_sw16 (long, long, long *);
void mep_sh16 (long, long, long *);
void mep_sb16 (long, long, long *);
void mep_lhu_tp (long*, long);
void mep_lbu_tp (long*, long);
void mep_lw_tp (long*, long);
void mep_lh_tp (long*, long);
void mep_lb_tp (long*, long);
void mep_sw_tp (long, long);
void mep_sh_tp (long, long);
void mep_sb_tp (long, long);
void mep_lw_sp (long*, long);
void mep_sw_sp (long, long);
void mep_lhu (long*, long *);
void mep_lbu (long*, long *);
void mep_lw (long*, long *);
void mep_lh (long*, long *);
void mep_lb (long*, long *);
void mep_sw (long, long *);
void mep_sh (long, long *);
void mep_sb (long, long *);
void mep_dsp1 (long*, long); // volatile
void mep_dsp0 (long); // volatile
void mep_dsp (long*, long, long); // volatile
void mep_uci (long*, long, long); // volatile
void mep_lhucpm1 (cp_data_bus_int*, long **, long);
void mep_lbucpm1 (cp_data_bus_int*, long **, long);
void mep_lhucpm0 (cp_data_bus_int*, long **, long);
void mep_lbucpm0 (cp_data_bus_int*, long **, long);
void mep_lhucpa (cp_data_bus_int*, long **, long);
void mep_lbucpa (cp_data_bus_int*, long **, long);
void mep_lhucp (cp_data_bus_int*, long, long *);
void mep_lhcp (cp_data_bus_int*, long, long *);
void mep_shcp (cp_data_bus_int, long, long *);
void mep_lbucp (cp_data_bus_int*, long, long *);
void mep_lbcp (cp_data_bus_int*, long, long *);
void mep_sbcp (cp_data_bus_int, long, long *);
void mep_casw3 (long*, long, long); // volatile
void mep_cash3 (long*, long, long); // volatile
void mep_casb3 (long*, long, long); // volatile
void mep_prefd (long, long, long *); // volatile
void mep_pref (long, long *); // volatile
void mep_ldcb_r (long*, long *); // volatile
void mep_stcb_r (long, long *); // volatile
void mep_cmovh2 (long*, cp_data_bus_int);
void mep_cmovh1 (cp_data_bus_int*, long);
void mep_cmovc2 (long*, long); // volatile
void mep_cmovc1 (long, long); // volatile
void mep_cmov2 (long*, cp_data_bus_int);
void mep_cmov1 (cp_data_bus_int*, long);
cp_data_bus_int mep_cpmov (cp_data_bus_int);
gcc/config/mep/intrinsics.md deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/mep/ivc2-template.h deleted 100644 → 0
#undef __section
#define __section(_secname) __attribute__((section(#_secname)))
#undef mep_nop
#define mep_nop() __asm__ volatile ("nop")
#pragma GCC coprocessor available $c0...$c31
#pragma GCC coprocessor call_saved $c6...$c7
#include <intrinsics.h>
gcc/config/mep/mep-c5.cpu deleted 100644 → 0
; Toshiba MeP C5 Core description. -*- scheme -*-
; Copyright (C) 2009-2016 Free Software Foundation, Inc.
; Contributed by Red Hat, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
(dnf f-c5n4 "extended field" (all-mep-core-isas) 16 4)
(dnf f-c5n5 "extended field" (all-mep-core-isas) 20 4)
(dnf f-c5n6 "extended field" (all-mep-core-isas) 24 4)
(dnf f-c5n7 "extended field" (all-mep-core-isas) 28 4)
(dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)
(df f-12s20 "extended field" (all-mep-core-isas) 20 12 INT #f #f)
(dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)
(dnop cdisp12 "copro addend (12 bits)" (all-mep-core-isas) h-sint f-12s20)
(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
"stcb $rn,($rma)"
(+ MAJ_7 rn rma (f-sub4 12))
(c-call VOID "do_stcb" rn (and rma #xffff))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-stcb))))
(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
"ldcb $rn,($rma)"
(+ MAJ_7 rn rma (f-sub4 13))
(set rn (c-call SI "do_ldcb" (and rma #xffff)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-ldcb)
(unit u-exec)
(unit u-ldcb-gpr (out loadreg rn)))))
(dnci pref "cache prefetch" ((MACH c5) VOLATILE)
"pref $cimm4,($rma)"
(+ MAJ_7 cimm4 rma (f-sub4 5))
(sequence ()
(c-call VOID "check_option_dcache" pc)
(c-call VOID "do_cache_prefetch" cimm4 rma pc))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
"pref $cimm4,$sdisp16($rma)"
(+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16)
(sequence ()
(c-call VOID "check_option_dcache" pc)
(c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
"casb3 $rl5,$rn,($rm)"
(+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0))
(sequence ()
(c-call VOID "do_casb3" (index-of rl5) rn rm pc)
(set rl5 rl5)
)
((mep (unit u-use-gpr (in usereg rl5))
(unit u-load-gpr (out loadreg rl5))
(unit u-exec))))
(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
"cash3 $rl5,$rn,($rm)"
(+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1))
(sequence ()
(c-call VOID "do_cash3" (index-of rl5) rn rm pc)
(set rl5 rl5)
)
((mep (unit u-use-gpr (in usereg rl5))
(unit u-load-gpr (out loadreg rl5))
(unit u-exec))))
(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
"casw3 $rl5,$rn,($rm)"
(+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2))
(sequence ()
(c-call VOID "do_casw3" (index-of rl5) rn rm pc)
(set rl5 rl5)
)
((mep (unit u-use-gpr (in usereg rl5))
(unit u-load-gpr (out loadreg rl5))
(unit u-exec))))
(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
"sbcp $crn,$cdisp12($rma)"
(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
(set (mem QI (add rma (ext SI cdisp12))) (and crn #xff)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
"lbcp $crn,$cdisp12($rma)"
(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI (add rma (ext SI cdisp12))))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
"lbucp $crn,$cdisp12($rma)"
(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (zext SI (mem QI (add rma (ext SI cdisp12))))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
"shcp $crn,$cdisp12($rma)"
(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
(set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
"lhcp $crn,$cdisp12($rma)"
(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (add rma (ext SI cdisp12))))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
"lhucp $crn,$cdisp12($rma)"
(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (zext SI (mem HI (add rma (ext SI cdisp12))))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
"lbucpa $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (zext SI (mem QI rma)))
(set rma (add rma cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
"lhucpa $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (zext SI (mem HI (and rma (inv SI 1)))))
(set rma (add rma (ext SI cdisp10a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5))
"lbucpm0 $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (zext SI (mem QI rma)))
(set rma (mod0 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5))
"lhucpm0 $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (zext SI (mem HI (and rma (inv SI 1)))))
(set rma (mod0 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5))
"lbucpm1 $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (zext SI (mem QI rma)))
(set rma (mod1 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN (MACH c5))
"lhucpm1 $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (zext SI (mem HI (and rma (inv SI 1)))))
(set rma (mod1 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci uci "uci" ((MACH c5) VOLATILE)
"uci $rn,$rm,$uimm16"
(+ MAJ_15 rn rm (f-sub4 2) simm16)
(set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnf f-c5-rnm "register n/m" (all-mep-isas) 4 8)
(dnf f-c5-rm "register m" (all-mep-isas) 8 4)
(df f-c5-16u16 "general 16-bit u-val" (all-mep-isas) 16 16 UINT #f #f)
(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT
(f-c5-rm f-c5-16u16)
(sequence () ; insert
(set (ifield f-c5-rm) (srl (ifield f-c5-rmuimm20) 16))
(set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff))
)
(sequence () ; extract
(set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16)
(sll (ifield f-c5-rm) 16)))
)
)
(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20)
(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT
(f-c5-rnm f-c5-16u16)
(sequence () ; insert
(set (ifield f-c5-rnm) (srl (ifield f-c5-rnmuimm24) 16))
(set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff))
)
(sequence () ; extract
(set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16)
(sll (ifield f-c5-rnm) 16)))
)
)
(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24)
(dnci dsp "dsp" ((MACH c5) VOLATILE)
"dsp $rn,$rm,$uimm16"
(+ MAJ_15 rn rm (f-sub4 0) uimm16)
(set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci dsp0 "dsp0" ((MACH c5) VOLATILE NO-DIS ALIAS)
"dsp0 $c5rnmuimm24"
(+ MAJ_15 c5rnmuimm24 (f-sub4 0))
(c-call VOID "do_DSP" (zext SI c5rnmuimm24) pc)
((mep (unit u-exec))))
(dnci dsp1 "dsp1" ((MACH c5) VOLATILE NO-DIS ALIAS)
"dsp1 $rn,$c5rmuimm20"
(+ MAJ_15 rn (f-sub4 0) c5rmuimm20)
(set rn (c-call SI "do_DSP" rn (zext SI c5rmuimm20) pc))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
gcc/config/mep/mep-core.cpu deleted 100644 → 0
; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
; Copyright (C) 2001-2016 Free Software Foundation, Inc.
; Contributed by Red Hat, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
(include "simplify.inc")
(define-pmacro isa-enum ()
(isas mep
; begin-isa-enum
ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64
; end-isa-enum
)
)
(define-arch
(name mep)
(comment "Toshiba MeP Media Engine")
(insn-lsb0? #f) ;; work around cgen limitation
(machs mep h1 c5)
isa-enum
)
(define-isa
(name mep)
(comment "MeP core instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
; begin-isas
(define-isa
(name ext_core1)
(comment "MeP core extension instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_cop1_16)
(comment "MeP coprocessor instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_cop1_32)
(comment "MeP coprocessor instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_cop1_48)
(comment "MeP coprocessor instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_cop1_64)
(comment "MeP coprocessor instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
(define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32))
(define-pmacro all-core-isa-list () mep,ext_core1)
; end-isas
(define-cpu
(name mepf)
(comment "MeP family")
(endian either)
(insn-chunk-bitsize 16)
(word-bitsize 32)
)
(define-mach
(name mep)
(comment "MeP media engine")
(cpu mepf)
isa-enum
)
(define-mach
(name h1)
(comment "H1 media engine")
(cpu mepf)
isa-enum
)
(define-mach
(name c5)
(comment "C5 media engine")
(cpu mepf)
isa-enum
)
(define-model
(name mep)
(comment "MeP media engine processor")
(mach c5) ; mach gets changed by MeP-Integrator
(unit u-exec "execution unit" ()
1 1 ; issue done
() () () ())
; Branch unit
(unit u-branch "Branch Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((pc)) ; outputs
() ; profile action (default)
)
; Multiply unit
(unit u-multiply "Multiply Unit" ()
0 0 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Divide unit
(unit u-divide "Divide Unit" ()
0 0 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Stcb unit
(unit u-stcb "stcb Unit" ()
0 0 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Ldcb unit
(unit u-ldcb "ldcb Unit" ()
0 0 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Load gpr unit
(unit u-load-gpr "Load into GPR Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((loadreg INT -1)) ; outputs
() ; profile action (default)
)
(unit u-ldcb-gpr "Ldcb into GPR Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((loadreg INT -1)) ; outputs
() ; profile action (default)
)
; Multiply into GPR unit
(unit u-mul-gpr "Multiply into GPR Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((resultreg INT -1)) ; outputs
() ; profile action (default)
)
; Use gpr unit -- stalls if GPR not ready
(unit u-use-gpr "Use GPR Unit" ()
0 0 ; issue done
() ; state
((usereg INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Use ctrl-reg unit -- stalls if CTRL-REG not ready
(unit u-use-ctrl-reg "Use CTRL-REG Unit" ()
0 0 ; issue done
() ; state
((usereg INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Store ctrl-reg unit -- stalls if CTRL-REG not ready
(unit u-store-ctrl-reg "Store CTRL-REG Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((storereg INT -1)) ; outputs
() ; profile action (default)
)
)
; Hardware elements.
(dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ())
(define-hardware
(name h-gpr)
(comment "General purpose registers")
(attrs all-mep-isas CACHE-ADDR PROFILE)
(type register SI (16))
(indices keyword "$"
(("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5)
("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
; "$8" is the preferred name for register 8, but "$tp", "$gp"
; and "$sp" are preferred for their respective registers.
(fp 8) (tp 13) (gp 14) (sp 15)
("12" 12) ("13" 13) ("14" 14) ("15" 15)))
)
(define-hardware
(name h-csr)
(comment "Control/special registers")
(attrs all-mep-isas PROFILE)
(type register SI (32))
(indices keyword "$"
((pc 0) (lp 1) (sar 2) (rpb 4) (rpe 5) (rpc 6)
(hi 7) (lo 8) (mb0 12) (me0 13) (mb1 14) (me1 15)
(psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21)
(npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28)
; begin-extra-csr-registers
(vid 22)
; end-extra-csr-registers
))
(get (index) (c-call SI "cgen_get_csr_value" index))
(set (index newval) (c-call VOID "cgen_set_csr_value" index newval))
)
(define-pmacro (-reg-pair n) ((.sym n) n))
(define-hardware
(name h-cr64)
(comment "64-bit coprocessor registers")
(attrs all-mep-isas)
; This assumes that the data path of the co-pro is 64 bits.
(type register DI (32))
(indices keyword "$c" (.map -reg-pair (.iota 32)))
(set (index newval) (c-call VOID "h_cr64_queue_set" index newval))
)
(define-hardware
(name h-cr64-w)
(comment "64-bit coprocessor registers, pending writes")
(attrs all-mep-isas)
; This assumes that the data path of the co-pro is 64 bits.
(type register DI (32))
)
(define-hardware
(name h-cr)
(comment "32-bit coprocessor registers")
(attrs all-mep-isas VIRTUAL)
(type register SI (32))
(indices keyword "$c" (.map -reg-pair (.iota 32)))
(set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
(get (index) (trunc SI (c-call DI "h_cr64_get" index)))
)
;; Given a coprocessor control register number N, expand to a
;; name/index pair: ($ccrN N)
(define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n))
(define-hardware
(name h-ccr)
(comment "Coprocessor control registers")
(attrs all-mep-isas)
(type register SI (64))
(indices keyword "" (.map -ccr-reg-pair (.iota 64)))
(set (index newval) (c-call VOID "h_ccr_queue_set" index newval))
)
(define-hardware
(name h-ccr-w)
(comment "Coprocessor control registers, pending writes")
(attrs all-mep-isas)
(type register SI (64))
)
; Instruction fields. Bit numbering reversed.
; Conventions:
;
; N = number of bits in value
; A = alignment (2 or 4, omit for 1)
; B = leftmost (i.e. closest to zero) bit position
;
; -- Generic Fields (f-*) --
; N number of bits in *value* (1-24)
; [us] signed vs unsigned
; B position of left-most bit (4-16)
; aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc)
; n opt. for noncontiguous fields
; f-foo-{hi,lo} msb/lsb parts of field f-foo
;
; -- Operands --
; pcrelNaA PC-relative branch target (signed)
; pcabsNaA Absolute branch target (unsigned)
;
; [us]dispNaA [un]signed displacement
; [us]immN [un]signed immediate value
; addrNaA absolute address (unsigned)
;
; Additional prefixes may be used for special cases.
(dnf f-major "major opcode" (all-mep-core-isas) 0 4)
(dnf f-rn "register n" (all-mep-core-isas) 4 4)
(dnf f-rn3 "register 0-7" (all-mep-core-isas) 5 3)
(dnf f-rm "register m" (all-mep-core-isas) 8 4)
(dnf f-rl "register l" (all-mep-core-isas) 12 4)
(dnf f-sub2 "sub opcode (2 bits)" (all-mep-core-isas) 14 2)
(dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3)
(dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4)
(dnf f-ext "extended field" (all-mep-core-isas) 16 8)
(dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4)
(dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2)
(dnf f-crn "copro register n" (all-mep-core-isas) 4 4)
(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f)
(df f-csrn-lo "cr lo 4u8" (all-mep-core-isas) 8 4 UINT #f #f)
(define-multi-ifield
(name f-csrn)
(comment "control reg")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-csrn-hi f-csrn-lo)
(insert (sequence ()
(set (ifield f-csrn-lo) (and (ifield f-csrn) #xf))
(set (ifield f-csrn-hi) (srl (ifield f-csrn) 4))))
(extract (set (ifield f-csrn)
(or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo))))
)
(df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f)
(df f-crnx-lo "crx lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f)
(define-multi-ifield
(name f-crnx)
(comment "copro register n (0-31)")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-crnx-hi f-crnx-lo)
(insert (sequence ()
(set (ifield f-crnx-lo) (and (ifield f-crnx) #xf))
(set (ifield f-crnx-hi) (srl (ifield f-crnx) 4))))
(extract (set (ifield f-crnx)
(or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo))))
)
; Miscellaneous fields.
(define-pmacro (dnfb n)
(dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1))
; Define small fields used throughout the instruction set description.
; Each field (eg. `f-N') is at single bit field at position N.
(dnfb 0)
(dnfb 1)
(dnfb 2)
(dnfb 3)
(dnfb 4)
(dnfb 5)
(dnfb 6)
(dnfb 7)
(dnfb 8)
(dnfb 9)
(dnfb 10)
(dnfb 11)
(dnfb 12)
(dnfb 13)
(dnfb 14)
(dnfb 15)
(dnfb 16)
(dnfb 17)
(dnfb 18)
(dnfb 19)
(dnfb 20)
(dnfb 21)
(dnfb 22)
(dnfb 23)
(dnfb 24)
(dnfb 25)
(dnfb 26)
(dnfb 27)
(dnfb 28)
(dnfb 29)
(dnfb 30)
(dnfb 31)
; Branch/Jump target addresses
(df f-8s8a2 "pc-rel addr (8 bits)" (all-mep-core-isas PCREL-ADDR) 8 7 INT
((value pc) (sra SI (sub SI value pc) 1))
((value pc) (add SI (sll SI value 1) pc)))
(df f-12s4a2 "pc-rel addr (12 bits)" (all-mep-core-isas PCREL-ADDR) 4 11 INT
((value pc) (sra SI (sub SI value pc) 1))
((value pc) (add SI (sll SI value 1) pc)))
(df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT
((value pc) (sra SI (sub SI value pc) 1))
((value pc) (add SI (sll SI value 1) pc)))
(df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16 INT #f #f)
(df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR) 5 7 UINT #f #f)
(define-multi-ifield
(name f-24s5a2n)
(comment "pc-rel addr (24 bits align 2)")
(attrs all-mep-core-isas PCREL-ADDR)
(mode INT)
(subfields f-24s5a2n-hi f-24s5a2n-lo)
(insert (sequence ()
(set (ifield f-24s5a2n)
(sub (ifield f-24s5a2n) pc))
(set (ifield f-24s5a2n-lo)
(srl (and (ifield f-24s5a2n) #xfe) 1))
(set (ifield f-24s5a2n-hi)
(sra INT (ifield f-24s5a2n) 8))))
(extract (set (ifield f-24s5a2n)
(add SI (or (sll (ifield f-24s5a2n-hi) 8)
(sll (ifield f-24s5a2n-lo) 1))
pc)))
)
(df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
(df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas) 5 7 UINT #f #f)
(define-multi-ifield
(name f-24u5a2n)
(comment "abs jump target (24 bits, alignment 2)")
(attrs all-mep-core-isas ABS-ADDR)
(mode UINT)
(subfields f-24u5a2n-hi f-24u5a2n-lo)
(insert (sequence ()
(set (ifield f-24u5a2n-lo)
(srl (and (ifield f-24u5a2n) #xff) 1))
(set (ifield f-24u5a2n-hi)
(srl (ifield f-24u5a2n) 8))
))
(extract (set (ifield f-24u5a2n)
(or (sll (ifield f-24u5a2n-hi) 8)
(sll (ifield f-24u5a2n-lo) 1))))
)
; Displacement fields.
(df f-2u6 "SAR offset (2 bits)" (all-mep-core-isas) 6 2 UINT #f #f)
(df f-7u9 "tp-rel b (7 bits)" (all-mep-core-isas) 9 7 UINT #f #f)
(df f-7u9a2 "tp-rel h (7 bits)" (all-mep-core-isas) 9 6 UINT
((value pc) (srl SI value 1))
((value pc) (sll SI value 1)))
(df f-7u9a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas) 9 5 UINT
((value pc) (srl SI value 2))
((value pc) (sll SI value 2)))
(df f-16s16 "general 16-bit s-val" (all-mep-core-isas) 16 16 INT #f #f)
; Immediate fields.
(df f-2u10 "swi level (2 bits)" (all-mep-core-isas) 10 2 UINT #f #f)
(df f-3u5 "bit offset (3 bits)" (all-mep-core-isas) 5 3 UINT #f #f)
(df f-4u8 "bCC const (4 bits)" (all-mep-core-isas) 8 4 UINT #f #f)
(df f-5u8 "slt & shifts (5 bits)" (all-mep-core-isas) 8 5 UINT #f #f)
(df f-5u24 "clip immediate (5 bits)" (all-mep-core-isas) 24 5 UINT #f #f)
(df f-6s8 "add immediate (6 bits)" (all-mep-core-isas) 8 6 INT #f #f)
(df f-8s8 "add imm (8 bits)" (all-mep-core-isas) 8 8 INT #f #f)
(df f-16u16 "general 16-bit u-val" (all-mep-core-isas) 16 16 UINT #f #f)
(df f-12u16 "cmov fixed 1" (all-mep-core-isas) 16 12 UINT #f #f)
(df f-3u29 "cmov fixed 2" (all-mep-core-isas) 29 3 UINT #f #f)
; These are all for the coprocessor opcodes
; The field is like IJKiiiiiii where I and J are toggled if K is set,
; for compatibility with older cores.
(define-pmacro (compute-cdisp10 val)
(cond SI
((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200)
(sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400))
(else
(cond SI ((and SI val #x80) (xor SI val #x300)) (else val)))
)
)
(define-pmacro (extend-cdisp10 val)
(cond SI
((and SI (compute-cdisp10 val) #x200)
(sub (and SI (compute-cdisp10 val) #x3ff) #x400))
(else
(and SI (compute-cdisp10 val) #x3ff))
)
)
(df f-cdisp10 "cop imm10" (all-mep-core-isas) 22 10 INT
((value pc) (extend-cdisp10 value))
((value pc) (extend-cdisp10 value))
)
; Non-contiguous fields.
(df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
(df f-24u8a4n-lo "24u8a4n lo 8u8a4" (all-mep-core-isas) 8 6 UINT #f #f)
(define-multi-ifield
(name f-24u8a4n)
(comment "absolute 24-bit address")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-24u8a4n-hi f-24u8a4n-lo)
(insert (sequence ()
(set (ifield f-24u8a4n-hi) (srl (ifield f-24u8a4n) 8))
(set (ifield f-24u8a4n-lo) (srl (and (ifield f-24u8a4n) #xfc) 2))))
(extract (set (ifield f-24u8a4n)
(or (sll (ifield f-24u8a4n-hi) 8)
(sll (ifield f-24u8a4n-lo) 2))))
)
(df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
(df f-24u8n-lo "24u8n lo 8u8" (all-mep-core-isas) 8 8 UINT #f #f)
(define-multi-ifield
(name f-24u8n)
(comment "24-bit constant")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-24u8n-hi f-24u8n-lo)
(insert (sequence ()
(set (ifield f-24u8n-hi) (srl (ifield f-24u8n) 8))
(set (ifield f-24u8n-lo) (and (ifield f-24u8n) #xff))))
(extract (set (ifield f-24u8n)
(or (sll (ifield f-24u8n-hi) 8)
(ifield f-24u8n-lo))))
)
(df f-24u4n-hi "24u4n hi 8u4" (all-mep-core-isas) 4 8 UINT #f #f)
(df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
(define-multi-ifield
(name f-24u4n)
(comment "coprocessor code")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-24u4n-hi f-24u4n-lo)
(insert (sequence ()
(set (ifield f-24u4n-hi) (srl (ifield f-24u4n) 16))
(set (ifield f-24u4n-lo) (and (ifield f-24u4n) #xffff))))
(extract (set (ifield f-24u4n)
(or (sll (ifield f-24u4n-hi) 16)
(ifield f-24u4n-lo))))
)
(define-multi-ifield
(name f-callnum)
(comment "system call number field")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-5 f-6 f-7 f-11)
(insert (sequence ()
(set (ifield f-5) (and (srl (ifield f-callnum) 3) 1))
(set (ifield f-6) (and (srl (ifield f-callnum) 2) 1))
(set (ifield f-7) (and (srl (ifield f-callnum) 1) 1))
(set (ifield f-11) (and (ifield f-callnum) 1))))
(extract (set (ifield f-callnum)
(or (sll (ifield f-5) 3)
(or (sll (ifield f-6) 2)
(or (sll (ifield f-7) 1)
(ifield f-11))))))
)
(df f-ccrn-hi "ccrn hi 2u28" (all-mep-core-isas) 28 2 UINT #f #f)
(df f-ccrn-lo "ccrn lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f)
(define-multi-ifield
(name f-ccrn)
(comment "Coprocessor register number field")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-ccrn-hi f-ccrn-lo)
(insert (sequence ()
(set (ifield f-ccrn-hi) (and (srl (ifield f-ccrn) 4) #x3))
(set (ifield f-ccrn-lo) (and (ifield f-ccrn) #xf))))
(extract (set (ifield f-ccrn)
(or (sll (ifield f-ccrn-hi) 4)
(ifield f-ccrn-lo))))
)
; Operands.
;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct
;; operation. The others are mostly kept for backwards compatibility,
;; although they do affect the dummy prototypes in
;; gcc/config/mep/intrinsics.h.
(define-attr
(type enum)
(for operand)
(name CDATA)
(comment "datatype to use for C intrinsics mapping")
(values LABEL REGNUM FMAX_FLOAT FMAX_INT
POINTER LONG ULONG SHORT USHORT CHAR UCHAR CP_DATA_BUS_INT)
(default LONG))
(define-attr
(type enum)
(for insn)
(name CPTYPE)
(comment "datatype to use for coprocessor values")
(values CP_DATA_BUS_INT VECT V2SI V4HI V8QI V2USI V4UHI V8UQI)
(default CP_DATA_BUS_INT))
(define-attr
(type enum)
(for insn)
(name CRET)
;; VOID - all arguments are passed as parameters; if any are written, pointers to them are passed.
;; FIRST - the first argument is the return value.
;; FIRSTCOPY - the first argument is the return value, but a copy is also the first parameter.
(values VOID FIRST FIRSTCOPY)
(default VOID)
(comment "Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it."))
(define-attr
(type integer)
(for operand)
(name ALIGN)
(comment "alignment of immediate operands")
(default 1))
(define-attr
(for operand)
(type boolean)
(name RELOC_IMPLIES_OVERFLOW)
(comment "Operand should not be considered as a candidate for relocs"))
(define-attr
(for hardware)
(type boolean)
(name IS_FLOAT)
(comment "Register contains a floating point value"))
(define-pmacro (dpop name commment attrib hwr field func)
(define-full-operand name comment attrib
hwr DFLT field ((parse func)) () ()))
(define-pmacro (dprp name commment attrib hwr field pafunc prfunc)
(define-full-operand name comment attrib
hwr DFLT field ((parse pafunc) (print prfunc)) () ()))
(dnop r0 "register 0" (all-mep-core-isas) h-gpr 0)
(dnop rn "register Rn" (all-mep-core-isas) h-gpr f-rn)
(dnop rm "register Rm" (all-mep-core-isas) h-gpr f-rm)
(dnop rl "register Rl" (all-mep-core-isas) h-gpr f-rl)
(dnop rn3 "register 0-7" (all-mep-core-isas) h-gpr f-rn3)
;; Variants of RM/RN with different CDATA attributes. See comment above
;; CDATA for more details.
(dnop rma "register Rm holding pointer" (all-mep-core-isas (CDATA POINTER)) h-gpr f-rm)
(dnop rnc "register Rn holding char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
(dnop rnuc "register Rn holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
(dnop rns "register Rn holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
(dnop rnus "register Rn holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
(dnop rnl "register Rn holding long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
(dnop rnul "register Rn holding unsigned long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn)
(dnop rn3c "register 0-7 holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
(dnop rn3uc "register 0-7 holding byte" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
(dnop rn3s "register 0-7 holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
(dnop rn3us "register 0-7 holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
(dnop rn3l "register 0-7 holding unsigned long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
(dnop rn3ul "register 0-7 holding long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn3)
(dnop lp "link pointer" (all-mep-core-isas) h-csr 1)
(dnop sar "shift amount register" (all-mep-core-isas) h-csr 2)
(dnop hi "high result" (all-mep-core-isas) h-csr 7)
(dnop lo "low result" (all-mep-core-isas) h-csr 8)
(dnop mb0 "modulo begin register 0" (all-mep-core-isas) h-csr 12)
(dnop me0 "modulo end register 0" (all-mep-core-isas) h-csr 13)
(dnop mb1 "modulo begin register 1" (all-mep-core-isas) h-csr 14)
(dnop me1 "modulo end register 1" (all-mep-core-isas) h-csr 15)
(dnop psw "program status word" (all-mep-core-isas) h-csr 16)
(dnop epc "exception prog counter" (all-mep-core-isas) h-csr 19)
(dnop exc "exception cause" (all-mep-core-isas) h-csr 20)
(dnop npc "nmi program counter" (all-mep-core-isas) h-csr 23)
(dnop dbg "debug register" (all-mep-core-isas) h-csr 24)
(dnop depc "debug exception pc" (all-mep-core-isas) h-csr 25)
(dnop opt "option register" (all-mep-core-isas) h-csr 26)
(dnop r1 "register 1" (all-mep-core-isas) h-gpr 1)
(dnop tp "tiny data area pointer" (all-mep-core-isas) h-gpr 13)
(dnop sp "stack pointer" (all-mep-core-isas) h-gpr 15)
(dprp tpr "TP register" (all-mep-core-isas) h-gpr 13 "tpreg" "tpreg")
(dprp spr "SP register" (all-mep-core-isas) h-gpr 15 "spreg" "spreg")
(define-full-operand
csrn "control/special register" (all-mep-core-isas (CDATA REGNUM)) h-csr
DFLT f-csrn ((parse "csrn")) () ()
)
(dnop csrn-idx "control/special reg idx" (all-mep-core-isas) h-uint f-csrn)
(dnop crn64 "copro Rn (64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crn)
(dnop crn "copro Rn (32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crn)
(dnop crnx64 "copro Rn (0-31, 64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crnx)
(dnop crnx "copro Rn (0-31, 32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crnx)
(dnop ccrn "copro control reg CCRn" (all-mep-core-isas (CDATA REGNUM)) h-ccr f-ccrn)
(dnop cccc "copro flags" (all-mep-core-isas) h-uint f-rm)
(dprp pcrel8a2 "pc-rel addr (8 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-8s8a2 "mep_align" "address")
(dprp pcrel12a2 "pc-rel addr (12 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-12s4a2 "mep_align" "address")
(dprp pcrel17a2 "pc-rel addr (17 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-17s16a2 "mep_align" "address")
(dprp pcrel24a2 "pc-rel addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-sint f-24s5a2n "mep_align" "address")
(dprp pcabs24a2 "pc-abs addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-uint f-24u5a2n "mep_alignu" "address")
(dpop sdisp16 "displacement (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16")
(dpop simm16 "signed imm (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16")
(dpop uimm16 "unsigned imm (16 bits)" (all-mep-core-isas) h-uint f-16u16 "unsigned16")
(dnop code16 "uci/dsp code (16 bits)" (all-mep-core-isas) h-uint f-16u16)
(dnop udisp2 "SSARB addend (2 bits)" (all-mep-core-isas) h-sint f-2u6)
(dnop uimm2 "interrupt (2 bits)" (all-mep-core-isas) h-uint f-2u10)
(dnop simm6 "add const (6 bits)" (all-mep-core-isas) h-sint f-6s8)
(dnop simm8 "mov const (8 bits)" (all-mep-core-isas RELOC_IMPLIES_OVERFLOW)
h-sint f-8s8)
(dpop addr24a4 "sw/lw addr (24 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-24u8a4n "mep_alignu")
(dnop code24 "coprocessor code" (all-mep-core-isas) h-uint f-24u4n)
(dnop callnum "system call number" (all-mep-core-isas) h-uint f-callnum)
(dnop uimm3 "bit immediate (3 bits)" (all-mep-core-isas) h-uint f-3u5)
(dnop uimm4 "bCC const (4 bits)" (all-mep-core-isas) h-uint f-4u8)
(dnop uimm5 "bit/shift val (5 bits)" (all-mep-core-isas) h-uint f-5u8)
(dpop udisp7 "tp-rel b (7 bits)" (all-mep-core-isas) h-uint f-7u9 "unsigned7")
(dpop udisp7a2 "tp-rel h (7 bits)" (all-mep-core-isas (ALIGN 2)) h-uint f-7u9a2 "unsigned7")
(dpop udisp7a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "unsigned7")
(dpop uimm7a4 "sp w-addend (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "mep_alignu")
(dnop uimm24 "immediate (24 bits)" (all-mep-core-isas) h-uint f-24u8n)
(dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn)
(dnop cimm5 "clip immediate (5 bits)" (all-mep-core-isas) h-uint f-5u24)
(dpop cdisp10 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
(dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
(dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
(dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
; Special operand representing the various ways that the literal zero can be
; specified.
(define-full-operand
zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil
((parse "zero")) () ()
)
; Attributes.
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_BIT_INSN)
(comment "optional bit manipulation instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_MUL_INSN)
(comment "optional 32-bit multiply instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_DIV_INSN)
(comment "optional 32-bit divide instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_DEBUG_INSN)
(comment "optional debug instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_LDZ_INSN)
(comment "optional leading zeroes instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_ABS_INSN)
(comment "optional absolute difference instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_AVE_INSN)
(comment "optional average instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_MINMAX_INSN)
(comment "optional min/max instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_CLIP_INSN)
(comment "optional clipping instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_SAT_INSN)
(comment "optional saturation instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_UCI_INSN)
(comment "optional UCI instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_DSP_INSN)
(comment "optional DSP instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_CP_INSN)
(comment "optional coprocessor-related instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_CP64_INSN)
(comment "optional coprocessor-related 64 data bit instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_VLIW64)
(comment "optional vliw64 mode (vliw32 is default)"))
(define-attr
(for insn)
(type enum)
(name STALL)
(attrs META)
(values NONE SHIFTI INT2 LOAD STORE LDC STC LDCB STCB SSARB FSFT RET
ADVCK MUL MULR DIV)
(default NONE)
(comment "gcc stall attribute"))
(define-attr
(for insn)
(type string)
(name INTRINSIC)
(attrs META)
(comment "gcc intrinsic name"))
(define-attr
(for insn)
(type enum)
(name SLOT)
(attrs META)
(values NONE C3 V1 V3 P0S P0 P1)
(default NONE)
(comment "coprocessor slot type"))
(define-attr
(for insn)
(type boolean)
(name MAY_TRAP)
(comment "instruction may generate an exception"))
; Attributes for scheduling restrictions in vliw mode
(define-attr
(for insn)
(type boolean)
(name VLIW_ALONE)
(comment "instruction can be scheduled alone in vliw mode"))
(define-attr
(for insn)
(type boolean)
(name VLIW_NO_CORE_NOP)
(comment "there is no corresponding nop core instruction"))
(define-attr
(for insn)
(type boolean)
(name VLIW_NO_COP_NOP)
(comment "there is no corresponding nop coprocessor instruction"))
(define-attr
(for insn)
(type boolean)
(name VLIW64_NO_MATCHING_NOP)
(comment "there is no corresponding nop coprocessor instruction"))
(define-attr
(for insn)
(type boolean)
(name VLIW32_NO_MATCHING_NOP)
(comment "there is no corresponding nop coprocessor instruction"))
(define-attr
(for insn)
(type boolean)
(name VOLATILE)
(comment "Insn is volatile."))
(define-attr
(for insn)
(type integer)
(name LATENCY)
(comment "The latency of this insn, used for scheduling as an intrinsic in gcc")
(default 0))
; The MeP config tool will edit this.
(define-attr
(type enum)
(for insn)
(name CONFIG)
(values NONE ; config-attr-start
default
) ; config-attr-end
)
; Enumerations.
(define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_
f-major
(.map .str (.iota 16))
)
(define-pmacro (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming isa)
(define-insn
(name xname)
(comment xcomment)
(.splice attrs (.unsplice xattrs) (ISA isa))
(syntax xsyntax)
(format xformat)
(semantics xsemantics)
(.splice timing (.unsplice xtiming))
)
)
(define-pmacro (dnmi-isa xname xcomment xattrs xsyntax xemit isa)
(dnmi xname xcomment (.splice (.unsplice xattrs) (ISA isa)) xsyntax xemit)
)
; For making profiling calls and dynamic configuration
(define-pmacro (cg-profile caller callee)
(c-call "cg_profile" caller callee)
)
; For dynamic configuration only
(define-pmacro (cg-profile-jump caller callee)
(c-call "cg_profile_jump" caller callee)
)
; For defining Core Instructions
(define-pmacro (dnci xname xcomment xattrs xsyntax xformat xsemantics xtiming)
(dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming all-core-isa-list)
)
(define-pmacro (dncmi xname xcomment xattrs xsyntax xemit)
(dnmi-isa xname xcomment xattrs xsyntax xemit all-core-isa-list)
)
; For defining Coprocessor Instructions
;(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming cop)
;)
;; flag setting macro
(define-pmacro (set-bit xop xbitnum xval)
(set xop (or
(and xop (inv (sll 1 xbitnum)))
(and (sll 1 xbitnum) (sll xval xbitnum)))))
;; some flags we commonly use in vliw reasoning / mode-switching etc.
(define-pmacro (get-opt.vliw64) (and (srl opt 6) 1))
(define-pmacro (get-opt.vliw32) (and (srl opt 5) 1))
(define-pmacro (get-rm.lsb) (and rm 1))
(define-pmacro (get-psw.om) (and (srl psw 12) 1))
(define-pmacro (get-psw.nmi) (and (srl psw 9) 1))
(define-pmacro (get-psw.iep) (and (srl psw 1) 1))
(define-pmacro (get-psw.ump) (and (srl psw 3) 1))
(define-pmacro (get-epc.etom) (and epc 1))
(define-pmacro (get-npc.ntom) (and npc 1))
(define-pmacro (get-lp.ltom) (and lp 1))
(define-pmacro (set-psw.om zval) (set-bit (raw-reg h-csr 16) 12 zval))
(define-pmacro (set-psw.nmi zval) (set-bit (raw-reg h-csr 16) 9 zval))
(define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval))
(define-pmacro (set-psw.iec zval) (set-bit (raw-reg h-csr 16) 0 zval))
(define-pmacro (set-rpe.elr zval) (set-bit (raw-reg h-csr 5) 0 zval))
;; the "3 way switch" depending on our current operating mode and vliw status flags
(define-pmacro (core-vliw-switch core-rtl vliw32-rtl vliw64-rtl)
(cond
((andif (get-psw.om) (get-opt.vliw64)) vliw64-rtl)
((andif (get-psw.om) (get-opt.vliw32)) vliw32-rtl)
(else core-rtl)))
;; the varying-pcrel idiom
(define-pmacro (set-vliw-modified-pcrel-offset xtarg xa xb xc)
(core-vliw-switch (set xtarg (add pc xa))
(set xtarg (add pc xb))
(set xtarg (add pc xc))))
;; the increasing-alignment idiom in branch displacements
(define-pmacro (set-vliw-alignment-modified xtarg zaddr)
(core-vliw-switch (set xtarg (and zaddr (inv 1)))
(set xtarg (and zaddr (inv 3)))
(set xtarg (and zaddr (inv 7)))))
;; the increasing-alignment idiom in option-only form
(define-pmacro (set-vliw-aliignment-modified-by-option xtarg zaddr)
(if (get-opt.vliw32)
(set xtarg (and zaddr (inv 3)))
(set xtarg (and zaddr (inv 7)))))
; pmacros needed for coprocessor modulo addressing.
; Taken from supplement ``The operation of the modulo addressing'' in
; Toshiba documentation rev 2.2, p. 34.
(define-pmacro (compute-mask0)
(sequence SI ((SI temp))
(set temp (or mb0 me0))
(srl (const SI -1) (c-call SI "do_ldz" temp))))
(define-pmacro (mod0 immed)
(sequence SI ((SI modulo-mask))
(set modulo-mask (compute-mask0))
(if SI (eq (and rma modulo-mask) me0)
(or (and rma (inv modulo-mask)) mb0)
(add rma (ext SI immed)))))
(define-pmacro (compute-mask1)
(sequence SI ((SI temp))
(set temp (or mb1 me1))
(srl (const SI -1) (c-call SI "do_ldz" temp))))
(define-pmacro (mod1 immed)
(sequence SI ((SI modulo-mask))
(set modulo-mask (compute-mask1))
(if SI (eq (and rma modulo-mask) me1)
(or (and rma (inv modulo-mask)) mb1)
(add rma (ext SI immed)))))
; Instructions.
; A pmacro for use in semantic bodies of unimplemented insns.
(define-pmacro (unimp mnemonic) (nop))
; Core specific instructions
; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator
(include "mep-c5.cpu") ; -- exposed by MeP-Integrator
; Load/store instructions.
(dnci sb "store byte (register indirect)" ((STALL STORE))
"sb $rnc,($rma)"
(+ MAJ_0 rnc rma (f-sub4 8))
(sequence ()
(c-call VOID "check_write_to_text" rma)
(set (mem UQI rma) (and rnc #xff)))
((mep (unit u-use-gpr (in usereg rnc))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sh "store half-word (register indirect)" ((STALL STORE))
"sh $rns,($rma)"
(+ MAJ_0 rns rma (f-sub4 9))
(sequence ()
(c-call VOID "check_write_to_text" (and rma (inv 1)))
(set (mem UHI (and rma (inv 1))) (and rns #xffff)))
((mep (unit u-use-gpr (in usereg rns))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sw "store word (register indirect)" ((STALL STORE))
"sw $rnl,($rma)"
(+ MAJ_0 rnl rma (f-sub4 10))
(sequence ()
(c-call VOID "check_write_to_text" (and rma (inv 3)))
(set (mem USI (and rma (inv 3))) rnl))
((mep (unit u-use-gpr (in usereg rnl))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lb "load byte (register indirect)" ((STALL LOAD) (LATENCY 2))
"lb $rnc,($rma)"
(+ MAJ_0 rnc rma (f-sub4 12))
(set rnc (ext SI (mem QI rma)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnc)))))
(dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
"lh $rns,($rma)"
(+ MAJ_0 rns rma (f-sub4 13))
(set rns (ext SI (mem HI (and rma (inv 1)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rns)))))
(dnci lw "load word (register indirect)" ((STALL LOAD) (LATENCY 2))
"lw $rnl,($rma)"
(+ MAJ_0 rnl rma (f-sub4 14))
(set rnl (mem SI (and rma (inv 3))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnl)))))
(dnci lbu "load unsigned byte (register indirect)" ((STALL LOAD) (LATENCY 2))
"lbu $rnuc,($rma)"
(+ MAJ_0 rnuc rma (f-sub4 11))
(set rnuc (zext SI (mem UQI rma)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnuc)))))
(dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
"lhu $rnus,($rma)"
(+ MAJ_0 rnus rma (f-sub4 15))
(set rnus (zext SI (mem UHI (and rma (inv 1)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnus)))))
(dnci sw-sp "store word (sp relative)" ((STALL STORE))
"sw $rnl,$udisp7a4($spr)"
(+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 2))
(sequence ()
(c-call VOID "check_write_to_text" (and (add udisp7a4 sp) (inv 3)))
(set (mem SI (and (add udisp7a4 sp) (inv 3))) rnl))
((mep (unit u-use-gpr (in usereg rnl))
(unit u-use-gpr (in usereg sp))
(unit u-exec))))
(dnci lw-sp "load word (sp relative)" ((STALL LOAD) (LATENCY 2))
"lw $rnl,$udisp7a4($spr)"
(+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 3))
(set rnl (mem SI (and (add udisp7a4 sp) (inv 3))))
((mep (unit u-use-gpr (in usereg sp))
(unit u-exec)
(unit u-load-gpr (out loadreg rnl)))))
(dnci sb-tp "store byte (tp relative)" ((STALL STORE))
"sb $rn3c,$udisp7($tpr)"
(+ MAJ_8 (f-4 0) rn3c (f-8 0) udisp7)
(sequence ()
(c-call VOID "check_write_to_text" (add (zext SI udisp7) tp))
(set (mem QI (add (zext SI udisp7) tp)) (and rn3c #xff)))
((mep (unit u-use-gpr (in usereg rn3c))
(unit u-use-gpr (in usereg tp))
(unit u-exec))))
(dnci sh-tp "store half-word (tp relative)" ((STALL STORE))
"sh $rn3s,$udisp7a2($tpr)"
(+ MAJ_8 (f-4 0) rn3s (f-8 1) udisp7a2 (f-15 0))
(sequence ()
(c-call VOID "check_write_to_text" (and (add (zext SI udisp7a2) tp) (inv 1)))
(set (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))) (and rn3s #xffff)))
((mep (unit u-use-gpr (in usereg rn3s))
(unit u-use-gpr (in usereg tp))
(unit u-exec))))
(dnci sw-tp "store word (tp relative)" ((STALL STORE))
"sw $rn3l,$udisp7a4($tpr)"
(+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 2))
(sequence ()
(c-call VOID "check_write_to_text" (and (add (zext SI udisp7a4) tp) (inv 3)))
(set (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))) rn3l))
((mep (unit u-use-gpr (in usereg rn3l))
(unit u-use-gpr (in usereg tp))
(unit u-exec))))
(dnci lb-tp "load byte (tp relative)" ((STALL LOAD) (LATENCY 2))
"lb $rn3c,$udisp7($tpr)"
(+ MAJ_8 (f-4 1) rn3c (f-8 0) udisp7)
(set rn3c (ext SI (mem QI (add (zext SI udisp7) tp))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3c)))))
(dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
"lh $rn3s,$udisp7a2($tpr)"
(+ MAJ_8 (f-4 1) rn3s (f-8 1) udisp7a2 (f-15 0))
(set rn3s (ext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3s)))))
(dnci lw-tp "load word (tp relative)" ((STALL LOAD) (LATENCY 2))
"lw $rn3l,$udisp7a4($tpr)"
(+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 3))
(set rn3l (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3l)))))
(dnci lbu-tp "load unsigned byte (tp relative)" ((STALL LOAD) (LATENCY 2))
"lbu $rn3uc,$udisp7($tpr)"
(+ MAJ_4 (f-4 1) rn3uc (f-8 1) udisp7)
(set rn3uc (zext SI (mem QI (add (zext SI udisp7) tp))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3uc)))))
(dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
"lhu $rn3us,$udisp7a2($tpr)"
(+ MAJ_8 (f-4 1) rn3us (f-8 1) udisp7a2 (f-15 1))
(set rn3us (zext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3us)))))
(dnci sb16 "store byte (16 bit displacement)" ((STALL STORE))
"sb $rnc,$sdisp16($rma)"
(+ MAJ_12 rnc rma (f-sub4 8) sdisp16)
(sequence ()
(c-call VOID "check_write_to_text" (add rma (ext SI sdisp16)))
(set (mem QI (add rma (ext SI sdisp16))) (and rnc #xff)))
((mep (unit u-use-gpr (in usereg rnc))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE))
"sh $rns,$sdisp16($rma)"
(+ MAJ_12 rns rma (f-sub4 9) sdisp16)
(sequence ()
(c-call VOID "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 1)))
(set (mem HI (and (add rma (ext SI sdisp16)) (inv 1))) (and rns #xffff)))
((mep (unit u-use-gpr (in usereg rns))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sw16 "store word (16 bit displacement)" ((STALL STORE))
"sw $rnl,$sdisp16($rma)"
(+ MAJ_12 rnl rma (f-sub4 10) sdisp16)
(sequence ()
(c-call "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 3)))
(set (mem SI (and (add rma (ext SI sdisp16)) (inv 3))) rnl))
((mep (unit u-use-gpr (in usereg rnl))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lb16 "load byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lb $rnc,$sdisp16($rma)"
(+ MAJ_12 rnc rma (f-sub4 12) sdisp16)
(set rnc (ext SI (mem QI (add rma (ext SI sdisp16)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnc)))))
(dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lh $rns,$sdisp16($rma)"
(+ MAJ_12 rns rma (f-sub4 13) sdisp16)
(set rns (ext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rns)))))
(dnci lw16 "load word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lw $rnl,$sdisp16($rma)"
(+ MAJ_12 rnl rma (f-sub4 14) sdisp16)
(set rnl (mem SI (and (add rma (ext SI sdisp16)) (inv 3))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnl)))))
(dnci lbu16 "load unsigned byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lbu $rnuc,$sdisp16($rma)"
(+ MAJ_12 rnuc rma (f-sub4 11) sdisp16)
(set rnuc (zext SI (mem QI (add rma (ext SI sdisp16)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnuc)))))
(dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lhu $rnus,$sdisp16($rma)"
(+ MAJ_12 rnus rma (f-sub4 15) sdisp16)
(set rnus (zext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnus)))))
(dnci sw24 "store word (24 bit absolute addressing)" ((STALL STORE))
"sw $rnl,($addr24a4)"
(+ MAJ_14 rnl addr24a4 (f-sub2 2))
(sequence ()
(c-call VOID "check_write_to_text" (zext SI addr24a4))
(set (mem SI (zext SI addr24a4)) rnl))
((mep (unit u-use-gpr (in usereg rnl))
(unit u-exec))))
(dnci lw24 "load word (24 bit absolute addressing)" ((STALL LOAD) (LATENCY 2))
"lw $rnl,($addr24a4)"
(+ MAJ_14 rnl addr24a4 (f-sub2 3))
(set rnl (mem SI (zext SI addr24a4)))
((mep (unit u-exec)
(unit u-load-gpr (out loadreg rnl)))))
; Extension instructions.
(dnci extb "sign extend byte" ()
"extb $rn"
(+ MAJ_1 rn (f-rm 0) (f-sub4 13))
(set rn (ext SI (and QI rn #xff)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci exth "sign extend half-word" ()
"exth $rn"
(+ MAJ_1 rn (f-rm 2) (f-sub4 13))
(set rn (ext SI (and HI rn #xffff)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci extub "zero extend byte" ()
"extub $rn"
(+ MAJ_1 rn (f-rm 8) (f-sub4 13))
(set rn (zext SI (and rn #xff)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci extuh "zero extend half-word" ()
"extuh $rn"
(+ MAJ_1 rn (f-rm 10) (f-sub4 13))
(set rn (zext SI (and rn #xffff)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
; Shift amount manipulation instructions.
(dnci ssarb "set sar to bytes" ((STALL SSARB) VOLATILE)
"ssarb $udisp2($rm)"
(+ MAJ_1 (f-4 0) (f-5 0) udisp2 rm (f-sub4 12))
(if (c-call BI "big_endian_p")
(set sar (zext SI (mul (and (add udisp2 rm) 3) 8)))
(set sar (sub 32 (zext SI (mul (and (add udisp2 rm) 3) 8)))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Move instructions.
(dnci mov "move" ()
"mov $rn,$rm"
(+ MAJ_0 rn rm (f-sub4 0))
(set rn rm)
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci movi8 "move 8-bit immediate" ()
"mov $rn,$simm8"
(+ MAJ_5 rn simm8)
(set rn (ext SI simm8))
())
(dnci movi16 "move 16-bit immediate" ()
"mov $rn,$simm16"
(+ MAJ_12 rn (f-rm 0) (f-sub4 1) simm16)
(set rn (ext SI simm16))
())
(dnci movu24 "move 24-bit unsigned immediate" ()
"movu $rn3,$uimm24"
(+ MAJ_13 (f-4 0) rn3 uimm24)
(set rn3 (zext SI uimm24))
())
(dnci movu16 "move 16-bit unsigned immediate" ()
"movu $rn,$uimm16"
(+ MAJ_12 rn (f-rm 1) (f-sub4 1) uimm16)
(set rn (zext SI uimm16))
())
(dnci movh "move high 16-bit immediate" ()
"movh $rn,$uimm16"
(+ MAJ_12 rn (f-rm 2) (f-sub4 1) uimm16)
(set rn (sll uimm16 16))
())
; Arithmetic instructions.
(dnci add3 "add three registers" ()
"add3 $rl,$rn,$rm"
(+ MAJ_9 rn rm rl)
(set rl (add rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci add "add" ()
"add $rn,$simm6"
(+ MAJ_6 rn simm6 (f-sub2 0))
(set rn (add rn (ext SI simm6)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci add3i "add two registers and immediate" ()
"add3 $rn,$spr,$uimm7a4"
(+ MAJ_4 rn (f-8 0) uimm7a4 (f-sub2 0))
(set rn (add sp (zext SI uimm7a4)))
((mep (unit u-use-gpr (in usereg sp))
(unit u-exec))))
(dnci advck3 "add overflow check" ((STALL ADVCK))
"advck3 \\$0,$rn,$rm"
(+ MAJ_0 rn rm (f-sub4 7))
(if (add-oflag rn rm 0)
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sub "subtract" ()
"sub $rn,$rm"
(+ MAJ_0 rn rm (f-sub4 4))
(set rn (sub rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm)))))
(dnci sbvck3 "subtraction overflow check" ((STALL ADVCK))
"sbvck3 \\$0,$rn,$rm"
(+ MAJ_0 rn rm (f-sub4 5))
(if (sub-oflag rn rm 0)
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci neg "negate" ()
"neg $rn,$rm"
(+ MAJ_0 rn rm (f-sub4 1))
(set rn (neg rm))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci slt3 "set if less than" ()
"slt3 \\$0,$rn,$rm"
(+ MAJ_0 rn rm (f-sub4 2))
(if (lt rn rm)
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sltu3 "set less than unsigned" ()
"sltu3 \\$0,$rn,$rm"
(+ MAJ_0 rn rm (f-sub4 3))
(if (ltu rn rm)
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci slt3i "set if less than immediate" ()
"slt3 \\$0,$rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 1))
(if (lt rn (zext SI uimm5))
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci sltu3i "set if less than unsigned immediate" ()
"sltu3 \\$0,$rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 5))
(if (ltu rn (zext SI uimm5))
(set r0 1)
(set r0 0))
())
(dnci sl1ad3 "shift left one and add" ((STALL INT2))
"sl1ad3 \\$0,$rn,$rm"
(+ MAJ_2 rn rm (f-sub4 6))
(set r0 (add (sll rn 1) rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sl2ad3 "shift left two and add" ((STALL INT2))
"sl2ad3 \\$0,$rn,$rm"
(+ MAJ_2 rn rm (f-sub4 7))
(set r0 (add (sll rn 2) rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci add3x "three operand add (extended)" ()
"add3 $rn,$rm,$simm16"
(+ MAJ_12 rn rm (f-sub4 0) simm16)
(set rn (add rm (ext SI simm16)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci slt3x "set if less than (extended)" ()
"slt3 $rn,$rm,$simm16"
(+ MAJ_12 rn rm (f-sub4 2) simm16)
(if (lt rm (ext SI simm16))
(set rn 1)
(set rn 0))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sltu3x "set if less than unsigned (extended)" ()
"sltu3 $rn,$rm,$uimm16"
(+ MAJ_12 rn rm (f-sub4 3) uimm16)
(if (ltu rm (zext SI uimm16))
(set rn 1)
(set rn 0))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Logical instructions.
(dnci or "bitwise or" ()
"or $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 0))
(set rn (or rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci and "bitwise and" ()
"and $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 1))
(set rn (and rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci xor "bitwise exclusive or" ()
"xor $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 2))
(set rn (xor rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci nor "bitwise negated or" ()
"nor $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 3))
(set rn (inv (or rn rm)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci or3 "or three operand" ()
"or3 $rn,$rm,$uimm16"
(+ MAJ_12 rn rm (f-sub4 4) uimm16)
(set rn (or rm (zext SI uimm16)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci and3 "and three operand" ()
"and3 $rn,$rm,$uimm16"
(+ MAJ_12 rn rm (f-sub4 5) uimm16)
(set rn (and rm (zext SI uimm16)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci xor3 "exclusive or three operand" ()
"xor3 $rn,$rm,$uimm16"
(+ MAJ_12 rn rm (f-sub4 6) uimm16)
(set rn (xor rm (zext SI uimm16)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Shift instructions.
(dnci sra "shift right arithmetic" ((STALL INT2))
"sra $rn,$rm"
(+ MAJ_2 rn rm (f-sub4 13))
(set rn (sra rn (and rm #x1f)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci srl "shift right logical" ((STALL INT2))
"srl $rn,$rm"
(+ MAJ_2 rn rm (f-sub4 12))
(set rn (srl rn (and rm #x1f)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sll "shift left logical" ((STALL INT2))
"sll $rn,$rm"
(+ MAJ_2 rn rm (f-sub4 14))
(set rn (sll rn (and rm #x1f)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci srai "shift right arithmetic (immediate)" ((STALL SHIFTI))
"sra $rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 3))
(set rn (sra rn uimm5))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci srli "shift right logical (immediate)" ((STALL SHIFTI))
"srl $rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 2))
(set rn (srl rn uimm5))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci slli "shift left logical (immediate)" ((STALL SHIFTI))
"sll $rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 6))
(set rn (sll rn uimm5))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci sll3 "three-register shift left logical" ((STALL INT2))
"sll3 \\$0,$rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 7))
(set r0 (sll rn uimm5))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci fsft "field shift" ((STALL FSFT) VOLATILE)
"fsft $rn,$rm"
(+ MAJ_2 rn rm (f-sub4 15))
(sequence ((DI temp) (QI shamt))
(set shamt (and sar #x3f))
(set temp (sll (or (sll (zext DI rn) 32) (zext DI rm)) shamt))
(set rn (subword SI (srl temp 32) 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Branch/jump instructions.
(dnci bra "branch" (RELAXABLE)
"bra $pcrel12a2"
(+ MAJ_11 pcrel12a2 (f-15 0))
(set-vliw-alignment-modified pc pcrel12a2)
((mep (unit u-branch)
(unit u-exec))))
(dnci beqz "branch if equal zero" (RELAXABLE)
"beqz $rn,$pcrel8a2"
(+ MAJ_10 rn pcrel8a2 (f-15 0))
(if (eq rn 0)
(set-vliw-alignment-modified pc pcrel8a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci bnez "branch if not equal zero" (RELAXABLE)
"bnez $rn,$pcrel8a2"
(+ MAJ_10 rn pcrel8a2 (f-15 1))
(if (ne rn 0)
(set-vliw-alignment-modified pc pcrel8a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci beqi "branch equal immediate" (RELAXABLE)
"beqi $rn,$uimm4,$pcrel17a2"
(+ MAJ_14 rn uimm4 (f-sub4 0) pcrel17a2)
(if (eq rn (zext SI uimm4))
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci bnei "branch not equal immediate" (RELAXABLE)
"bnei $rn,$uimm4,$pcrel17a2"
(+ MAJ_14 rn uimm4 (f-sub4 4) pcrel17a2)
(if (ne rn (zext SI uimm4))
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci blti "branch less than immediate" (RELAXABLE)
"blti $rn,$uimm4,$pcrel17a2"
(+ MAJ_14 rn uimm4 (f-sub4 12) pcrel17a2)
(if (lt rn (zext SI uimm4))
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci bgei "branch greater than immediate" (RELAXABLE)
"bgei $rn,$uimm4,$pcrel17a2"
(+ MAJ_14 rn uimm4 (f-sub4 8) pcrel17a2)
(if (ge rn (zext SI uimm4))
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci beq "branch equal" ()
"beq $rn,$rm,$pcrel17a2"
(+ MAJ_14 rn rm (f-sub4 1) pcrel17a2)
(if (eq rn rm)
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci bne "branch not equal" ()
"bne $rn,$rm,$pcrel17a2"
(+ MAJ_14 rn rm (f-sub4 5) pcrel17a2)
(if (ne rn rm)
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci bsr12 "branch to subroutine (12 bit displacement)" (RELAXABLE)
"bsr $pcrel12a2"
(+ MAJ_11 pcrel12a2 (f-15 1))
(sequence ()
(cg-profile pc pcrel12a2)
(set-vliw-modified-pcrel-offset lp 2 4 8)
(set-vliw-alignment-modified pc pcrel12a2))
((mep (unit u-exec)
(unit u-branch))))
(dnci bsr24 "branch to subroutine (24 bit displacement)" ()
"bsr $pcrel24a2"
(+ MAJ_13 (f-4 1) (f-sub4 9) pcrel24a2)
(sequence ()
(cg-profile pc pcrel24a2)
(set-vliw-modified-pcrel-offset lp 4 4 8)
(set-vliw-alignment-modified pc pcrel24a2))
((mep (unit u-exec)
(unit u-branch))))
(dnci jmp "jump" ()
"jmp $rm"
(+ MAJ_1 (f-rn 0) rm (f-sub4 14))
(sequence ()
(if (eq (get-psw.om) 0)
;; core mode
(if (get-rm.lsb)
(sequence ()
(set-psw.om 1) ;; enter VLIW mode
(set-vliw-aliignment-modified-by-option pc rm))
(set pc (and rm (inv 1))))
;; VLIW mode
(if (get-rm.lsb)
(sequence ()
(set-psw.om 0) ;; enter core mode
(set pc (and rm (inv 1))))
(set-vliw-aliignment-modified-by-option pc rm)))
(cg-profile-jump pc rm))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci jmp24 "jump (24 bit target)" ()
"jmp $pcabs24a2"
(+ MAJ_13 (f-4 1) (f-sub4 8) pcabs24a2)
(sequence ()
(set-vliw-alignment-modified pc (or (and pc #xf0000000) pcabs24a2))
(cg-profile-jump pc pcabs24a2))
((mep (unit u-exec)
(unit u-branch))))
(dnci jsr "jump to subroutine" ()
"jsr $rm"
(+ MAJ_1 (f-rn 0) rm (f-sub4 15))
(sequence ()
(cg-profile pc rm)
(set-vliw-modified-pcrel-offset lp 2 4 8)
(set-vliw-alignment-modified pc rm))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci ret "return from subroutine" ((STALL RET))
"ret"
(+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 2))
(sequence ()
(if (eq (get-psw.om) 0)
;; core mode
(if (get-lp.ltom) ;; link-pointer "toggle mode" bit
(sequence ()
(set-psw.om 1) ;; enter VLIW mode
(set-vliw-aliignment-modified-by-option pc lp))
(set pc (and lp (inv 1))))
;; VLIW mode
(if (get-lp.ltom) ;; link-pointer "toggle mode" bit
(sequence ()
(set-psw.om 0) ;; enter VLIW mode
(set pc (and lp (inv 1))))
(set-vliw-aliignment-modified-by-option pc lp)))
(c-call VOID "notify_ret" pc))
((mep (unit u-exec)
(unit u-branch))))
; Repeat instructions.
(dnci repeat "repeat specified repeat block" ()
"repeat $rn,$pcrel17a2"
(+ MAJ_14 rn (f-rm 0) (f-sub4 9) pcrel17a2)
(sequence ()
(set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
(set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
(set (reg h-csr 6) rn))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci erepeat "endless repeat" ()
"erepeat $pcrel17a2"
(+ MAJ_14 (f-rn 0) (f-rm 1) (f-sub4 9) pcrel17a2)
(sequence ()
(set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
(set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
(set-rpe.elr 1)
; rpc may be undefined for erepeat
; use 1 to trigger repeat logic in the sim's main loop
(set (reg h-csr 6) 1))
())
; Control instructions.
;; special store variants
(dnci stc_lp "store to control register lp" ((STALL STC))
"stc $rn,\\$lp"
(+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
(set lp rn)
((mep (unit u-use-gpr (in usereg rn))
(unit u-store-ctrl-reg (out storereg lp))
(unit u-exec))))
(dnci stc_hi "store to control register hi" ((STALL STC))
"stc $rn,\\$hi"
(+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
(set hi rn)
((mep (unit u-use-gpr (in usereg rn))
(unit u-store-ctrl-reg (out storereg hi))
(unit u-exec))))
(dnci stc_lo "store to control register lo" ((STALL STC))
"stc $rn,\\$lo"
(+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
(set lo rn)
((mep (unit u-use-gpr (in usereg rn))
(unit u-store-ctrl-reg (out storereg lo))
(unit u-exec))))
;; general store
(dnci stc "store to control register" (VOLATILE (STALL STC))
"stc $rn,$csrn"
(+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 0))
(set csrn rn)
((mep (unit u-use-gpr (in usereg rn))
(unit u-store-ctrl-reg (out storereg csrn))
(unit u-exec))))
;; special load variants
(dnci ldc_lp "load from control register lp" ((STALL LDC))
"ldc $rn,\\$lp"
(+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
(set rn lp)
((mep (unit u-use-ctrl-reg (in usereg lp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn)))))
(dnci ldc_hi "load from control register hi" ((STALL LDC))
"ldc $rn,\\$hi"
(+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
(set rn hi)
((mep (unit u-use-ctrl-reg (in usereg hi))
(unit u-exec)
(unit u-load-gpr (out loadreg rn)))))
(dnci ldc_lo "load from control register lo" ((STALL LDC))
"ldc $rn,\\$lo"
(+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
(set rn lo)
((mep (unit u-use-ctrl-reg (in usereg lo))
(unit u-exec)
(unit u-load-gpr (out loadreg rn)))))
;; general load
(dnci ldc "load from control register" (VOLATILE (STALL LDC) (LATENCY 2))
"ldc $rn,$csrn"
(+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 1))
(if (eq (ifield f-csrn) 0)
;; loading from the pc
(set-vliw-modified-pcrel-offset rn 2 4 8)
;; loading from something else
(set rn csrn))
((mep (unit u-use-ctrl-reg (in usereg csrn))
(unit u-exec)
(unit u-load-gpr (out loadreg rn)))))
(dnci di "disable interrupt" (VOLATILE)
"di"
(+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 0))
; clear psw.iec
(set psw (sll (srl psw 1) 1))
())
(dnci ei "enable interrupt" (VOLATILE)
"ei"
(+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 0))
; set psw.iec
(set psw (or psw 1))
())
(dnci reti "return from interrupt" ((STALL RET))
"reti"
(+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 2))
(if (eq (get-psw.om) 0)
;; core operation mode
(if (get-psw.nmi)
;; return from NMI
(if (get-npc.ntom)
;; return in VLIW operation mode
(sequence ()
(set-psw.om 1)
(set-vliw-aliignment-modified-by-option pc npc)
(set-psw.nmi 0))
;; return in core mode
(sequence ()
(set pc (and npc (inv 1)))
(set-psw.nmi 0)))
;; return from non-NMI
(if (get-epc.etom)
;; return in VLIW mode
(sequence ()
(set-psw.om 1)
(set-vliw-aliignment-modified-by-option pc epc)
(set-psw.umc (get-psw.ump))
(set-psw.iec (get-psw.iep)))
;; return in core mode
(sequence ()
(set pc (and epc (inv 1)))
(set-psw.umc (get-psw.ump))
(set-psw.iec (get-psw.iep)))))
;; VLIW operation mode
;; xxx undefined
(nop))
((mep (unit u-exec)
(unit u-branch))))
(dnci halt "halt pipeline" (VOLATILE)
"halt"
(+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 2))
; set psw.halt
(set (raw-reg h-csr 16) (or psw (sll 1 11)))
())
(dnci sleep "sleep pipeline" (VOLATILE)
"sleep"
(+ MAJ_7 (f-rn 0) (f-rm 6) (f-sub4 2))
(c-call VOID "do_sleep")
())
(dnci swi "software interrupt" (MAY_TRAP VOLATILE)
"swi $uimm2"
(+ MAJ_7 (f-rn 0) (f-8 0) (f-9 0) uimm2 (f-sub4 6))
(cond
((eq uimm2 0) (set exc (or exc (sll 1 4))))
((eq uimm2 1) (set exc (or exc (sll 1 5))))
((eq uimm2 2) (set exc (or exc (sll 1 6))))
((eq uimm2 3) (set exc (or exc (sll 1 7)))))
())
(dnci break "break exception" (MAY_TRAP VOLATILE)
"break"
(+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 2))
(set pc (c-call USI "break_exception" pc))
((mep (unit u-exec)
(unit u-branch))))
(dnci syncm "synchronise with memory" (VOLATILE)
"syncm"
(+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 1))
(unimp "syncm")
())
(dnci stcb "store in control bus space" (VOLATILE (STALL STCB))
"stcb $rn,$uimm16"
(+ MAJ_15 rn (f-rm 0) (f-sub4 4) uimm16)
(c-call VOID "do_stcb" rn uimm16)
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-stcb))))
(dnci ldcb "load from control bus space" (VOLATILE (STALL LDCB) (LATENCY 3))
"ldcb $rn,$uimm16"
(+ MAJ_15 rn (f-rm 1) (f-sub4 4) uimm16)
(set rn (c-call SI "do_ldcb" uimm16))
((mep (unit u-ldcb)
(unit u-exec)
(unit u-ldcb-gpr (out loadreg rn)))))
; Bit manipulation instructions.
; The following instructions become the reserved instruction when the
; bit manipulation option is off.
(dnci bsetm "set bit in memory" (OPTIONAL_BIT_INSN)
"bsetm ($rma),$uimm3"
(+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 0))
(sequence ()
(c-call "check_option_bit" pc)
(set (mem UQI rma) (or (mem UQI rma) (sll 1 uimm3))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci bclrm "clear bit in memory" (OPTIONAL_BIT_INSN)
"bclrm ($rma),$uimm3"
(+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 1))
(sequence ()
(c-call "check_option_bit" pc)
(set (mem UQI rma) (and (mem UQI rma) (inv (sll 1 uimm3)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci bnotm "toggle bit in memory" (OPTIONAL_BIT_INSN)
"bnotm ($rma),$uimm3"
(+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 2))
(sequence ()
(c-call "check_option_bit" pc)
(set (mem UQI rma) (xor (mem UQI rma) (sll 1 uimm3))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci btstm "test bit in memory" (OPTIONAL_BIT_INSN)
"btstm \\$0,($rma),$uimm3"
(+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 3))
(sequence ()
(c-call "check_option_bit" pc)
(set r0 (zext SI (and UQI (mem UQI rma) (sll 1 uimm3)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci tas "test and set" (OPTIONAL_BIT_INSN)
"tas $rn,($rma)"
(+ MAJ_2 rn rma (f-sub4 4))
(sequence ((SI result))
(c-call "check_option_bit" pc)
(set result (zext SI (mem UQI rma)))
(set (mem UQI rma) 1)
(set rn result))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
; Data cache instruction.
(dnci cache "cache operations" (VOLATILE)
"cache $cimm4,($rma)"
(+ MAJ_7 cimm4 rma (f-sub4 4))
(c-call VOID "do_cache" cimm4 rma pc)
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
; Multiply instructions.
; These instructions become the RI when the 32-bit multiply
; instruction option is off.
(dnci mul "multiply" (OPTIONAL_MUL_INSN (STALL MUL))
"mul $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 4))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (mul (ext DI rn) (ext DI rm)))
(set hi (subword SI result 0))
(set lo (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply))))
(dnci mulu "multiply unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
"mulu $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 5))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (mul (zext UDI rn) (zext UDI rm)))
(set hi (subword SI result 0))
(set lo (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply))))
(dnci mulr "multiply, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
"mulr $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 6))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (mul (ext DI rn) (ext DI rm)))
(set hi (subword SI result 0))
(set lo (subword SI result 1))
(set rn (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply)
(unit u-mul-gpr (out resultreg rn)))))
(dnci mulru "multiply unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
"mulru $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 7))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (mul (zext UDI rn) (zext UDI rm)))
(set hi (subword SI result 0))
(set lo (subword SI result 1))
(set rn (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply)
(unit u-mul-gpr (out resultreg rn)))))
(dnci madd "multiply accumulate" (OPTIONAL_MUL_INSN (STALL MUL))
"madd $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (or (sll (zext DI hi) 32) (zext DI lo)))
(set result (add result (mul (ext DI rn) (ext DI rm))))
(set hi (subword SI result 0))
(set lo (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply))))
(dnci maddu "multiply accumulate unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
"maddu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (or (sll (zext DI hi) 32) (zext DI lo)))
(set result (add result (mul (zext UDI rn) (zext UDI rm))))
(set hi (subword SI result 0))
(set lo (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply))))
(dnci maddr "multiply accumulate, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
"maddr $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3006))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (or (sll (zext DI hi) 32) (zext DI lo)))
(set result (add result (mul (ext DI rn) (ext DI rm))))
(set hi (subword SI result 0))
(set lo (subword SI result 1))
(set rn (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply)
(unit u-mul-gpr (out resultreg rn)))))
(dnci maddru "multiple accumulate unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
"maddru $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3007))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (or (sll (zext DI hi) 32) (zext DI lo)))
(set result (add result (mul (zext UDI rn) (zext UDI rm))))
(set hi (subword SI result 0))
(set lo (subword SI result 1))
(set rn (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply)
(unit u-mul-gpr (out resultreg rn)))))
; Divide instructions.
; These instructions become the RI when the 32-bit divide instruction
; option is off.
(dnci div "divide" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
"div $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 8))
(sequence ()
(c-call "check_option_div" pc)
(if (eq rm 0)
(set pc (c-call USI "zdiv_exception" pc))
; Special case described on p. 76.
(if (and (eq rn #x80000000)
(eq rm #xffffffff))
(sequence ()
(set lo #x80000000)
(set hi 0))
(sequence ()
(set lo (div rn rm))
(set hi (mod rn rm))))))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-divide)
(unit u-branch))))
(dnci divu "divide unsigned" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
"divu $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 9))
(sequence ()
(c-call "check_option_div" pc)
(if (eq rm 0)
(set pc (c-call USI "zdiv_exception" pc))
(sequence ()
(set lo (udiv rn rm))
(set hi (umod rn rm)))))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-divide)
(unit u-branch))))
; Debug functions.
; These instructions become the RI when the debug function option is
; off.
(dnci dret "return from debug exception" (OPTIONAL_DEBUG_INSN)
"dret"
(+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 3))
(sequence ()
(c-call "check_option_debug" pc)
; set DBG.DM.
(set dbg (and dbg (inv (sll SI 1 15))))
(set pc depc))
((mep (unit u-exec)
(unit u-branch))))
(dnci dbreak "generate debug exception" (OPTIONAL_DEBUG_INSN MAY_TRAP VOLATILE)
"dbreak"
(+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 3))
(sequence ()
(c-call "check_option_debug" pc)
; set DBG.DPB.
(set dbg (or dbg 1)))
())
; Leading zero instruction.
(dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2))
"ldz $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 0))
(sequence ()
(c-call "check_option_ldz" pc)
(set rn (c-call SI "do_ldz" rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Absolute difference instruction.
(dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2))
"abs $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 3))
(sequence ()
(c-call "check_option_abs" pc)
(set rn (abs (sub rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
; Average instruction.
(dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2))
"ave $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 2))
(sequence ()
(c-call "check_option_ave" pc)
(set rn (sra (add (add rn rm) 1) 1)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
; MIN/MAX instructions.
(dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2))
"min $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 4))
(sequence ()
(c-call "check_option_minmax" pc)
(if (gt rn rm)
(set rn rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci max "maximum" (OPTIONAL_MINMAX_INSN (STALL INT2))
"max $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 5))
(sequence ()
(c-call "check_option_minmax" pc)
(if (lt rn rm)
(set rn rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci minu "minimum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
"minu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 6))
(sequence ()
(c-call "check_option_minmax" pc)
(if (gtu rn rm)
(set rn rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci maxu "maximum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
"maxu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 7))
(sequence ()
(c-call "check_option_minmax" pc)
(if (ltu rn rm)
(set rn rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
; Clipping instruction.
(dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2))
"clip $rn,$cimm5"
(+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 0))
(sequence ((SI min) (SI max))
(c-call "check_option_clip" pc)
(set max (sub (sll 1 (sub cimm5 1)) 1))
(set min (neg (sll 1 (sub cimm5 1))))
(cond
((eq cimm5 0) (set rn 0))
((gt rn max) (set rn max))
((lt rn min) (set rn min))))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci clipu "clip unsigned" (OPTIONAL_CLIP_INSN (STALL INT2))
"clipu $rn,$cimm5"
(+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 1))
(sequence ((SI max))
(c-call "check_option_clip" pc)
(set max (sub (sll 1 cimm5) 1))
(cond
((eq cimm5 0) (set rn 0))
((gt rn max) (set rn max))
((lt rn 0) (set rn 0))))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
; Saturation instructions.
(dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2))
"sadd $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 8))
(sequence ()
(c-call "check_option_sat" pc)
(if (add-oflag rn rm 0)
(if (nflag rn)
; underflow
(set rn (neg (sll 1 31)))
; overflow
(set rn (sub (sll 1 31) 1)))
(set rn (add rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci ssub "saturating subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
"ssub $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 10))
(sequence ()
(c-call "check_option_sat" pc)
(if (sub-oflag rn rm 0)
(if (nflag rn)
; underflow
(set rn (neg (sll 1 31)))
; overflow
(set rn (sub (sll 1 31) 1)))
(set rn (sub rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci saddu "saturating unsigned addition" (OPTIONAL_SAT_INSN (STALL INT2))
"saddu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 9))
(sequence ()
(c-call "check_option_sat" pc)
(if (add-cflag rn rm 0)
(set rn (inv 0))
(set rn (add rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci ssubu "saturating unsigned subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
"ssubu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 11))
(sequence ()
(c-call "check_option_sat" pc)
(if (sub-cflag rn rm 0)
(set rn 0)
(set rn (sub rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
; UCI and DSP options are defined in an external file.
; See `mep-sample-ucidsp.cpu' for a sample.
; Coprocessor instructions.
(dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
"swcp $crn,($rma)"
(+ MAJ_3 crn rma (f-sub4 8))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcp "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
"lwcp $crn,($rma)"
(+ MAJ_3 crn rma (f-sub4 9))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcp "smcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
"smcp $crn64,($rma)"
(+ MAJ_3 crn64 rma (f-sub4 10))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcp" rma crn64 pc))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcp "lmcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
"lmcp $crn64,($rma)"
(+ MAJ_3 crn64 rma (f-sub4 11))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpi "swcp (post-increment)" (OPTIONAL_CP_INSN (STALL STORE))
"swcpi $crn,($rma+)"
(+ MAJ_3 crn rma (f-sub4 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
(set rma (add rma 4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpi "lwcp (post-increment)" (OPTIONAL_CP_INSN (STALL LOAD))
"lwcpi $crn,($rma+)"
(+ MAJ_3 crn rma (f-sub4 1))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
(set rma (add rma 4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpi "smcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
"smcpi $crn64,($rma+)"
(+ MAJ_3 crn64 rma (f-sub4 2))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcpi" (index-of rma) crn64 pc)
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpi "lmcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
"lmcpi $crn64,($rma+)"
(+ MAJ_3 crn64 rma (f-sub4 3))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcpi" (index-of rma) pc))
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcp16 "swcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL STORE))
"swcp $crn,$sdisp16($rma)"
(+ MAJ_15 crn rma (f-sub4 12) sdisp16)
(sequence ()
(c-call "check_option_cp" pc)
(set (mem SI (and (add rma sdisp16) (inv SI 3))) crn))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcp16 "lwcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL LOAD))
"lwcp $crn,$sdisp16($rma)"
(+ MAJ_15 crn rma (f-sub4 13) sdisp16)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and (add rma sdisp16) (inv SI 3)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcp16 "smcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
"smcp $crn64,$sdisp16($rma)"
(+ MAJ_15 crn64 rma (f-sub4 14) sdisp16)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call "do_smcp16" rma sdisp16 crn64 pc))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcp16 "lmcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
"lmcp $crn64,$sdisp16($rma)"
(+ MAJ_15 crn64 rma (f-sub4 15) sdisp16)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp16" rma sdisp16 pc)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
"sbcpa $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
(set rma (add rma (ext SI cdisp10))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
"lbcpa $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
(set rma (add rma (ext SI cdisp10))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
"shcpa $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
(set rma (add rma (ext SI cdisp10a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
"lhcpa $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
(set rma (add rma (ext SI cdisp10a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
"swcpa $crn,($rma+),$cdisp10a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
(set rma (add rma (ext SI cdisp10a4))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
"lwcpa $crn,($rma+),$cdisp10a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
(set rma (add rma (ext SI cdisp10a4))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
"smcpa $crn64,($rma+),$cdisp10a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc)
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
"lmcpa $crn64,($rma+),$cdisp10a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc))
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN)
"sbcpm0 $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
(set rma (mod0 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN)
"lbcpm0 $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
(set rma (mod0 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN)
"shcpm0 $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
(set rma (mod0 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN)
"lhcpm0 $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
(set rma (mod0 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN)
"swcpm0 $crn,($rma+),$cdisp10a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
(set rma (mod0 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN)
"lwcpm0 $crn,($rma+),$cdisp10a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
(set rma (mod0 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
"smcpm0 $crn64,($rma+),$cdisp10a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcp" rma crn64 pc)
(set rma (mod0 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
"lmcpm0 $crn64,($rma+),$cdisp10a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc))
(set rma (mod0 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN)
"sbcpm1 $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
(set rma (mod1 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN)
"lbcpm1 $crn,($rma+),$cdisp10"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
(set rma (mod1 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN)
"shcpm1 $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
(set rma (mod1 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN)
"lhcpm1 $crn,($rma+),$cdisp10a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
(set rma (mod1 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN)
"swcpm1 $crn,($rma+),$cdisp10a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
(set rma (mod1 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN)
"lwcpm1 $crn,($rma+),$cdisp10a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem SI (and rma (inv SI 3)))))
(set rma (mod1 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
"smcpm1 $crn64,($rma+),$cdisp10a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call "do_smcp" rma crn64 pc)
(c-call VOID "check_write_to_text" rma)
(set rma (mod1 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
"lmcpm1 $crn64,($rma+),$cdisp10a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc))
(set rma (mod1 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnop cp_flag "branch condition register" (all-mep-isas) h-ccr 1)
(dnci bcpeq "branch coprocessor equal" (OPTIONAL_CP_INSN RELAXABLE)
"bcpeq $cccc,$pcrel17a2"
(+ MAJ_13 (f-rn 8) cccc (f-sub4 4) pcrel17a2)
(sequence ()
(c-call "check_option_cp" pc)
(if (eq (xor cccc cp_flag) 0)
(set-vliw-alignment-modified pc pcrel17a2)))
())
(dnci bcpne "branch coprocessor not equal" (OPTIONAL_CP_INSN RELAXABLE)
"bcpne $cccc,$pcrel17a2"
(+ MAJ_13 (f-rn 8) cccc (f-sub4 5) pcrel17a2)
(sequence ()
(c-call "check_option_cp" pc)
(if (ne (xor cccc cp_flag) 0)
(set-vliw-alignment-modified pc pcrel17a2)))
())
(dnci bcpat "branch coprocessor and true" (OPTIONAL_CP_INSN RELAXABLE)
"bcpat $cccc,$pcrel17a2"
(+ MAJ_13 (f-rn 8) cccc (f-sub4 6) pcrel17a2)
(sequence ()
(c-call "check_option_cp" pc)
(if (ne (and cccc cp_flag) 0)
(set-vliw-alignment-modified pc pcrel17a2)))
())
(dnci bcpaf "branch coprocessor and false" (OPTIONAL_CP_INSN RELAXABLE)
"bcpaf $cccc,$pcrel17a2"
(+ MAJ_13 (f-rn 8) cccc (f-sub4 7) pcrel17a2)
(sequence ()
(c-call "check_option_cp" pc)
(if (eq (and cccc cp_flag) 0)
(set-vliw-alignment-modified pc pcrel17a2)))
())
(dnci synccp "synchronise with coprocessor" (OPTIONAL_CP_INSN)
"synccp"
(+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 1))
(sequence ()
(c-call "check_option_cp" pc)
(unimp "synccp"))
())
(dnci jsrv "jump to vliw subroutine " (OPTIONAL_CP_INSN)
"jsrv $rm"
(+ MAJ_1 (f-rn 8) rm (f-sub4 15))
(sequence ()
(cg-profile pc rm)
(c-call "check_option_cp" pc)
(core-vliw-switch
;; in core operating mode
(sequence ()
(set lp (or (add pc 2) 1))
(set-vliw-aliignment-modified-by-option pc rm)
(set-psw.om 1)) ;; to VLIW operation mode
;; in VLIW32 operating mode
(sequence ()
(set lp (or (add pc 4) 1))
(set pc (and rm (inv 1)))
(set-psw.om 0)) ;; to core operation mode
;; in VLIW64 operating mode
(sequence ()
(set lp (or (add pc 8) 1))
(set pc (and rm (inv 1)))
(set-psw.om 0)))) ;; to core operation mode
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci bsrv "branch to vliw subroutine" (OPTIONAL_CP_INSN)
"bsrv $pcrel24a2"
(+ MAJ_13 (f-4 1) (f-sub4 11) pcrel24a2)
(sequence ()
(cg-profile pc pcrel24a2)
(c-call "check_option_cp" pc)
(core-vliw-switch
;; in core operating mode
(sequence ()
(set lp (or (add pc 4) 1))
(set-vliw-aliignment-modified-by-option pc pcrel24a2)
(set-psw.om 1)) ;; to VLIW operation mode
;; in VLIW32 operating mode
(sequence ()
(set lp (or (add pc 4) 1))
(set pc (and pcrel24a2 (inv 1)))
(set-psw.om 0)) ;; to core operation mode
;; in VLIW64 operating mode
(sequence ()
(set lp (or (add pc 8) 1))
(set pc (and pcrel24a2 (inv 1)))
(set-psw.om 0)))) ;; to core operation mode
((mep (unit u-exec)
(unit u-branch))))
; An instruction for test instrumentation.
; Using a reserved opcode.
(dnci sim-syscall "simulator system call" ()
"--syscall--"
(+ MAJ_7 (f-4 1) callnum (f-8 0) (f-9 0) (f-10 0) (f-sub4 0))
(c-call "do_syscall" pc callnum)
())
(define-pmacro (dnri n major minor)
(dnci (.sym ri- n) "reserved instruction" ()
"--reserved--"
(+ major rn rm (f-sub4 minor))
(set pc (c-call USI "ri_exception" pc))
((mep (unit u-exec)
(unit u-branch)))))
(dnri 0 MAJ_0 6)
(dnri 1 MAJ_1 10)
(dnri 2 MAJ_1 11)
(dnri 3 MAJ_2 5)
(dnri 4 MAJ_2 8)
(dnri 5 MAJ_2 9)
(dnri 6 MAJ_2 10)
(dnri 7 MAJ_2 11)
(dnri 8 MAJ_3 4)
(dnri 9 MAJ_3 5)
(dnri 10 MAJ_3 6)
(dnri 11 MAJ_3 7)
(dnri 12 MAJ_3 12)
(dnri 13 MAJ_3 13)
(dnri 14 MAJ_3 14)
(dnri 15 MAJ_3 15)
(dnri 17 MAJ_7 7)
(dnri 20 MAJ_7 14)
(dnri 21 MAJ_7 15)
(dnri 22 MAJ_12 7)
(dnri 23 MAJ_14 13)
;(dnri 24 MAJ_15 3)
(dnri 26 MAJ_15 8)
; begin core-specific reserved insns
; end core-specific reserved insns
; Macro instructions.
(dnmi nop "nop"
()
"nop"
(emit mov (rn 0) (rm 0)))
; Emit the 16 bit form of these 32 bit insns when the displacement is zero.
;
(dncmi sb16-0 "store byte (explicit 16 bit displacement of zero)" (NO-DIS)
"sb $rnc,$zero($rma)"
(emit sb rnc rma))
(dncmi sh16-0 "store half (explicit 16 bit displacement of zero)" (NO-DIS)
"sh $rns,$zero($rma)"
(emit sh rns rma))
(dncmi sw16-0 "store word (explicit 16 bit displacement of zero)" (NO-DIS)
"sw $rnl,$zero($rma)"
(emit sw rnl rma))
(dncmi lb16-0 "load byte (explicit 16 bit displacement of zero)" (NO-DIS)
"lb $rnc,$zero($rma)"
(emit lb rnc rma))
(dncmi lh16-0 "load half (explicit 16 bit displacement of zero)" (NO-DIS)
"lh $rns,$zero($rma)"
(emit lh rns rma))
(dncmi lw16-0 "load word (explicit 16 bit displacement of zero)" (NO-DIS)
"lw $rnl,$zero($rma)"
(emit lw rnl rma))
(dncmi lbu16-0 "load unsigned byte (explicit 16 bit displacement of zero)" (NO-DIS)
"lbu $rnuc,$zero($rma)"
(emit lbu rnuc rma))
(dncmi lhu16-0 "load unsigned half (explicit 16 bit displacement of zero)" (NO-DIS)
"lhu $rnus,$zero($rma)"
(emit lhu rnus rma))
(dncmi swcp16-0 "swcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
"swcp $crn,$zero($rma)"
(emit swcp crn rma))
(dncmi lwcp16-0 "lwcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
"lwcp $crn,$zero($rma)"
(emit lwcp crn rma))
(dncmi smcp16-0 "smcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
"smcp $crn64,$zero($rma)"
(emit smcp crn64 rma))
(dncmi lmcp16-0 "lmcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
"lmcp $crn64,$zero($rma)"
(emit lmcp crn64 rma))
gcc/config/mep/mep-default.cpu deleted 100644 → 0
; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
; Copyright (C) 2001-2016 Free Software Foundation, Inc.
; Contributed by Red Hat, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
; This file serves as a wrapper to bring in the core description plus
; sample implementations of the UCI and DSP instructions.
(include "mep-core.cpu")
(include "mep-ext-cop.cpu")
gcc/config/mep/mep-ext-cop.cpu deleted 100644 → 0
; Toshiba MeP IVC2 Coprocessor description. -*- scheme -*-
; Copyright (C) 2003-2016 Free Software Foundation, Inc.
; Contributed by Red Hat, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
;; begin-user-isa-includes
(include "mep-ivc2.cpu")
;; end-user-isa-includes
gcc/config/mep/mep-intrin.h deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/mep/mep-ivc2.cpu deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/mep/mep-pragma.c deleted 100644 → 0
/* Definitions of Toshiba Media Processor
Copyright (C) 2001-2016 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "target.h"
#include "function.h"
#include "tree.h"
#include "diagnostic-core.h"
#include "c-family/c-pragma.h"
#include "output.h" /* for decode_reg_name */
#include "mep-protos.h"
#define MAX_RECOG_OPERANDS 10
#include "reload.h"
enum cw_which { CW_AVAILABLE, CW_CALL_SAVED };
/* This is normally provided by rtl.h but we can't include that file
here. It's safe to copy the definition here because we're only
using it internally; the value isn't passed to functions outside
this file. */
#ifndef INVALID_REGNUM
#define INVALID_REGNUM (~(unsigned int) 0)
#endif
static enum cpp_ttype
mep_pragma_lex (tree *valp)
{
enum cpp_ttype t = pragma_lex (valp);
if (t == CPP_EOF)
t = CPP_PRAGMA_EOL;
return t;
}
static void
mep_pragma_io_volatile (cpp_reader *reader ATTRIBUTE_UNUSED)
{
/* On off. */
tree val;
enum cpp_ttype type;
const char * str;
type = mep_pragma_lex (&val);
if (type == CPP_NAME)
{
str = IDENTIFIER_POINTER (val);
type = mep_pragma_lex (&val);
if (type != CPP_PRAGMA_EOL)
warning (0, "junk at end of #pragma io_volatile");
if (strcmp (str, "on") == 0)
{
target_flags |= MASK_IO_VOLATILE;
return;
}
if (strcmp (str, "off") == 0)
{
target_flags &= ~ MASK_IO_VOLATILE;
return;
}
}
error ("#pragma io_volatile takes only on or off");
}
static unsigned int
parse_cr_reg (const char * str)
{
unsigned int regno;
regno = decode_reg_name (str);
if (regno >= FIRST_PSEUDO_REGISTER)
return INVALID_REGNUM;
/* Verify that the regno is in CR_REGS. */
if (! TEST_HARD_REG_BIT (reg_class_contents[CR_REGS], regno))
return INVALID_REGNUM;
return regno;
}
static bool
parse_cr_set (HARD_REG_SET * set)
{
tree val;
enum cpp_ttype type;
unsigned int last_regno = INVALID_REGNUM;
bool do_range = false;
CLEAR_HARD_REG_SET (*set);
while ((type = mep_pragma_lex (&val)) != CPP_PRAGMA_EOL)
{
if (type == CPP_COMMA)
{
last_regno = INVALID_REGNUM;
do_range = false;
}
else if (type == CPP_ELLIPSIS)
{
if (last_regno == INVALID_REGNUM)
{
error ("invalid coprocessor register range");
return false;
}
do_range = true;
}
else if (type == CPP_NAME || type == CPP_STRING)
{
const char *str;
unsigned int regno, i;
if (TREE_CODE (val) == IDENTIFIER_NODE)
str = IDENTIFIER_POINTER (val);
else if (TREE_CODE (val) == STRING_CST)
str = TREE_STRING_POINTER (val);
else
gcc_unreachable ();
regno = parse_cr_reg (str);
if (regno == INVALID_REGNUM)
{
error ("invalid coprocessor register %qE", val);
return false;
}
if (do_range)
{
if (last_regno > regno)
i = regno, regno = last_regno;
else
i = last_regno;
do_range = false;
}
else
last_regno = i = regno;
while (i <= regno)
{
SET_HARD_REG_BIT (*set, i);
i++;
}
}
else
{
error ("malformed coprocessor register");
return false;
}
}
return true;
}
static void
mep_pragma_coprocessor_which (enum cw_which cw_which)
{
HARD_REG_SET set;
/* Process the balance of the pragma and turn it into a hard reg set. */
if (! parse_cr_set (&set))
return;
/* Process the collected hard reg set. */
switch (cw_which)
{
case CW_AVAILABLE:
{
int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
if (TEST_HARD_REG_BIT (set, i))
fixed_regs[i] = 0;
}
break;
case CW_CALL_SAVED:
{
int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
if (TEST_HARD_REG_BIT (set, i))
fixed_regs[i] = call_used_regs[i] = 0;
}
break;
default:
gcc_unreachable ();
}
/* Fix up register class hierarchy. */
mep_save_register_info ();
mep_reinit_regs ();
if (cfun == 0)
{
init_dummy_function_start ();
init_caller_save ();
expand_dummy_function_end ();
}
else
{
init_caller_save ();
}
}
static void
mep_pragma_coprocessor_width (void)
{
tree val;
enum cpp_ttype type;
HOST_WIDE_INT i;
type = mep_pragma_lex (&val);
switch (type)
{
case CPP_NUMBER:
if (! tree_fits_uhwi_p (val))
break;
i = tree_to_uhwi (val);
/* This pragma no longer has any effect. */
#if 0
if (i == 32)
target_flags &= ~MASK_64BIT_CR_REGS;
else if (i == 64)
target_flags |= MASK_64BIT_CR_REGS;
else
break;
targetm.init_builtins ();
#else
if (i != 32 && i != 64)
break;
#endif
type = mep_pragma_lex (&val);
if (type != CPP_PRAGMA_EOL)
warning (0, "junk at end of #pragma GCC coprocessor width");
return;
default:
break;
}
error ("#pragma GCC coprocessor width takes only 32 or 64");
}
static void
mep_pragma_coprocessor_subclass (void)
{
tree val;
enum cpp_ttype type;
HARD_REG_SET set;
int class_letter;
enum reg_class rclass;
type = mep_pragma_lex (&val);
if (type != CPP_CHAR)
goto syntax_error;
class_letter = tree_to_uhwi (val);
switch (class_letter)
{
case 'A':
rclass = USER0_REGS;
break;
case 'B':
rclass = USER1_REGS;
break;
case 'C':
rclass = USER2_REGS;
break;
case 'D':
rclass = USER3_REGS;
break;
default:
error ("#pragma GCC coprocessor subclass letter must be in [ABCD]");
return;
}
if (reg_class_size[rclass] > 0)
{
error ("#pragma GCC coprocessor subclass '%c' already defined",
class_letter);
return;
}
type = mep_pragma_lex (&val);
if (type != CPP_EQ)
goto syntax_error;
if (! parse_cr_set (&set))
return;
/* Fix up register class hierarchy. */
COPY_HARD_REG_SET (reg_class_contents[rclass], set);
mep_init_regs ();
return;
syntax_error:
error ("malformed #pragma GCC coprocessor subclass");
}
static void
mep_pragma_disinterrupt (cpp_reader *reader ATTRIBUTE_UNUSED)
{
tree val;
enum cpp_ttype type;
int saw_one = 0;
for (;;)
{
type = mep_pragma_lex (&val);
if (type == CPP_COMMA)
continue;
if (type != CPP_NAME)
break;
mep_note_pragma_disinterrupt (IDENTIFIER_POINTER (val));
saw_one = 1;
}
if (!saw_one || type != CPP_PRAGMA_EOL)
{
error ("malformed #pragma disinterrupt");
return;
}
}
static void
mep_pragma_coprocessor (cpp_reader *reader ATTRIBUTE_UNUSED)
{
tree val;
enum cpp_ttype type;
type = mep_pragma_lex (&val);
if (type != CPP_NAME)
{
error ("malformed #pragma GCC coprocessor");
return;
}
if (!TARGET_COP)
error ("coprocessor not enabled");
if (strcmp (IDENTIFIER_POINTER (val), "available") == 0)
mep_pragma_coprocessor_which (CW_AVAILABLE);
else if (strcmp (IDENTIFIER_POINTER (val), "call_saved") == 0)
mep_pragma_coprocessor_which (CW_CALL_SAVED);
else if (strcmp (IDENTIFIER_POINTER (val), "width") == 0)
mep_pragma_coprocessor_width ();
else if (strcmp (IDENTIFIER_POINTER (val), "subclass") == 0)
mep_pragma_coprocessor_subclass ();
else
error ("unknown #pragma GCC coprocessor %E", val);
}
static void
mep_pragma_call (cpp_reader *reader ATTRIBUTE_UNUSED)
{
tree val;
enum cpp_ttype type;
int saw_one = 0;
for (;;)
{
type = mep_pragma_lex (&val);
if (type == CPP_COMMA)
continue;
if (type != CPP_NAME)
break;
mep_note_pragma_call (IDENTIFIER_POINTER (val));
saw_one = 1;
}
if (!saw_one || type != CPP_PRAGMA_EOL)
{
error ("malformed #pragma call");
return;
}
}
void
mep_register_pragmas (void)
{
c_register_pragma ("custom", "io_volatile", mep_pragma_io_volatile);
c_register_pragma ("GCC", "coprocessor", mep_pragma_coprocessor);
c_register_pragma (0, "disinterrupt", mep_pragma_disinterrupt);
c_register_pragma (0, "call", mep_pragma_call);
}
gcc/config/mep/mep-protos.h deleted 100644 → 0
/* Prototypes for exported functions defined in mep.c
Copyright (C) 2001-2016 Free Software Foundation, Inc.
Contributed by Red Hat Inc (dj@redhat.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
extern int mep_regno_reg_class (int);
extern rtx mep_mulr_source (rtx_insn *, rtx, rtx, rtx);
extern bool mep_reuse_lo_p (rtx, rtx, rtx_insn *, bool);
extern bool mep_use_post_modify_p (rtx_insn *, rtx, rtx);
extern bool mep_allow_clip (rtx, rtx, int);
extern bool mep_bit_position_p (rtx, bool);
extern bool mep_split_mov (rtx *, int);
extern bool mep_vliw_mode_match (rtx);
extern bool mep_vliw_jmp_match (rtx);
extern bool mep_multi_slot (rtx_insn *);
extern bool mep_legitimate_address (machine_mode, rtx, int);
extern int mep_legitimize_address (rtx *, rtx, machine_mode);
extern int mep_legitimize_reload_address (rtx *, machine_mode, int, /*enum reload_type*/ int, int);
extern int mep_core_address_length (rtx_insn *, int);
extern int mep_cop_address_length (rtx_insn *, int);
extern bool mep_expand_mov (rtx *, machine_mode);
extern bool mep_mov_ok (rtx *, machine_mode);
extern void mep_split_wide_move (rtx *, machine_mode);
#ifdef RTX_CODE
extern bool mep_expand_setcc (rtx *);
extern rtx mep_expand_cbranch (rtx *);
#endif
extern const char *mep_emit_cbranch (rtx *, int);
extern void mep_expand_call (rtx *, int);
extern rtx mep_find_base_term (rtx);
extern enum reg_class mep_secondary_input_reload_class (enum reg_class, machine_mode, rtx);
extern enum reg_class mep_secondary_output_reload_class (enum reg_class, machine_mode, rtx);
extern bool mep_secondary_memory_needed (enum reg_class, enum reg_class,
machine_mode);
extern void mep_expand_reload (rtx *, machine_mode);
extern enum reg_class mep_preferred_reload_class (rtx, enum reg_class);
extern int mep_register_move_cost (machine_mode, enum reg_class, enum reg_class);
extern void mep_init_expanders (void);
extern rtx mep_return_addr_rtx (int);
extern bool mep_epilogue_uses (int);
extern int mep_elimination_offset (int, int);
extern void mep_expand_prologue (void);
extern void mep_expand_epilogue (void);
extern void mep_expand_eh_return (rtx *);
extern void mep_emit_eh_epilogue (rtx *);
extern void mep_expand_sibcall_epilogue (void);
extern rtx mep_return_stackadj_rtx (void);
extern rtx mep_return_handler_rtx (void);
extern void mep_function_profiler (FILE *);
extern const char *mep_emit_bb_trace_ret (void);
extern void mep_print_operand_address (FILE *, rtx);
extern void mep_print_operand (FILE *, rtx, int);
extern void mep_final_prescan_insn (rtx_insn *, rtx *, int);
extern void mep_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
extern bool mep_return_in_memory (const_tree, const_tree);
extern rtx mep_function_value (const_tree, const_tree);
extern rtx mep_libcall_value (machine_mode);
extern void mep_asm_output_opcode (FILE *, const char *);
extern void mep_note_pragma_disinterrupt (const char *);
extern void mep_note_pragma_call (const char *);
extern void mep_file_cleanups (void);
extern const char *mep_strip_name_encoding (const char *);
extern void mep_output_aligned_common (FILE *, tree, const char *,
int, int, int);
extern void mep_emit_doloop (rtx *, int);
extern bool mep_vliw_function_p (tree);
extern bool mep_store_data_bypass_p (rtx_insn *, rtx_insn *);
extern bool mep_mul_hilo_bypass_p (rtx_insn *, rtx_insn *);
extern bool mep_ipipe_ldc_p (rtx_insn *);
extern bool mep_emit_intrinsic (int, const rtx *);
extern bool mep_expand_unary_intrinsic (int, rtx *);
extern bool mep_expand_binary_intrinsic (int, int, int, int, rtx *);
extern int mep_intrinsic_length (int);
extern void mep_register_pragmas (void);
extern int mep_section_tag (rtx);
extern bool mep_lookup_pragma_call (const char *);
extern bool mep_have_core_copro_moves_p;
extern bool mep_have_copro_copro_moves_p;
extern bool mep_cannot_change_mode_class (machine_mode, machine_mode,
enum reg_class);
/* These are called from mep-pragmas (front end) and then call into
the RTL layer to re-initialize the register tables once we're done
changing them via pragmas. */
extern void mep_save_register_info (void);
extern void mep_reinit_regs (void);
extern void mep_init_regs (void);
extern int cgen_h_uint_6a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_7a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_8a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_6a2_immediate (rtx, machine_mode);
extern int cgen_h_uint_22a4_immediate (rtx, machine_mode);
extern int cgen_h_sint_2a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_24a1_immediate (rtx, machine_mode);
extern int cgen_h_sint_6a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_5a4_immediate (rtx, machine_mode);
extern int cgen_h_uint_2a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_16a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_3a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_5a1_immediate (rtx, machine_mode);
extern int cgen_h_sint_16a1_immediate (rtx, machine_mode);
extern int cgen_h_sint_8a1_immediate (rtx, machine_mode);
extern int cgen_h_sint_7a2_immediate (rtx, machine_mode);
extern int cgen_h_sint_6a4_immediate (rtx, machine_mode);
extern int cgen_h_sint_5a8_immediate (rtx, machine_mode);
extern int cgen_h_uint_4a1_immediate (rtx, machine_mode);
extern int cgen_h_sint_10a1_immediate (rtx, machine_mode);
extern int cgen_h_sint_12a1_immediate (rtx, machine_mode);
extern int cgen_h_uint_20a1_immediate (rtx, machine_mode);
gcc/config/mep/mep.c deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/mep/mep.cpu deleted 100644 → 0
; Toshiba MeP Media Engine description. -*- Scheme -*-
; Copyright (C) 2009-2016 Free Software Foundation, Inc.
; Contributed by Red Hat, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
(include "mep-default.cpu")
gcc/config/mep/mep.h deleted 100644 → 0
/* Definitions for Toshiba Media Processor
Copyright (C) 2001-2016 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef CPP_SPEC
#define CPP_SPEC "\
-D__MEP__ -D__MeP__ \
-D__section(_x)=__attribute__((section(_x))) \
-D__align(_x)=__attribute__((aligned(_x))) \
-D__io(_x)=__attribute__((io(_x))) \
-D__cb(_x)=__attribute__((cb(_x))) \
-D__based=__attribute__((based)) \
-D__tiny=__attribute__((tiny)) \
-D__near=__attribute__((near)) \
-D__far=__attribute__((far)) \
-D__vliw=__attribute__((vliw)) \
-D__interrupt=__attribute__((interrupt)) \
-D__disinterrupt=__attribute__((disinterrupt)) \
%{!meb:%{!mel:-D__BIG_ENDIAN__}} \
%{meb:-U__LITTLE_ENDIAN__ -D__BIG_ENDIAN__} \
%{mel:-U__BIG_ENDIAN__ -D__LITTLE_ENDIAN__} \
%{mconfig=*:-D__MEP_CONFIG_%*} \
%{mivc2:-D__MEP_CONFIG_CP_DATA_BUS_WIDTH=64} \
"
#undef CC1_SPEC
#define CC1_SPEC "%{!mlibrary:%(config_cc_spec)} \
%{!.cc:%{O2:%{!funroll*:--param max-completely-peeled-insns=6 \
--param max-unrolled-insns=6 -funroll-loops}}}"
#undef CC1PLUS_SPEC
#define CC1PLUS_SPEC "%{!mlibrary:%(config_cc_spec)}"
#undef ASM_SPEC
#define ASM_SPEC "%{mconfig=*} %{meb:-EB} %{mel:-EL} \
%{mno-satur} %{msatur} %{mno-clip} %{mclip} %{mno-minmax} %{mminmax} \
%{mno-absdiff} %{mabsdiff} %{mno-leadz} %{mleadz} %{mno-bitops} %{mbitops} \
%{mno-div} %{mdiv} %{mno-mult} %{mmult} %{mno-average} %{maverage} \
%{mcop32} %{mno-debug} %{mdebug} %{mlibrary}"
/* The MeP config tool will edit this spec. */
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{msdram:%{msim:simsdram-crt0.o%s}} \
%{mno-sdram:%{msim:sim-crt0.o%s}} \
%{msdram:%{!msim*:sdram-crt0.o%s}} \
%{mno-sdram:%{!msim*:crt0.o%s}} \
%(config_start_spec) \
%{msimnovec:simnovec-crt0.o%s} \
crtbegin.o%s"
#undef LIB_SPEC
#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) %(config_link_spec)"
#undef LINK_SPEC
#define LINK_SPEC "%{meb:-EB} %{mel:-EL}"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend.o%s %{msim*:sim-crtn.o%s}%{!msim*:crtn.o%s}"
/* The MeP config tool will edit this spec. */
#define CONFIG_CC_SPEC "\
%{mconfig=default: -mbitops -mleadz -mabsdiff -maverage -mminmax -mclip -msatur -mvl64 -mvliw -mcop64 -D__MEP_CONFIG_CP_DATA_BUS_WIDTH=64 -mivc2}\
"
/* end-config-cc-spec */
/* The MeP config tool will edit this spec. */
#define CONFIG_LINK_SPEC "\
%{mconfig=default: %{!T*:-Tdefault.ld}}\
"
/* end-config-link-spec */
/* The MeP config tool will edit this spec. */
#define CONFIG_START_SPEC "\
%{!msdram:%{!mno-sdram:%{!msim*:crt0.o%s}}} \
%{!msdram:%{!mno-sdram:%{msim:sim-crt0.o%s}}} \
"
/* end-config-start-spec */
#define EXTRA_SPECS \
{ "config_cc_spec", CONFIG_CC_SPEC }, \
{ "config_link_spec", CONFIG_LINK_SPEC }, \
{ "config_start_spec", CONFIG_START_SPEC },
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("mep"); \
builtin_assert ("machine=mep"); \
} \
while (0)
/* Controlled by MeP-Integrator. */
#define TARGET_H1 0
#define MEP_ALL_OPTS (MASK_OPT_AVERAGE \
| MASK_OPT_MULT \
| MASK_OPT_DIV \
| MASK_OPT_BITOPS \
| MASK_OPT_LEADZ \
| MASK_OPT_ABSDIFF \
| MASK_OPT_MINMAX \
| MASK_OPT_CLIP \
| MASK_OPT_SATUR )
#define TARGET_DEFAULT (MASK_IO_VOLATILE | MASK_OPT_REPEAT | MEP_ALL_OPTS | MASK_LITTLE_ENDIAN)
#define TARGET_IO_NO_VOLATILE (! (target_flags & MASK_IO_VOLATILE))
#define TARGET_OPT_NOREPEAT (! (target_flags & MASK_OPT_REPEAT))
#define TARGET_32BIT_CR_REGS (! (target_flags & MASK_64BIT_CR_REGS))
#define TARGET_BIG_ENDIAN (! (target_flags & MASK_LITTLE_ENDIAN))
#define TARGET_COPRO_MULT 0
/* The MeP config tool will replace this as appropriate. */
#define DEFAULT_ENDIAN_SPEC "%{!meb: -mel}"
/* The MeP config tool will replace this with an -mconfig= switch. */
#define LIBRARY_CONFIG_SPEC "-mconfig=default"
/* Don't add an endian option when building the libraries. */
#define DRIVER_SELF_SPECS \
"%{!mlibrary:" DEFAULT_ENDIAN_SPEC "}", \
"%{mlibrary: " LIBRARY_CONFIG_SPEC " %{!mel:-meb}}", \
"%{mall-opts:-maverage -mmult -mdiv -mbitops -mleadz \
-mabsdiff -mminmax -mclip -msatur -mdebug} %<mall-opts", \
"%{mno-opts:-mno-average -mno-mult -mno-div -mno-bitops -mno-leadz \
-mno-absdiff -mno-minmax -mno-clip -mno-satur -mno-debug} %<mno-opts", \
"%{mfar:-ml -mtf -mc=far} %<mfar", \
"%{mconfig=default:-mmult -mdiv -D__MEP_CONFIG_ISA=1}"
/* The MeP config tool will add COPROC_SELECTION_TABLE here. */
/* start-coproc-selection-table */
#define COPROC_SELECTION_TABLE \
{"default", ISA_EXT1}
/* end-coproc-selection-table */
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN ? 0 : 1)
#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN ? 0 : 1)
#define UNITS_PER_WORD 4
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
do \
{ \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
(MODE) = SImode; \
} \
while (0)
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 32
#define PREFERRED_STACK_BOUNDARY 64
#define FUNCTION_BOUNDARY 16
#define BIGGEST_ALIGNMENT 64
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
(TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
#define STRICT_ALIGNMENT 1
#define PCC_BITFIELD_TYPE_MATTERS 1
#define DEFAULT_VTABLE_THUNKS 1
#define INT_TYPE_SIZE 32
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#define CHAR_TYPE_SIZE 8
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE 64
#define DEFAULT_SIGNED_CHAR 1
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "int"
#undef WCHAR_TYPE
#define WCHAR_TYPE "long int"
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE BITS_PER_WORD
/* Register numbers:
0..15 core registers
16..47 control registers
48..79 coprocessor registers
80..111 coprocessor control registers
112 virtual arg pointer register */
#define FIRST_PSEUDO_REGISTER (LAST_SHADOW_REGISTER + 1)
/* R12 is optionally FP. R13 is TP, R14 is GP, R15 is SP. */
/* hi and lo can be used as general registers. Others have
immutable bits. */
/* A "1" here means the register is generally not available to gcc,
and is assumed to remain unchanged or unused throughout. */
#define FIXED_REGISTERS { \
/* core registers */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
/* control registers */ \
1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* coprocessor registers */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* coprocessor control registers */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* virtual arg pointer */ \
1, FIXED_SHADOW_REGISTERS \
}
/* This is a call-clobbered reg not used for args or return value,
that we use as a temp for saving control registers in the prolog
and restoring them in the epilog. */
#define REGSAVE_CONTROL_TEMP 11
/* A "1" here means a register may be changed by a function without
needing to preserve its previous value. */
#define CALL_USED_REGISTERS { \
/* core registers */ \
1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, \
/* control registers */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* coprocessor registers */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* coprocessor control registers */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* virtual arg pointer */ \
1, CALL_USED_SHADOW_REGISTERS \
}
#define REG_ALLOC_ORDER { \
/* core registers */ \
3, 2, 1, 0, 9, 10, 11, 12, 4, 5, 6, 7, 8, 13, 14, 15, \
/* control registers */ \
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
/* coprocessor registers */ \
/* Prefer to use the non-loadable registers when looking for a \
member of CR_REGS (as opposed to LOADABLE_CR_REGS). */ \
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 48, 49, 50, 51, 52, 58, \
59, 60, 61, 62, 63, 53, 54, 55, 56, 57, 74, 75, 76, 77, 78, 79, \
/* coprocessor control registers */ \
80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, \
/* virtual arg pointer */ \
112, SHADOW_REG_ALLOC_ORDER \
}
/* We must somehow disable register remapping for interrupt functions. */
extern char mep_leaf_registers[];
#define LEAF_REGISTERS mep_leaf_registers
#define LEAF_REG_REMAP(REG) (REG)
#define FIRST_GR_REGNO 0
#define FIRST_CONTROL_REGNO (FIRST_GR_REGNO + 16)
#define FIRST_CR_REGNO (FIRST_CONTROL_REGNO + 32)
#define FIRST_CCR_REGNO (FIRST_CR_REGNO + 32)
#define GR_REGNO_P(REGNO) \
((unsigned) ((REGNO) - FIRST_GR_REGNO) < 16)
#define CONTROL_REGNO_P(REGNO) \
((unsigned) ((REGNO) - FIRST_CONTROL_REGNO) < 32)
#define LOADABLE_CR_REGNO_P(REGNO) \
((unsigned) ((REGNO) - FIRST_CR_REGNO) < 16)
#define CR_REGNO_P(REGNO) \
((unsigned) ((REGNO) - FIRST_CR_REGNO) < 32)
#define CCR_REGNO_P(REGNO) \
((unsigned) ((REGNO) - FIRST_CCR_REGNO) < 32)
#define ANY_CONTROL_REGNO_P(REGNO) \
(CONTROL_REGNO_P (REGNO) || CCR_REGNO_P (REGNO))
#define HARD_REGNO_NREGS(REGNO, MODE) \
((CR_REGNO_P (REGNO) && TARGET_64BIT_CR_REGS) \
? (GET_MODE_SIZE (MODE) + 8 - 1) / 8 \
: (GET_MODE_SIZE (MODE) + 4 - 1) / 4)
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
#define MODES_TIEABLE_P(MODE1, MODE2) 1
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
mep_cannot_change_mode_class (FROM, TO, CLASS)
enum reg_class
{
NO_REGS,
SP_REGS,
TP_REGS,
GP_REGS,
R0_REGS,
RPC_REGS,
HI_REGS,
LO_REGS,
HILO_REGS,
TPREL_REGS,
GENERAL_NOT_R0_REGS,
GENERAL_REGS,
CONTROL_REGS,
CONTROL_OR_GENERAL_REGS,
USER0_REGS,
USER1_REGS,
USER2_REGS,
USER3_REGS,
LOADABLE_CR_REGS,
CR_REGS,
CCR_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
#define REG_CLASS_NAMES { \
"NO_REGS", \
"SP_REGS", \
"TP_REGS", \
"GP_REGS", \
"R0_REGS", \
"RPC_REGS", \
"HI_REGS", \
"LO_REGS", \
"HILO_REGS", \
"TPREL_REGS", \
"GENERAL_NOT_R0_REGS", \
"GENERAL_REGS", \
"CONTROL_REGS", \
"CONTROL_OR_GENERAL_REGS", \
"USER0_REGS", \
"USER1_REGS", \
"USER2_REGS", \
"USER3_REGS", \
"LOADABLE_CR_REGS", \
"CR_REGS", \
"CCR_REGS", \
"ALL_REGS" }
#define REG_CLASS_CONTENTS { \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
{ 0x00008000, 0x00000000, 0x00000000, 0x00000000 }, /* SP_REGS */ \
{ 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* TP_REGS */ \
{ 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* GP_REGS */ \
{ 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* R0_REGS */ \
{ 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* RPC_REGS */ \
{ 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
{ 0x01800000, 0x00000000, 0x00000000, 0x00000000 }, /* HILO_REGS */ \
{ 0x000000ff, 0x00000000, 0x00000000, 0x00000000 }, /* TPREL_REGS */ \
{ 0x0000fffe, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_NOT_R0_REGS */ \
{ 0x0000ffff, 0x00000000, 0x00000000, 0x00010000 }, /* GENERAL_REGS */ \
{ 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* CONTROL_REGS */ \
{ 0xffffffff, 0x0000ffff, 0x00000000, 0x00000000 }, /* CONTROL_OR_GENERAL_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER0_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER1_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER2_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER3_REGS */ \
{ 0x00000000, 0xffff0000, 0x00000000, 0x00000000 }, /* LOADABLE_CR_REGS */ \
{ 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* CR_REGS */ \
{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* CCR_REGS */ \
{ 0xffffffff, 0xffffffff, 0xffffffff, 0x0001ffff }, /* ALL_REGS */ \
}
#define REGNO_REG_CLASS(REGNO) (enum reg_class) mep_regno_reg_class (REGNO)
#define BASE_REG_CLASS GENERAL_REGS
#define INDEX_REG_CLASS GENERAL_REGS
#define REGNO_OK_FOR_BASE_P(NUM) (GR_REGNO_P (NUM) \
|| (NUM) == ARG_POINTER_REGNUM \
|| (NUM) >= FIRST_PSEUDO_REGISTER)
#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
#define PREFERRED_RELOAD_CLASS(X, CLASS) mep_preferred_reload_class (X, CLASS)
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
mep_secondary_input_reload_class (CLASS, MODE, X)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
mep_secondary_output_reload_class (CLASS, MODE, X)
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
mep_secondary_memory_needed (CLASS1, CLASS2, MODE)
#define WANT_GCC_DECLARATIONS
#include "mep-intrin.h"
#undef WANT_GCC_DECLARATIONS
extern int mep_intrinsic_insn[];
extern unsigned int mep_selected_isa;
/* True if intrinsic X is available. X is a mep_* value declared
in mep-intrin.h. */
#define MEP_INTRINSIC_AVAILABLE_P(X) (mep_intrinsic_insn[X] >= 0)
/* Used to define CGEN_ENABLE_INTRINSIC_P in mep-intrin.h. */
#define CGEN_CURRENT_ISAS mep_selected_isa
#define CGEN_CURRENT_GROUP \
(mep_vliw_function_p (cfun->decl) ? GROUP_VLIW : GROUP_NORMAL)
#define STACK_GROWS_DOWNWARD 1
#define FRAME_GROWS_DOWNWARD 1
#define STARTING_FRAME_OFFSET 0
#define FIRST_PARM_OFFSET(FUNDECL) 0
#define INCOMING_FRAME_SP_OFFSET 0
#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) mep_return_addr_rtx (COUNT)
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, LP_REGNO)
#define DWARF_FRAME_RETURN_COLUMN LP_REGNO
#define STACK_POINTER_REGNUM 15
#define FRAME_POINTER_REGNUM 8
#define ARG_POINTER_REGNUM 112
#define RETURN_ADDRESS_POINTER_REGNUM 17
#define STATIC_CHAIN_REGNUM 0
#define ELIMINABLE_REGS \
{ \
{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
}
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
(OFFSET) = mep_elimination_offset (FROM, TO)
#define ACCUMULATE_OUTGOING_ARGS 1
#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) 1
typedef struct
{
int nregs;
int vliw;
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
mep_init_cumulative_args (& (CUM), FNTYPE, LIBNAME, FNDECL)
#define FUNCTION_ARG_REGNO_P(REGNO) \
(((REGNO) >= 1 && (REGNO) <= 4) \
|| ((REGNO) >= FIRST_CR_REGNO + 1 \
&& (REGNO) <= FIRST_CR_REGNO + 4 \
&& TARGET_COP))
#define RETURN_VALUE_REGNUM 0
#define FUNCTION_VALUE(VALTYPE, FUNC) mep_function_value (VALTYPE, FUNC)
#define LIBCALL_VALUE(MODE) mep_libcall_value (MODE)
#define FUNCTION_VALUE_REGNO_P(REGNO) \
((REGNO) == RETURN_VALUE_REGNUM)
#define DEFAULT_PCC_STRUCT_RETURN 0
#define FUNCTION_OK_FOR_SIBCALL(DECL) mep_function_ok_for_sibcall(DECL)
/* Prologue and epilogues are all handled via RTL. */
#define EXIT_IGNORE_STACK 1
#define EPILOGUE_USES(REGNO) mep_epilogue_uses (REGNO)
/* Profiling is supported. */
#define FUNCTION_PROFILER(FILE, LABELNO) mep_function_profiler (FILE);
#define NO_PROFILE_COUNTERS 1
/* Trampolines are built at run-time. The cache is invalidated at
run-time also. */
#define TRAMPOLINE_SIZE 20
#define MAX_REGS_PER_ADDRESS 1
#ifdef REG_OK_STRICT
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
if (mep_legitimate_address ((MODE), (X), 1)) goto LABEL
#else
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
if (mep_legitimate_address ((MODE), (X), 0)) goto LABEL
#endif
#ifdef REG_OK_STRICT
#define REG_OK_FOR_BASE_P(X) GR_REGNO_P (REGNO (X))
#else
#define REG_OK_FOR_BASE_P(X) (GR_REGNO_P (REGNO (X)) \
|| REGNO (X) == ARG_POINTER_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
#endif
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
if (mep_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE), (IND_LEVELS))) \
goto WIN
#define SELECT_CC_MODE(OP, X, Y) CCmode
/* Moves between control regs need a scratch. */
#define REGISTER_MOVE_COST(MODE, FROM, TO) mep_register_move_cost (MODE, FROM, TO)
#define SLOW_BYTE_ACCESS 1
/* Define this macro if it is as good or better to call a constant function
address than to call an address kept in a register. */
#define NO_FUNCTION_CSE 1
#define TEXT_SECTION_ASM_OP "\t.text\n\t.core"
#define DATA_SECTION_ASM_OP "\t.data"
#define BSS_SECTION_ASM_OP ".bss"
#define USE_SELECT_SECTION_FOR_FUNCTIONS 1
#define JUMP_TABLES_IN_TEXT_SECTION 1
#define TARGET_ASM_FILE_END mep_file_cleanups
#define ASM_APP_ON "#APP\n"
#define ASM_APP_OFF "#NO_APP\n"
#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
do \
{ \
long l[2]; \
\
REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
fprintf (FILE, "\t.long\t0x%lx,0x%lx\n", l[0], l[1]); \
} \
while (0)
#define ASM_OUTPUT_FLOAT(FILE, VALUE) \
do \
{ \
long l; \
\
REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
fprintf ((FILE), "\t.long\t0x%lx\n", l); \
} \
while (0)
#define ASM_OUTPUT_CHAR(FILE, VALUE) \
do \
{ \
fprintf (FILE, "\t.byte\t"); \
output_addr_const (FILE, (VALUE)); \
fprintf (FILE, "\n"); \
} \
while (0)
#define ASM_OUTPUT_SHORT(FILE, VALUE) \
do \
{ \
fprintf (FILE, "\t.hword\t"); \
output_addr_const (FILE, (VALUE)); \
fprintf (FILE, "\n"); \
} \
while (0)
#define ASM_OUTPUT_INT(FILE, VALUE) \
do \
{ \
fprintf (FILE, "\t.word\t"); \
output_addr_const (FILE, (VALUE)); \
fprintf (FILE, "\n"); \
} \
while (0)
/* Most of these are here to support based/tiny/far/io attributes. */
#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
mep_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
mep_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
#define ASM_OUTPUT_LABEL(STREAM, NAME) \
do \
{ \
assemble_name (STREAM, NAME); \
fputs (":\n", STREAM); \
} \
while (0)
/* Globalizing directive for a label. */
#define GLOBAL_ASM_OP "\t.globl "
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
asm_fprintf ((STREAM), "%U%s", mep_strip_name_encoding (NAME))
#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
do \
{ \
(OUTVAR) = (char *) alloca (strlen ((NAME)) + 12); \
sprintf ((OUTVAR), "%s.%ld", (NAME), (long)(NUMBER)); \
} \
while (0)
#define REGISTER_NAMES \
{ \
/* Core registers. */ \
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
"$8", "$9", "$10", "$11", "$12", "$tp", "$gp", "$sp", \
/* Control registers. */ \
"$pc", "$lp", "$sar", "3", "$rpb", "$rpe", "$rpc", "$hi", \
"$lo", "9", "10", "11", "$mb0", "$me0", "$mb1", "$me1", \
"$psw", "$id", "$tmp", "$epc", "$exc", "$cfg", "22", "$npc", \
"$dbg", "$depc", "$opt", "$rcfg", "$ccfg", "29", "30", "31", \
/* Coprocessor registers. */ \
"$c0", "$c1", "$c2", "$c3", "$c4", "$c5", "$c6", "$c7", \
"$c8", "$c9", "$c10", "$c11", "$c12", "$c13", "$c14", "$c15", \
"$c16", "$c17", "$c18", "$c19", "$c20", "$c21", "$c22", "$c23", \
"$c24", "$c25", "$c26", "$c27", "$c28", "$c29", "$c30", "$c31", \
/* Coprocessor control registers. */ \
"$ccr0", "$ccr1", "$ccr2", "$ccr3", "$ccr4", "$ccr5", "$ccr6", \
"$ccr7", "$ccr8", "$ccr9", "$ccr10", "$ccr11", "$ccr12", "$ccr13", \
"$ccr14", "$ccr15", "$ccr16", "$ccr17", "$ccr18", "$ccr19", "$ccr20", \
"$ccr21", "$ccr22", "$ccr23", "$ccr24", "$ccr25", "$ccr26", "$ccr27", \
"$ccr28", "$ccr29", "$ccr30", "$ccr31", \
/* Virtual arg pointer. */ \
"$argp", SHADOW_REGISTER_NAMES \
}
/* We duplicate some of the above because we twiddle the above
according to *how* the registers are used. Likewise, we include
the standard names for coprocessor control registers so that
coprocessor options can rename them in the default table. Note
that these are compared to stripped names (see REGISTER_PREFIX
below). */
#define ADDITIONAL_REGISTER_NAMES \
{ \
{ "8", 8 }, { "fp", 8 }, \
{ "13", 13 }, { "tp", 13 }, \
{ "14", 14 }, { "gp", 14 }, \
{ "15", 15 }, { "sp", 15 }, \
{ "ccr0", FIRST_CCR_REGNO + 0 }, \
{ "ccr1", FIRST_CCR_REGNO + 1 }, \
{ "ccr2", FIRST_CCR_REGNO + 2 }, \
{ "ccr3", FIRST_CCR_REGNO + 3 }, \
{ "ccr4", FIRST_CCR_REGNO + 4 }, \
{ "ccr5", FIRST_CCR_REGNO + 5 }, \
{ "ccr6", FIRST_CCR_REGNO + 6 }, \
{ "ccr7", FIRST_CCR_REGNO + 7 }, \
{ "ccr8", FIRST_CCR_REGNO + 8 }, \
{ "ccr9", FIRST_CCR_REGNO + 9 }, \
{ "ccr10", FIRST_CCR_REGNO + 10 }, \
{ "ccr11", FIRST_CCR_REGNO + 11 }, \
{ "ccr12", FIRST_CCR_REGNO + 12 }, \
{ "ccr13", FIRST_CCR_REGNO + 13 }, \
{ "ccr14", FIRST_CCR_REGNO + 14 }, \
{ "ccr15", FIRST_CCR_REGNO + 15 }, \
{ "ccr16", FIRST_CCR_REGNO + 16 }, \
{ "ccr17", FIRST_CCR_REGNO + 17 }, \
{ "ccr18", FIRST_CCR_REGNO + 18 }, \
{ "ccr19", FIRST_CCR_REGNO + 19 }, \
{ "ccr20", FIRST_CCR_REGNO + 20 }, \
{ "ccr21", FIRST_CCR_REGNO + 21 }, \
{ "ccr22", FIRST_CCR_REGNO + 22 }, \
{ "ccr23", FIRST_CCR_REGNO + 23 }, \
{ "ccr24", FIRST_CCR_REGNO + 24 }, \
{ "ccr25", FIRST_CCR_REGNO + 25 }, \
{ "ccr26", FIRST_CCR_REGNO + 26 }, \
{ "ccr27", FIRST_CCR_REGNO + 27 }, \
{ "ccr28", FIRST_CCR_REGNO + 28 }, \
{ "ccr29", FIRST_CCR_REGNO + 29 }, \
{ "ccr30", FIRST_CCR_REGNO + 30 }, \
{ "ccr31", FIRST_CCR_REGNO + 31 } \
}
/* We watch for pipeline hazards with these */
#define ASM_OUTPUT_OPCODE(STREAM, PTR) mep_asm_output_opcode (STREAM, PTR)
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) mep_final_prescan_insn (INSN, OPVEC, NOPERANDS)
#define PRINT_OPERAND(STREAM, X, CODE) mep_print_operand (STREAM, X, CODE)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '!' || (CODE) == '<')
#define PRINT_OPERAND_ADDRESS(STREAM, X) mep_print_operand_address (STREAM, X)
#define REGISTER_PREFIX "$"
#define LOCAL_LABEL_PREFIX "."
#define USER_LABEL_PREFIX ""
#define IMMEDIATE_PREFIX ""
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
fprintf (STREAM, "\t.word .L%d\n", VALUE)
#undef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
#define DWARF2_DEBUGGING_INFO 1
#define DWARF2_UNWIND_INFO 1
#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 10 : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX mep_return_stackadj_rtx ()
#define EH_RETURN_HANDLER_RTX mep_return_handler_rtx ()
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
fprintf ((STREAM), "\t.p2align %d\n", (POWER))
#define CASE_VECTOR_MODE SImode
#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
#define SHORT_IMMEDIATES_SIGN_EXTEND 1
#define MOVE_MAX 4
#define SHIFT_COUNT_TRUNCATED 1
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define STORE_FLAG_VALUE 1
#define Pmode SImode
#define FUNCTION_MODE SImode
#define REGISTER_TARGET_PRAGMAS() mep_register_pragmas ()
/* If defined, a C expression to determine the base term of address X.
This macro is used in only one place: `find_base_term' in alias.c.
It is always safe for this macro to not be defined. It exists so
that alias analysis can understand machine-dependent addresses.
The typical use of this macro is to handle addresses containing
a label_ref or symbol_ref within an UNSPEC. */
#define FIND_BASE_TERM(X) mep_find_base_term (X)
gcc/config/mep/mep.md deleted 100644 → 0
;; Toshiba Media Processor Machine description template
;; Copyright (C) 2001-2016 Free Software Foundation, Inc.
;; Contributed by Red Hat Inc
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
;; Constraints:
;;
;; a $sp
;; b $tp
;; c control regs
;; h $hi ($23)
;; l $lo ($24)
;; d $hi/$lo pair (DImode)
;; j $rpc ($22)
;; r $0..$15
;; t $0..$7
;; v $gp
;; x $c0..$c31
;; ex coprocessor registers that can be moved to other coprocessor registers
;; er coprocessor registers that can be moved to and from core registers
;; em coprocessor registers that can be moves to and from memory
;; y $ccr0..$ccr31
;; z $0
;;
;; I sign imm16 mov/add
;; J zero imm16 mov/add
;; K zero imm24 mov
;; L sign imm6 add
;; M zero imm5 slt,shifts
;; N zero imm4 bCC
;; O high imm16 mov
;;
;; R near symbol
;; S sign imm8 mov
;; T tp or gp relative symbol
;; U non-absolute memory
;; W %hi(sym)
;; Y (Rn)
;; Z Control Bus Symbol
;;
;; Modifiers:
;;
;; b print unique bit in mask
;; B print bits required for value (for clip)
;; h print decimal >> 16.
;; I print decimal, with hex comment if more than 8 bits
;; J print unsigned hex
;; L print set, clr or not (for bitops)
;; P print memory as a post-inc with no increment
;; U print bits required for value (for clipu)
;; x print unsigned decimal or hex, depending on where set bits are
(define_constants [
(REGSAVE_CONTROL_TEMP 11)
(FP_REGNO 8)
(TP_REGNO 13)
(GP_REGNO 14)
(SP_REGNO 15)
(PSW_REGNO 16)
(LP_REGNO 17)
(SAR_REGNO 18)
(RPB_REGNO 20)
(RPE_REGNO 21)
(RPC_REGNO 22)
(HI_REGNO 23)
(LO_REGNO 24)
(CBCR_REGNO 81)
])
(define_constants [
(UNS_BLOCKAGE 0)
(UNS_TPREL 2)
(UNS_GPREL 3)
(UNS_REPEAT_BEG 4)
(UNS_REPEAT_END 5)
(UNS_EH_EPILOGUE 6)
(UNS_EREPEAT_BEG 7)
(UNS_EREPEAT_END 8)
(UNS_BB_TRACE_RET 9)
(UNS_DISABLE_INT 10)
(UNS_ENABLE_INT 11)
(UNS_RETI 12)
])
;; This attribute determines the VLIW packing mechanism. The IVC2
;; coprocessor has two pipelines (P0 and P1), and a MeP+IVC2 can issue
;; up to three insns at a time. Most IVC2 insns can run on either
;; pipeline, however, scheduling some insns on P0 precludes packing a
;; core insn with it, and only 16-bit core insns can pack with any P0
;; insn.
(define_attr "vliw" "basic,ivc2"
(const (symbol_ref "TARGET_IVC2")))
;; This attribute describes the kind of memory operand present in the
;; instruction. This is used to compute the length of the insn based
;; on the addressing mode used.
(define_attr "memop" "none,core0,core1,cop0,cop1"
(const_string "none"))
(define_attr "intrinsic" "none,cmov,cmov1,cmov2,cmovc1,cmovc2,cmovh1,cmovh2"
(const_string "none"))
;; This attribute describes how the instruction may be bundled in a
;; VLIW instruction. Type MULTI is assumed to use both slots.
(define_attr "slot" "core,cop,multi"
(cond [(eq_attr "intrinsic" "!none")
(const_string "cop")]
(const_string "core")))
;; This attribute describes the latency of the opcode (ready delay).
;; The 0 is used to indicate "unspecified". An instruction that
;; completes immediately with no potential stalls would have a value
;; of 1, a one cycle stall would be 2, etc.
(define_attr "latency" ""
(const_int 0))
(define_attr "shiftop" "none,operand2"
(const_string "none"))
;; This attribute describes the size of the instruction in bytes.
;; This *must* be exact unless the pattern is SLOT_MULTI, as this
;; is used by the VLIW bundling code.
(define_attr "length" ""
(cond [(eq_attr "memop" "core0")
(symbol_ref "mep_core_address_length (insn, 0)")
(eq_attr "memop" "core1")
(symbol_ref "mep_core_address_length (insn, 1)")
(eq_attr "memop" "cop0")
(symbol_ref "mep_cop_address_length (insn, 0)")
(eq_attr "memop" "cop1")
(symbol_ref "mep_cop_address_length (insn, 1)")
]
; Catch patterns that don't define the length properly.
(symbol_ref "(abort (), 0)")))
;; This attribute describes a pipeline hazard seen in the insn.
(define_attr "stall" "none,int2,ssarb,load,store,ldc,stc,ldcb,stcb,ssrab,fsft,ret,advck,mul,mulr,div"
(cond [(and (eq_attr "shiftop" "operand2")
(not (match_operand:SI 2 "mep_single_shift_operand" "")))
(const_string "int2")]
(const_string "none")))
(define_attr "may_trap" "no,yes"
(const_string "no"))
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "length" "4")
(set_attr "slot" "multi")])
;; Each IVC2 instruction uses one of these two pipelines. P0S insns
;; use P0; C3 insns use P1.
(define_automaton "mep_ivc2")
(define_cpu_unit "ivc2_core,ivc2_p0,ivc2_p1" "mep_ivc2")
;; Each core or IVC2 instruction is bundled into one of these slots.
;; Supported bundlings:
;;
;; Core mode:
;;
;; C1 [-----core-----]
;; C2 [-------------core-------------]
;; C3 [--------------c3--------------]
;;
;; VLIW mode:
;;
;; V1 [-----core-----][--------p0s-------][------------p1------------]
;; V2 [-------------core-------------]xxxx[------------p1------------]
;; V3 1111[--p0--]0111[--------p0--------][------------p1------------]
(define_attr "slots" "core,c3,p0,p0_p0s,p0_p1,p0s,p0s_p1,p1" (const_string "core"))
(define_cpu_unit "ivc2_slot_c16,ivc2_slot_c32,ivc2_slot_c3,ivc2_slot_p0s,ivc2_slot_p0,ivc2_slot_p1" "mep_ivc2")
(define_insn_reservation "ivc2_insn_core16" 1
(and (eq_attr "vliw" "ivc2")
(and (eq (symbol_ref "get_attr_length(insn)") (const_int 2))
(and (eq_attr "intrinsic" "none")
(eq_attr "slot" "!cop"))))
"ivc2_core+ivc2_slot_c16")
(define_insn_reservation "ivc2_insn_core32" 1
(and (eq_attr "vliw" "ivc2")
(and (eq (symbol_ref "get_attr_length(insn)") (const_int 4))
(and (eq_attr "intrinsic" "none")
(eq_attr "slot" "!cop"))))
"ivc2_core+ivc2_slot_c32")
;; These shouldn't happen when in VLIW mode.
(define_insn_reservation "ivc2_insn_c3" 1
(and (eq_attr "vliw" "ivc2")
(eq_attr "slots" "c3"))
"ivc2_p1+ivc2_slot_c3")
(define_insn_reservation "ivc2_insn_p0" 1
(and (eq_attr "vliw" "ivc2")
(eq_attr "slots" "p0"))
"ivc2_p0+ivc2_slot_p0")
(define_insn_reservation "ivc2_insn_p0_p0s" 1
(and (eq_attr "vliw" "ivc2")
(eq_attr "slots" "p0_p0s"))
"ivc2_p0+ivc2_slot_p0|ivc2_p0+ivc2_slot_p0s")
(define_insn_reservation "ivc2_insn_p0_p1" 1
(and (eq_attr "vliw" "ivc2")
(eq_attr "slots" "p0_p1"))
"ivc2_p0+ivc2_slot_p0|ivc2_p1+ivc2_slot_p1")
(define_insn_reservation "ivc2_insn_p0s" 1
(and (eq_attr "vliw" "ivc2")
(eq_attr "slots" "p0s"))
"ivc2_p0+ivc2_slot_p0s")
(define_insn_reservation "ivc2_insn_p0s_p1" 1
(and (eq_attr "vliw" "ivc2")
(eq_attr "slots" "p0s_p1"))
"ivc2_p0+ivc2_slot_p0s|ivc2_p1+ivc2_slot_p1")
(define_insn_reservation "ivc2_insn_p1" 1
(and (eq_attr "vliw" "ivc2")
(eq_attr "slots" "p1"))
"ivc2_p1+ivc2_slot_p1")
;; these run in C3 also, but when we're doing VLIW scheduling, they
;; only run in P0.
(define_insn_reservation "ivc2_insn_cmov" 1
(and (eq_attr "vliw" "ivc2")
(eq_attr "intrinsic" "!none"))
"ivc2_p0+ivc2_slot_p0")
(exclusion_set "ivc2_slot_c32"
"ivc2_slot_p0,ivc2_slot_p0s")
(exclusion_set "ivc2_slot_p0"
"ivc2_slot_p0s")
(exclusion_set "ivc2_slot_c16"
"ivc2_slot_p0")
(exclusion_set "ivc2_slot_c16"
"ivc2_slot_c32")
;; Non-IVC2 scheduling.
(define_automaton "mep")
(define_cpu_unit "core,cop" "mep")
;; Latencies are the time between one insn entering the second pipeline
;; stage (E2, LD, A2 or V2) and the next instruction entering the same
;; stage. When an instruction assigns to general registers, the default
;; latencies are for when the next instruction receives the register
;; through bypass 1.
;; Arithmetic instructions that execute in a single stage.
(define_insn_reservation "h1_int1" 2
(and (eq_attr "slot" "!cop")
(eq_attr "stall" "none"))
"core")
(define_bypass 1 "h1_int1" "h1_int1,h1_ssarb")
(define_bypass 1 "h1_int1" "h1_store" "mep_store_data_bypass_p")
;; $sar can be read by an immediately following fsft or ldc.
(define_insn_reservation "h1_ssarb" 1
(eq_attr "stall" "ssarb")
"core")
;; Arithmetic instructions that execute in two stages.
(define_insn_reservation "h1_int2" 2
(eq_attr "stall" "int2,fsft")
"core")
(define_bypass 1 "h1_int2" "h1_int1,h1_ssarb")
(define_bypass 1 "h1_int2" "h1_store" "mep_store_data_bypass_p")
(define_insn_reservation "h1_load" 4
(eq_attr "stall" "load")
"core")
(define_bypass 3 "h1_load" "h1_int1,h1_ssarb")
(define_bypass 3 "h1_load" "h1_store" "mep_store_data_bypass_p")
(define_insn_reservation "h1_store" 1
(eq_attr "stall" "store")
"core")
(define_insn_reservation "h1_ipipe_ldc" 2
(and (eq_attr "stall" "ldc")
(ne (symbol_ref "mep_ipipe_ldc_p(insn)") (const_int 0)))
"core")
(define_bypass 1 "h1_ipipe_ldc" "h1_int1,h1_ssarb")
(define_bypass 1 "h1_ipipe_ldc" "h1_store" "mep_store_data_bypass_p")
(define_insn_reservation "h1_apipe_ldc" 2
(and (eq_attr "stall" "ldc")
(eq (symbol_ref "mep_ipipe_ldc_p(insn)") (const_int 0)))
"core")
;; 2 is correct for stc->ret and stc->fsft. The most important remaining
;; case is stc->madd, which induces no stall.
(define_insn_reservation "h1_stc" 2
(eq_attr "stall" "stc")
"core")
(define_bypass 1 "h1_stc" "h1_mul")
;; ??? Parameterised latency.
(define_insn_reservation "h1_ldcb" 5
(eq_attr "stall" "ldcb")
"core")
(define_insn_reservation "h1_stcb" 1
(eq_attr "stall" "stcb")
"core")
(define_insn_reservation "h1_advck" 6
(eq_attr "stall" "advck")
"core")
(define_insn_reservation "h1_mul" 5
(eq_attr "stall" "mul,mulr")
"core")
(define_bypass 4 "h1_mul" "h1_int1,h1_ssarb")
(define_bypass 4 "h1_mul" "h1_store" "mep_store_data_bypass_p")
(define_bypass 1 "h1_mul" "h1_mul" "mep_mul_hilo_bypass_p")
(define_insn_reservation "h1_div" 36
(eq_attr "stall" "div")
"core")
(define_insn_reservation "h1_cop" 1
(eq_attr "slot" "cop")
"cop")
(include "predicates.md")
(include "constraints.md")
(include "intrinsics.md")
;; ::::::::::::::::::::
;; ::
;; :: Moves
;; ::
;; ::::::::::::::::::::
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
"
{
if (mep_expand_mov (operands, QImode))
DONE;
}")
;; The Idea here is to prefer the 16-bit tp-relative load, but to fall back
;; to the general 32-bit load rather than do silly things with spill regs.
(define_insn "*movqi_tprel_load"
[(set (match_operand:QI 0 "mep_tprel_operand" "=t,*r")
(mem:QI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
(const:SI (unspec:SI [(match_operand:SI 2
"symbolic_operand" "s,s")]
UNS_TPREL)))))]
""
"lb\\t%0, %%tpoff(%2)(%1)"
[(set_attr "length" "2,4")
(set_attr "stall" "load")])
(define_insn "*movqi_tprel_store"
[(set (mem:QI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
(const:SI (unspec:SI [(match_operand:SI 1
"symbolic_operand" "s,s")]
UNS_TPREL))))
(match_operand:QI 2 "mep_tprel_operand" "t,*r"))]
""
"sb\\t%2, %%tpoff(%1)(%0)"
[(set_attr "length" "2,4")
(set_attr "stall" "store")])
(define_insn "*movqi_internal"
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r, r,m,r,c,r,y,r,er,ex,em,Y")
(match_operand:QI 1 "general_operand" " r,n,rm,r,c,r,y,r,er,r,ex,Y,em"))]
"mep_mov_ok (operands, QImode)"
"@
mov\\t%0, %1
mov\\t%0, %1
lb\\t%0, %1
sb\\t%1, %0
ldc\\t%0, %1
stc\\t%1, %0
cmovc\\t%0, %1
cmovc\\t%0, %1
cmov\\t%0, %1
cmov\\t%0, %1
%<\\t%0, %M1
lbcpa\\t%0, %P1
sbcpa\\t%1, %P0"
[(set_attr "length" "2,2,*,*,2,2,4,4,4,4,*,4,4")
(set_attr "intrinsic" "*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
(set_attr "stall" "*,*,load,store,ldc,stc,*,*,*,*,*,load,store")
(set_attr "memop" "*,*,core1,core0,*,*,*,*,*,*,*,*,*")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))]
""
"
{
if (mep_expand_mov (operands, HImode))
DONE;
}")
(define_insn "*movhi_tprel_load"
[(set (match_operand:HI 0 "mep_tprel_operand" "=t,*r")
(mem:HI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
(const:SI (unspec:SI [(match_operand:SI 2
"symbolic_operand" "s,s")]
UNS_TPREL)))))]
""
"lh\\t%0, %%tpoff(%2)(%1)"
[(set_attr "length" "2,4")
(set_attr "stall" "load")])
(define_insn "*movhi_tprel_store"
[(set (mem:HI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
(const:SI (unspec:SI [(match_operand:SI 1
"symbolic_operand" "s,s")]
UNS_TPREL))))
(match_operand:HI 2 "mep_tprel_operand" "t,*r"))]
""
"sh\\t%2, %%tpoff(%1)(%0)"
[(set_attr "length" "2,4")
(set_attr "stall" "store")])
(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,m,r,c,r,y,r,er,ex,em,Y")
(match_operand:HI 1 "general_operand" " r,S,n,m,r,c,r,y,r,er,r,ex,Y,em"))]
"mep_mov_ok (operands, HImode)"
"@
mov\\t%0, %1
mov\\t%0, %I1
mov\\t%0, %I1
lh\\t%0, %1
sh\\t%1, %0
ldc\\t%0, %1
stc\\t%1, %0
cmovc\\t%0, %1
cmovc\\t%0, %1
cmov\\t%0, %1
cmov\\t%0, %1
%<\\t%0, %M1
lhcpa\\t%0, %P1
shcpa\\t%1, %P0"
[(set_attr "length" "2,2,4,*,*,2,2,4,4,4,4,*,4,4")
(set_attr "intrinsic" "*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
(set_attr "stall" "*,*,*,load,store,ldc,stc,*,*,*,*,*,load,store")
(set_attr "memop" "*,*,*,core1,core0,*,*,*,*,*,*,*,*,*")])
(define_expand "movsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:SI 1 "general_operand" ""))]
""
"
{
if (mep_expand_mov (operands, SImode))
DONE;
}")
(define_insn "*movsi_tprel_load"
[(set (match_operand:SI 0 "mep_tprel_operand" "=t,*r")
(mem:SI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
(const:SI (unspec:SI [(match_operand:SI 2
"symbolic_operand" "s,s")]
UNS_TPREL)))))]
""
"lw\\t%0, %%tpoff(%2)(%1)"
[(set_attr "length" "2,4")
(set_attr "stall" "load")])
(define_insn "*movsi_tprel_store"
[(set (mem:SI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
(const:SI (unspec:SI [(match_operand:SI 1
"symbolic_operand" "s,s")]
UNS_TPREL))))
(match_operand:SI 2 "mep_tprel_operand" "t,*r"))]
""
"sw\\t%2, %%tpoff(%1)(%0)"
[(set_attr "length" "2,4")
(set_attr "stall" "store")])
(define_insn "movsi_topsym_s"
[(set (match_operand:SI 0 "register_operand" "=r")
(high:SI (match_operand:SI 1 "symbolic_operand" "s")))]
""
"movh\\t%0, %%hi(%1)"
[(set_attr "length" "4")])
(define_insn "movsi_botsym_s"
[(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "symbolic_operand" "s")))]
""
"add3\\t%0, %1, %%lo(%2)"
[(set_attr "length" "4")])
(define_insn "cmovh_getsub"
[(set (match_operand:SI 0 "register_operand" "=r")
(subreg:SI (match_operand:DI 1 "register_operand" "er") 4))]
"0 && TARGET_64BIT_CR_REGS"
"cmovh\\t%0, %1"
[(set_attr "intrinsic" "cmovh2")
(set_attr "length" "4")])
(define_insn "*movsi_internal"
[(set (match_operand:SI 0 "mep_movdest_operand"
"=r,r,r,r,r, t,t,r,r,r,Z,m,r,c,r,y,r, er,ex,em,U ")
(match_operand:SI 1 "general_operand"
" r,S,I,J,OW,K,s,i,Z,m,r,r,c,r,y,r,er,r, ex,U, em"))]
"mep_mov_ok (operands, SImode)"
"@
mov\\t%0, %1
mov\\t%0, %I1
mov\\t%0, %I1
movu\\t%0, %J1
movh\\t%0, %h1
movu\\t%0, %x1
movu\\t%0, %1
#
ldcb\\t%0, %1
lw\\t%0, %1
stcb\\t%1, %0
sw\\t%1, %0
ldc\\t%0, %1
stc\\t%1, %0
cmovc\\t%0, %1
cmovc\\t%0, %1
cmov\\t%0, %1
cmov\\t%0, %1
%<\\t%0, %M1
lwcp\\t%0, %1
swcp\\t%1, %0"
[(set_attr "length" "2,2,4,4,4,4,4,*,4,*,4,*,2,2,4,4,4,4,4,*,*")
(set_attr "intrinsic" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
(set_attr "stall" "*,*,*,*,*,*,*,*,ldcb,load,stcb,store,ldc,stc,*,*,*,*,*,load,store")
(set_attr "memop" "*,*,*,*,*,*,*,*,*,core1,*,core0,*,*,*,*,*,*,*,cop1,cop0")
(set_attr "slot" "*,*,*,*,*,*,*,multi,*,*,*,*,*,*,*,*,*,*,*,*,*")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
"mep_split_mov (operands, 0)"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
"
{
HOST_WIDE_INT value;
int lo, hi;
value = INTVAL (operands[1]);
lo = value & 0xffff;
hi = trunc_int_for_mode (value & 0xffff0000, SImode);
operands[2] = GEN_INT (hi);
operands[3] = GEN_INT (lo);
}")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "immediate_operand" ""))]
"mep_split_mov (operands, 1)"
[(set (match_dup 0) (high:SI (match_dup 1)))
(set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
"")
;; ??? What purpose do these two serve that high+lo_sum do not?
(define_insn "movsi_topsym_u"
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (match_operand:SI 1 "symbolic_operand" "s")
(const_int -65536)))]
""
"movh\\t%0, %%uhi(%1)"
[(set_attr "length" "4")])
(define_insn "movsi_botsym_u"
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (match_operand:SI 1 "register_operand" "0")
(and:SI (match_operand:SI 2 "symbolic_operand" "s")
(const_int 65535))))]
""
"or3\\t%0, %1, %%lo(%2)"
[(set_attr "length" "4")])
(define_expand "movdi"
[(set (match_operand:DI 0 "" "")
(match_operand:DI 1 "" ""))]
""
"
{
if (mep_expand_mov (operands, DImode))
DONE;
}")
(define_insn "*movdi_internal_32"
[(set (match_operand:DI 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
(match_operand:DI 1 "general_operand" "rim,r,c,r,er,r,ex,U,em"))]
"TARGET_32BIT_CR_REGS && mep_mov_ok (operands, DImode)"
"#"
[(set_attr "slot" "multi")])
(define_insn "*movdi_internal_64"
[(set (match_operand:DI 0 "mep_movdest_operand" "=r,r,m,r,c,r,er,ex,em,U")
(match_operand:DI 1 "general_operand" "r,im,r,c,r,er,r,ex,U,em"))]
"TARGET_64BIT_CR_REGS && mep_mov_ok (operands, DImode)"
"@
#
#
#
#
#
#
#
%<\\t%0, %M1
lmcp\\t%0, %1
smcp\\t%1, %0"
[(set_attr "slot" "multi,multi,multi,multi,multi,multi,multi,*,*,*")
(set_attr "intrinsic" "*,*,*,*,*,*,*,cmov,*,*")
(set_attr "memop" "*,*,*,*,*,*,*,cop0,cop1,cop0")
(set_attr "stall" "*,*,*,*,*,*,*,*,load,store")])
(define_insn "*movdi_cop_postinc"
[(parallel [(set (match_operand:DI 0 "register_operand" "=em")
(mem:DI (reg:SI SP_REGNO)))
(set (reg:SI SP_REGNO)
(plus:SI (reg:SI SP_REGNO)
(const_int 8)))
]
)]
"TARGET_COP"
"lmcpi\\t%0,($sp+)"
[(set_attr "length" "2")])
(define_insn "*movdi_cop_postinc"
[(parallel [(set (match_operand:DI 0 "register_operand" "=em")
(mem:DI (match_operand:SI 2 "register_operand" "r")))
(set (match_operand:SI 1 "register_operand" "=0")
(plus:SI (match_operand:SI 3 "register_operand" "0")
(const_int 8)))
]
)]
"TARGET_COP"
"lmcpi\\t%0,(%1+)"
[(set_attr "length" "2")])
(define_insn "*cmovh_set"
[(set (zero_extract:SI (match_operand:DI 0 "register_operand" "+er")
(const_int 32)
(const_int 32))
(match_operand:SI 1 "register_operand" "r"))]
"TARGET_64BIT_CR_REGS"
"cmovh\\t%0, %1"
[(set_attr "intrinsic" "cmovh1")
(set_attr "length" "4")])
(define_insn "cmovh_get"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:DI 1 "register_operand" "er")
(const_int 32)
(const_int 32)))]
"TARGET_64BIT_CR_REGS"
"cmovh\\t%0, %1"
[(set_attr "intrinsic" "cmovh2")
(set_attr "length" "4")])
(define_split
[(set (match_operand:DI 0 "mep_movdest_operand" "")
(match_operand:DI 1 "general_operand" ""))]
"reload_completed && mep_multi_slot (insn)"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))]
"mep_split_wide_move (operands, DImode);")
;; Floating Point Moves
(define_expand "movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "general_operand" ""))]
""
"
{
if (mep_expand_mov (operands, SFmode))
DONE;
}")
(define_insn "*movsf_tprel_load"
[(set (match_operand:SF 0 "mep_tprel_operand" "=t,*r")
(mem:SF (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
(const:SI (unspec:SI [(match_operand:SI 2
"symbolic_operand" "s,s")]
UNS_TPREL)))))]
""
"lw\\t%0, %%tpoff(%2)(%1)"
[(set_attr "length" "2,4")
(set_attr "stall" "load")])
(define_insn "*movsf_tprel_store"
[(set (mem:SF (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
(const:SI (unspec:SI [(match_operand:SI 1
"symbolic_operand" "s,s")]
UNS_TPREL))))
(match_operand:SF 2 "mep_tprel_operand" "t,*r"))]
""
"sw\\t%2, %%tpoff(%1)(%0)"
[(set_attr "length" "2,4")
(set_attr "stall" "store")])
(define_insn "*movsf_internal"
[(set (match_operand:SF 0 "mep_movdest_operand"
"=r,r,r,r,Z,m,r,c,r,y,r,er,ex,em,U")
(match_operand:SF 1 "general_operand"
" r,F,Z,m,r,r,c,r,y,r,er,r,ex,U,em"))]
"mep_mov_ok (operands, SFmode)"
"@
mov\\t%0, %1
#
ldcb\\t%0, %1
lw\\t%0, %1
stcb\\t%1, %0
sw\\t%1, %0
ldc\\t%0, %1
stc\\t%1, %0
cmovc\\t%0, %1
cmovc\\t%0, %1
cmov\\t%0, %1
cmov\\t%0, %1
%<\\t%0, %M1
lwcp\\t%0, %1
swcp\\t%1, %0"
[(set_attr "length" "2,*,2,*,2,*,2,2,*,*,4,4,*,*,*")
(set_attr "intrinsic" "*,*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
(set_attr "stall" "*,*,ldcb,load,stcb,store,ldc,stc,*,*,*,*,*,load,store")
(set_attr "memop" "*,*,*,core1,*,core0,*,*,*,*,*,*,*,cop1,cop0")])
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(match_operand:SF 1 "const_double_operand" ""))]
"reload_completed"
[(const_int 0)]
"
{
HOST_WIDE_INT value;
HOST_WIDE_INT lo, hi;
rtx out;
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), value);
lo = value & 0xffff;
hi = trunc_int_for_mode (value & 0xffff0000, SImode);
out = gen_rtx_REG (SImode, REGNO (operands[0]));
emit_move_insn (out, GEN_INT (hi));
if (lo != 0)
emit_insn (gen_iorsi3 (out, out, GEN_INT (lo)));
DONE;
}")
(define_expand "movdf"
[(set (match_operand:DF 0 "" "")
(match_operand:DF 1 "" ""))]
""
"
{
if (mep_expand_mov (operands, DFmode))
DONE;
}")
(define_insn "*movdf_internal_32"
[(set (match_operand:DF 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
(match_operand:DF 1 "general_operand" "rFm,r,c,r,er,r,ex,U,em"))]
"TARGET_32BIT_CR_REGS && mep_mov_ok (operands, DFmode)"
"#"
[(set_attr "slot" "multi")])
(define_insn "*movdf_internal_64"
[(set (match_operand:DF 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
(match_operand:DF 1 "general_operand" "rFm,r,c,r,er,r,ex,U,em"))]
"TARGET_64BIT_CR_REGS && mep_mov_ok (operands, DFmode)"
"@
#
#
#
#
#
#
%<\\t%0, %M1
lmcp\\t%0, %1
smcp\\t%1, %0"
[(set_attr "slot" "multi,multi,multi,multi,multi,multi,*,*,*")
(set_attr "intrinsic" "*,*,*,*,*,*,cmov,*,*")
(set_attr "memop" "*,*,*,*,*,*,*,cop1,cop0")
(set_attr "stall" "*,*,*,*,*,*,*,load,store")])
(define_split
[(set (match_operand:DF 0 "mep_movdest_operand" "")
(match_operand:DF 1 "general_operand" ""))]
"reload_completed && mep_multi_slot (insn)"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))]
"mep_split_wide_move (operands, DFmode);")
(define_insn "*lbcpa"
[(set (match_operand:SI 0 "register_operand" "=em")
(sign_extend:SI (mem:QI (match_operand:SI 2 "register_operand" "1"))))
(set (match_operand:SI 1 "register_operand" "=r")
(plus:SI (match_dup 2)
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")))]
"TARGET_COP && reload_completed"
"lbcpa\t%0, (%1+), %3"
[(set_attr "length" "4")
(set_attr "stall" "load")])
(define_insn "*sbcpa"
[(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
(match_operand:QI 2 "register_operand" "em"))
(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_dup 1)
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")))]
"TARGET_COP && reload_completed"
"sbcpa\t%2, (%0+), %3"
[(set_attr "length" "4")
(set_attr "stall" "store")])
(define_insn "*lhcpa"
[(set (match_operand:SI 0 "register_operand" "=em")
(sign_extend:SI (mem:HI (match_operand:SI 2 "register_operand" "1"))))
(set (match_operand:SI 1 "register_operand" "=r")
(plus:SI (match_dup 2)
(match_operand:SI 3 "cgen_h_sint_7a2_immediate" "")))]
"TARGET_COP && reload_completed"
"lhcpa\t%0, (%1+), %3"
[(set_attr "length" "4")
(set_attr "stall" "load")])
(define_insn "*shcpa"
[(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
(match_operand:HI 2 "register_operand" "em"))
(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_dup 1)
(match_operand:SI 3 "cgen_h_sint_7a2_immediate" "")))]
"TARGET_COP && reload_completed"
"shcpa\t%2, (%0+), %3"
[(set_attr "length" "4")
(set_attr "stall" "store")])
(define_insn "*lwcpi"
[(set (match_operand:SI 0 "register_operand" "=em")
(mem:SI (match_operand:SI 2 "register_operand" "1")))
(set (match_operand:SI 1 "register_operand" "=r")
(plus:SI (match_dup 2)
(const_int 4)))]
"TARGET_COP && reload_completed"
"lwcpi\t%0, (%1+)"
[(set_attr "length" "2")
(set_attr "stall" "load")])
(define_insn "*lwcpa"
[(set (match_operand:SI 0 "register_operand" "=em")
(mem:SI (match_operand:SI 2 "register_operand" "1")))
(set (match_operand:SI 1 "register_operand" "=r")
(plus:SI (match_dup 2)
(match_operand:SI 3 "cgen_h_sint_6a4_immediate" "")))]
"TARGET_COP && reload_completed"
"lwcpa\t%0, (%1+), %3"
[(set_attr "length" "4")
(set_attr "stall" "load")])
(define_insn "*swcpi"
[(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
(match_operand:SI 2 "register_operand" "em"))
(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_dup 1)
(const_int 4)))]
"TARGET_COP && reload_completed"
"swcpi\t%2, (%0+)"
[(set_attr "length" "2")
(set_attr "stall" "store")])
(define_insn "*swcpa"
[(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
(match_operand:SI 2 "register_operand" "em"))
(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_dup 1)
(match_operand:SI 3 "cgen_h_sint_6a4_immediate" "")))]
"TARGET_COP && reload_completed"
"swcpa\t%2, (%0+), %3"
[(set_attr "length" "4")
(set_attr "stall" "store")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_dup 0)
(match_operand:SI 1 "cgen_h_sint_8a1_immediate" "")))]
"TARGET_COP && mep_use_post_modify_p (insn, operands[0], operands[1])"
[(const_int 0)]
{
emit_note (NOTE_INSN_DELETED);
DONE;
})
;; ::::::::::::::::::::
;; ::
;; :: Reloads
;; ::
;; ::::::::::::::::::::
(define_expand "reload_insi"
[(set (match_operand:SI 0 "mep_reload_operand" "")
(match_operand:SI 1 "mep_reload_operand" "r"))
(clobber (match_operand:SI 2 "register_operand" "=&r"))]
""
"
{
mep_expand_reload (operands, SImode);
DONE;
}")
(define_expand "reload_outsi"
[(set (match_operand:SI 0 "mep_reload_operand" "=r")
(match_operand:SI 1 "mep_reload_operand" ""))
(clobber (match_operand:SI 2 "register_operand" "=&r"))]
""
"
{
mep_expand_reload (operands, SImode);
DONE;
}")
;; ::::::::::::::::::::
;; ::
;; :: Conversions
;; ::
;; ::::::::::::::::::::
(define_insn "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r,em")
(sign_extend:SI
(match_operand:QI 1 "nonimmediate_operand" "0,m,Y")))]
""
"@
extb\\t%0
lb\\t%0, %1
lbcpa\\t%0, %P1"
[(set_attr "length" "2,*,*")
(set_attr "stall" "*,load,load")
(set_attr "memop" "*,core1,cop1")])
(define_insn "extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r,em")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "0,m,Y")))]
""
"@
exth\\t%0
lh\\t%0, %1
lhcpa\\t%0, %P1"
[(set_attr "length" "2,*,*")
(set_attr "stall" "*,load,load")
(set_attr "memop" "*,core1,cop1")])
(define_insn "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(zero_extend:SI
(match_operand:QI 1 "nonimmediate_operand" "0,r,m")))]
""
"@
extub\\t%0
and3\\t%0, %1, 255
lbu\\t%0, %1"
[(set_attr "length" "2,4,*")
(set_attr "stall" "*,*,load")
(set_attr "memop" "*,*,core1")])
(define_insn "zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(zero_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "0,r,m")))]
""
"@
extuh\\t%0
and3\\t%0, %1, 65535
lhu\\t%0, %1"
[(set_attr "length" "2,4,*")
(set_attr "stall" "*,*,load")
(set_attr "memop" "*,*,core1")])
;; ::::::::::::::::::::
;; ::
;; :: 32 bit Integer arithmetic
;; ::
;; ::::::::::::::::::::
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(plus:SI (match_operand:SI 1 "register_operand" "%r,0,r")
(match_operand:SI 2 "mep_add_operand" "r,L,IT")))]
""
"@
add3\\t%0, %1, %2
add\\t%0, %2
add3\\t%0, %1, %I2"
[(set (attr "length")
(if_then_else (eq_attr "alternative" "2")
(if_then_else (and (match_operand:SI 1 "mep_sp_operand" "")
(match_operand:SI 2 "mep_imm7a4_operand" ""))
(const_int 2)
(const_int 4))
(const_int 2)))])
;; The intention here is to combine the 16-bit add with the 16-bit
;; move to create a 32-bit add. It's the same size, but takes one
;; less machine cycle. It will happen to match a 32-bit add with a
;; 16-bit move also, but gcc shouldn't be doing that ;)
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "immediate_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(match_operand:SI 4 "register_operand" ""))]
"REGNO (operands[0]) == REGNO (operands[1])
&& REGNO (operands[0]) == REGNO (operands[4])
&& GR_REGNO_P (REGNO (operands[3]))
&& dead_or_set_p (peep2_next_insn (1), operands[4])"
[(set (match_dup 3)
(plus:SI (match_dup 1)
(match_dup 2)))]
"")
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "register_operand" "r")))]
""
"sub\\t%0, %2"
[(set_attr "length" "2")])
(define_expand "mulsi3"
[(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" "")))]
"TARGET_OPT_MULT || TARGET_COPRO_MULT"
{
emit_insn (gen_mulsi3_1 (operands[0], operands[1], operands[2]));
DONE;
})
;; Generated by mep_reuse_lo_p when no GPR destination is needed.
(define_insn "mulsi3_lo"
[(set (match_operand:SI 0 "mep_lo_operand" "=l")
(mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")))
(clobber (match_scratch:SI 3 "=h"))]
"TARGET_OPT_MULT && reload_completed"
"mul\\t%1, %2"
[(set_attr "length" "2")
(set_attr "stall" "mul")])
;; Generated by mep_reuse_lo_p when both destinations of a mulr
;; are needed.
(define_insn "mulsi3r"
[(set (match_operand:SI 0 "mep_lo_operand" "=l")
(mult:SI (match_operand:SI 2 "register_operand" "1")
(match_operand:SI 3 "register_operand" "r")))
(set (match_operand:SI 1 "register_operand" "=r")
(mult:SI (match_dup 2)
(match_dup 3)))
(clobber (match_scratch:SI 4 "=h"))]
"TARGET_OPT_MULT && reload_completed"
"mulr\\t%2, %3"
[(set_attr "length" "2")
(set_attr "stall" "mulr")])
(define_insn "mulsi3_1"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "register_operand" "r")))
(clobber (match_scratch:SI 3 "=l"))
(clobber (match_scratch:SI 4 "=h"))]
"TARGET_OPT_MULT"
"mulr\\t%1, %2"
[(set_attr "length" "2")
(set_attr "stall" "mulr")])
(define_expand "mulsidi3"
[(set (match_operand:DI 0 "register_operand" "")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
(sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
"TARGET_OPT_MULT"
"
{
rtx hi = gen_reg_rtx (SImode);
rtx lo = gen_reg_rtx (SImode);
emit_insn (gen_mulsidi3_i (hi, lo, operands[1], operands[2]));
emit_move_insn (gen_lowpart (SImode, operands[0]), lo);
emit_move_insn (gen_highpart (SImode, operands[0]), hi);
DONE;
}")
(define_insn "mulsidi3_i"
[(set (match_operand:SI 0 "mep_hi_operand" "=h")
(truncate:SI
(lshiftrt:DI
(mult:DI (sign_extend:DI
(match_operand:SI 2 "register_operand" "r"))
(sign_extend:DI
(match_operand:SI 3 "register_operand" "r")))
(const_int 32))))
(set (match_operand:SI 1 "mep_lo_operand" "=l")
(mult:SI (match_dup 2)
(match_dup 3)))]
"TARGET_OPT_MULT"
"mul\\t%2, %3"
[(set_attr "length" "2")
(set_attr "stall" "mul")])
(define_insn "smulsi3_highpart"
[(set (match_operand:SI 0 "mep_hi_operand" "=h")
(truncate:SI
(lshiftrt:DI
(mult:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "r"))
(sign_extend:DI
(match_operand:SI 2 "register_operand" "r")))
(const_int 32))))
(clobber (reg:SI LO_REGNO))]
"TARGET_OPT_MULT"
"mul\\t%1, %2"
[(set_attr "length" "2")
(set_attr "stall" "mul")])
(define_expand "umulsidi3"
[(set (match_operand:DI 0 "mep_hi_operand" "")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
(zero_extend:DI (match_operand:SI 2 "register_operand" ""))))]
"TARGET_OPT_MULT"
"
{
rtx hi = gen_reg_rtx (SImode);
rtx lo = gen_reg_rtx (SImode);
emit_insn (gen_umulsidi3_i (hi, lo, operands[1], operands[2]));
emit_move_insn (gen_lowpart (SImode, operands[0]), lo);
emit_move_insn (gen_highpart (SImode, operands[0]), hi);
DONE;
}")
(define_insn "umulsidi3_i"
[(set (match_operand:SI 0 "mep_hi_operand" "=h")
(truncate:SI
(lshiftrt:DI
(mult:DI (zero_extend:DI
(match_operand:SI 2 "register_operand" "r"))
(zero_extend:DI
(match_operand:SI 3 "register_operand" "r")))
(const_int 32))))
(set (match_operand:SI 1 "mep_lo_operand" "=l")
(mult:SI (match_dup 2)
(match_dup 3)))]
"TARGET_OPT_MULT"
"mulu\\t%2, %3"
[(set_attr "length" "2")
(set_attr "stall" "mul")])
(define_insn "umulsi3_highpart"
[(set (match_operand:SI 0 "mep_hi_operand" "=h")
(truncate:SI
(lshiftrt:DI
(mult:DI (zero_extend:DI
(match_operand:SI 1 "register_operand" "r"))
(zero_extend:DI
(match_operand:SI 2 "register_operand" "r")))
(const_int 32))))
(clobber (reg:SI LO_REGNO))]
"TARGET_OPT_MULT"
"mulu %1, %2"
[(set_attr "length" "2")
(set_attr "stall" "mul")])
;; These two don't currently match because we don't have an adddi3 pattern.
(define_insn "*smultdi_and_add"
[(set (match_operand:DI 0 "mep_hi_operand" "=d")
(plus:DI (mult:DI (zero_extend:DI
(match_operand:SI 1 "register_operand" "r"))
(zero_extend:DI
(match_operand:SI 2 "register_operand" "r")))
(match_operand:DI 3 "mep_hi_operand" "0")))]
"TARGET_OPT_MULT && TARGET_BIG_ENDIAN"
"maddu\\t%1, %2"
[(set_attr "length" "4")
(set_attr "stall" "mul")])
(define_insn "*umultdi_and_add"
[(set (match_operand:DI 0 "mep_hi_operand" "=d")
(plus:DI (mult:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "r"))
(sign_extend:DI
(match_operand:SI 2 "register_operand" "r")))
(match_operand:DI 3 "mep_hi_operand" "0")))]
"TARGET_OPT_MULT && TARGET_BIG_ENDIAN"
"madd\\t%1, %2"
[(set_attr "length" "4")
(set_attr "stall" "mul")])
;; A pattern for 'r1 = r2 * r3 + r4'. There are three possible
;; implementations:
;;
;; (1) 'mulr;add3'. This is usually the best choice if the instruction
;; is not part of a natural multiply-accumulate chain. It has the
;; same latency as 'stc;maddr' but doesn't tie up $lo for as long.
;;
;; (2) 'madd'. This is the best choice if the instruction is in the
;; middle of a natural multiply-accumulate chain. r4 will already
;; be in $lo and r1 will also be needed in $lo.
;;
;; (3) 'maddr'. This is the best choice if the instruction is at the
;; end of a natural multiply-accumulate chain. r4 will be in $lo
;; but r1 will be needed in a GPR.
;;
;; In theory, we could put all the alternatives into a single pattern and
;; leave the register allocator to choose between them. However, this can
;; sometimes produce poor results in practice.
;;
;; This pattern therefore describes a general GPR-to-GPR operation that
;; has a slight preference for cases in which operands 0 and 1 are tied.
;; After reload, we try to rewrite the patterns using peephole2s (if
;; enabled), falling back on define_splits if that fails. See also
;; mep_reuse_lo_p.
(define_insn "maddsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%0,r")
(match_operand:SI 2 "register_operand" "r,r"))
(match_operand:SI 3 "register_operand" "r,r")))
(clobber (match_scratch:SI 4 "=l,l"))
(clobber (match_scratch:SI 5 "=h,h"))]
"TARGET_OPT_MULT"
"#"
[(set_attr "length" "8")
(set_attr "stall" "mulr")])
;; Implement maddsi3s using maddr if operand 3 is already available in $lo.
(define_peephole2
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" ""))
(match_operand:SI 3 "register_operand" "")))
(clobber (match_scratch:SI 4 ""))
(clobber (match_scratch:SI 5 ""))])]
"TARGET_OPT_MULT
&& reload_completed
&& mep_reuse_lo_p (operands[4], operands[3], insn,
!rtx_equal_p (operands[1], operands[3])
&& !rtx_equal_p (operands[2], operands[3])
&& (rtx_equal_p (operands[0], operands[3])
|| peep2_reg_dead_p (1, operands[3])))"
[(parallel
[(set (match_dup 4)
(plus:SI (mult:SI (match_dup 0)
(match_dup 2))
(match_dup 4)))
(set (match_dup 0)
(plus:SI (mult:SI (match_dup 0)
(match_dup 2))
(match_dup 4)))
(clobber (match_dup 5))])]
"operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);")
;; This splitter implements maddsi3 as "mulr;add3". It only works if
;; operands 0 and 3 are distinct, since operand 0 is clobbered before
;; operand 3 is used.
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" ""))
(match_operand:SI 3 "register_operand" "")))
(clobber (match_scratch:SI 4 ""))
(clobber (match_scratch:SI 5 ""))]
"TARGET_OPT_MULT
&& reload_completed
&& !rtx_equal_p (operands[0], operands[3])"
[(parallel [(set (match_dup 0)
(mult:SI (match_dup 0)
(match_dup 2)))
(clobber (match_dup 4))
(clobber (match_dup 5))])
(set (match_dup 0)
(plus:SI (match_dup 0)
(match_dup 3)))]
"operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);")
;; This is the fallback splitter for maddsi3. It moves operand 3 into
;; $lo and then uses maddr.
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" ""))
(match_operand:SI 3 "register_operand" "")))
(clobber (match_scratch:SI 4 ""))
(clobber (match_scratch:SI 5 ""))]
"TARGET_OPT_MULT
&& reload_completed"
[(parallel [(set (match_dup 4)
(plus:SI (mult:SI (match_dup 0)
(match_dup 2))
(match_dup 4)))
(set (match_dup 0)
(plus:SI (mult:SI (match_dup 0)
(match_dup 2))
(match_dup 4)))
(clobber (match_dup 5))])]
{
emit_move_insn (operands[4], operands[3]);
operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);
})
;; Remove unnecessary stcs to $lo. This cleans up the moves generated
;; by earlier calls to mep_reuse_lo_p.
(define_peephole2
[(set (match_operand:SI 0 "mep_lo_operand" "")
(match_operand:SI 1 "register_operand" ""))]
"TARGET_OPT_MULT
&& mep_reuse_lo_p (operands[0], operands[1], insn,
peep2_reg_dead_p (1, operands[1]))"
[(const_int 0)]
{
emit_note (NOTE_INSN_DELETED);
DONE;
})
(define_insn "maddsi3_lo"
[(set (match_operand:SI 0 "mep_lo_operand" "=l")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 3 "mep_lo_operand" "0")))
(clobber (match_scratch:SI 4 "=h"))]
"TARGET_OPT_MULT && reload_completed"
"madd\\t%1, %2"
[(set_attr "length" "4")
(set_attr "stall" "mul")])
(define_insn "maddsi3r"
[(set (match_operand:SI 0 "mep_lo_operand" "=l")
(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "1")
(match_operand:SI 3 "register_operand" "r"))
(match_operand:SI 4 "register_operand" "0")))
(set (match_operand:SI 1 "register_operand" "=r")
(plus:SI (mult:SI (match_dup 2)
(match_dup 3))
(match_dup 4)))
(clobber (match_scratch:SI 5 "=h"))]
"TARGET_OPT_MULT && reload_completed"
"maddr\\t%2, %3"
[(set_attr "length" "4")
(set_attr "stall" "mulr")])
(define_insn "*shift_1_or_2_and_add"
[(set (match_operand:SI 0 "mep_r0_operand" "=z")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "mep_slad_operand" "n"))
(match_operand:SI 3 "register_operand" "r")))]
""
"sl%b2ad3\\t%0, %1, %3"
[(set_attr "length" "2")
(set_attr "stall" "int2")])
(define_insn "divmodsi4"
[(set (match_operand:SI 0 "mep_lo_operand" "=l")
(div:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")))
(set (match_operand:SI 3 "mep_hi_operand" "=h")
(mod:SI (match_dup 1)
(match_dup 2)))]
"TARGET_OPT_DIV"
"div\\t%1, %2"
[(set_attr "length" "2")
(set_attr "stall" "div")
(set_attr "may_trap" "yes")])
(define_insn "udivmodsi4"
[(set (match_operand:SI 0 "mep_lo_operand" "=l")
(udiv:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")))
(set (match_operand:SI 3 "mep_hi_operand" "=h")
(umod:SI (match_dup 1)
(match_dup 2)))]
"TARGET_OPT_DIV"
"divu\\t%1, %2"
[(set_attr "length" "2")
(set_attr "stall" "div")
(set_attr "may_trap" "yes")])
(define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
""
"neg\\t%0, %1"
[(set_attr "length" "2")])
;; We have "absolute difference between two regs" which isn't quite
;; what gcc is expecting.
(define_expand "abssi2"
[(set (match_dup 2) (const_int 0))
(set (match_operand:SI 0 "register_operand" "")
(abs:SI (minus:SI (match_operand:SI 1 "register_operand" "")
(match_dup 2))
))]
"TARGET_OPT_ABSDIFF"
"operands[2] = gen_reg_rtx (SImode);")
(define_insn "*absdiff"
[(set (match_operand:SI 0 "register_operand" "=r")
(abs:SI (minus:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "register_operand" "r"))))]
"TARGET_OPT_ABSDIFF"
"abs\\t%0, %2"
[(set_attr "length" "4")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(abs:SI (plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))
(clobber (match_operand:SI 3 "register_operand" ""))]
"!reload_completed"
[(set (match_dup 3)
(match_dup 4))
(set (match_operand:SI 0 "register_operand" "")
(abs:SI (minus:SI (match_operand:SI 1 "register_operand" "")
(match_dup 3))))]
"operands[4] = GEN_INT (-INTVAL (operands[2]));")
(define_insn "sminsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(smin:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "r")))]
"TARGET_OPT_MINMAX"
"min\\t%0, %2"
[(set_attr "length" "4")])
(define_insn "smaxsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(smax:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "r")))]
"TARGET_OPT_MINMAX"
"max\\t%0, %2"
[(set_attr "length" "4")])
(define_insn "uminsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(umin:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "r")))]
"TARGET_OPT_MINMAX"
"minu\\t%0, %2"
[(set_attr "length" "4")])
(define_insn "umaxsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(umax:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "r")))]
"TARGET_OPT_MINMAX"
"maxu\\t%0, %2"
[(set_attr "length" "4")])
;; Average: a = (b+c+1)>>1
(define_insn "*averagesi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (plus:SI (plus:SI
(match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "register_operand" "r"))
(const_int 1))
(const_int 1)))]
"TARGET_OPT_AVERAGE"
"ave\\t%0, %2"
[(set_attr "length" "4")])
;; clip support
(define_insn "clip_maxmin"
[(set (match_operand:SI 0 "register_operand" "=r")
(smax:SI (smin:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "immediate_operand" "n"))
(match_operand:SI 3 "immediate_operand" "n")))]
"mep_allow_clip (operands[2], operands[3], 1)"
"clip\\t%0, %B2"
[(set_attr "length" "4")])
(define_insn "clip_minmax"
[(set (match_operand:SI 0 "register_operand" "=r")
(smin:SI (smax:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "immediate_operand" "n"))
(match_operand:SI 3 "immediate_operand" "n")))]
"mep_allow_clip (operands[3], operands[2], 1)"
"clip\\t%0, %B3"
[(set_attr "length" "4")])
(define_insn "clipu_maxmin"
[(set (match_operand:SI 0 "register_operand" "=r")
(smax:SI (smin:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "immediate_operand" "n"))
(match_operand:SI 3 "immediate_operand" "n")))]
"mep_allow_clip (operands[2], operands[3], 0)"
"clipu\\t%0, %U2"
[(set_attr "length" "4")])
(define_insn "clipu_minmax"
[(set (match_operand:SI 0 "register_operand" "=r")
(smin:SI (smax:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "immediate_operand" "n"))
(match_operand:SI 3 "immediate_operand" "n")))]
"mep_allow_clip (operands[3], operands[2], 0)"
"clipu\\t%0, %U3"
[(set_attr "length" "4")])
;; ::::::::::::::::::::
;; ::
;; :: 32 bit Integer Shifts and Rotates
;; ::
;; ::::::::::::::::::::
(define_insn "ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=r,z")
(ashift:SI (match_operand:SI 1 "register_operand" "0,r")
(match_operand:SI 2 "nonmemory_operand" "rM,M")))]
""
"@
sll\\t%0, %2
sll3\\t%0, %1, %2"
[(set_attr "length" "2,2")
(set_attr "shiftop" "operand2")])
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "rM")))]
""
"sra\\t%0, %2"
[(set_attr "length" "2")
(set_attr "shiftop" "operand2")])
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "rM")))]
""
"srl\\t%0, %2"
[(set_attr "length" "2")
(set_attr "shiftop" "operand2")])
;; ::::::::::::::::::::
;; ::
;; :: 32 Bit Integer Logical operations
;; ::
;; ::::::::::::::::::::
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(and:SI (match_operand:SI 1 "register_operand" "%0,r")
(match_operand:SI 2 "nonmemory_operand" "r,J")))]
""
"@
and\\t%0, %2
and3\\t%0, %1, %J2"
[(set_attr "length" "2,4")])
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ior:SI (match_operand:SI 1 "register_operand" "%0,r")
(match_operand:SI 2 "nonmemory_operand" "r,J")))]
""
"@
or\\t%0, %2
or3\\t%0, %1, %J2"
[(set_attr "length" "2,4")])
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(xor:SI (match_operand:SI 1 "register_operand" "%0,r")
(match_operand:SI 2 "nonmemory_operand" "r,J")))]
""
"@
xor\\t%0, %2
xor3\\t%0, %1, %J2"
[(set_attr "length" "2,4")])
(define_expand "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "")
(not:SI (match_operand:SI 1 "register_operand" "")))]
""
"operands[2] = operands[1];
")
;; No separate insn for this; use NOR
(define_insn "*one_cmplsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "0")))]
""
"nor\\t%0, %0"
[(set_attr "length" "2")])
;; ::::::::::::::::::::
;; ::
;; :: Bit Manipulation
;; ::
;; ::::::::::::::::::::
(define_insn "*bitop_be"
[(set (match_operand:QI 0 "mep_Y_operand" "=Y")
(subreg:QI (match_operator:SI 3 "mep_bit_operator"
[(subreg:SI (match_operand:QI 1 "mep_Y_operand" "0") 0)
(match_operand 2 "immediate_operand" "n")])
3)
)]
"TARGET_BIG_ENDIAN && TARGET_OPT_BITOPS
&& rtx_equal_p (operands[0], operands[1])"
"b%L3m\\t%0, %b2"
[(set_attr "length" "2")])
(define_insn "*bitop_le"
[(set (match_operand:QI 0 "mep_Y_operand" "=Y")
(subreg:QI (match_operator:SI 3 "mep_bit_operator"
[(subreg:SI (match_operand:QI 1 "mep_Y_operand" "0") 0)
(match_operand 2 "immediate_operand" "n")])
0)
)]
"!TARGET_BIG_ENDIAN && TARGET_OPT_BITOPS
&& rtx_equal_p (operands[0], operands[1])"
"b%L3m\\t%0, %b2"
[(set_attr "length" "2")])
(define_insn "btstm"
[(set (match_operand:SI 0 "mep_r0_operand" "=z")
(and:SI (subreg:SI (match_operand:QI 1 "mep_Y_operand" "Y") 0)
(match_operand 2 "immediate_operand" "n"))
)]
"TARGET_OPT_BITOPS && mep_bit_position_p (operands[2], 1)"
"btstm\\t%0, %1, %b2"
[(set_attr "length" "2")])
(define_insn "tas"
[(parallel [(set (match_operand:SI 0 "mep_r0_operand" "=z")
(zero_extend:SI (match_operand:QI 1 "mep_Y_operand" "+Y")))
(set (match_dup 1)
(const_int 1))
]
)]
"TARGET_OPT_BITOPS"
"tas\\t%0, %1"
[(set_attr "length" "2")])
(define_peephole2
[(set (match_operand:SI 0 "mep_r0_operand" "")
(zero_extend:SI (match_operand:QI 1 "mep_Y_operand" "")))
(set (match_operand:QI 2 "register_operand" "")
(const_int 1))
(set (match_dup 1)
(match_dup 2))
]
"TARGET_OPT_BITOPS"
[(parallel [(set (match_dup 0)
(zero_extend:SI (match_dup 1)))
(set (match_dup 1)
(const_int 1))
])]
"")
(define_peephole2
[(set (match_operand:SI 0 "mep_r0_operand" "")
(sign_extend:SI (match_operand:QI 1 "mep_Y_operand" "")))
(set (match_operand:QI 2 "register_operand" "")
(const_int 1))
(set (match_dup 1)
(match_dup 2))
]
"TARGET_OPT_BITOPS"
[(parallel [(set (match_dup 0)
(zero_extend:SI (match_dup 1)))
(set (match_dup 1)
(const_int 1))
])
(set (match_dup 0)
(sign_extend:SI (match_dup 3)))]
"operands[3] = gen_lowpart (QImode, operands[0]);")
;; ::::::::::::::::::::
;; ::
;; :: Conditional branches and stores
;; ::
;; ::::::::::::::::::::
(define_expand "cbranchsi4"
[(set (pc)
(if_then_else (match_operator 0 "ordered_comparison_operator"
[(match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "nonmemory_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
"emit_jump_insn (gen_branch_true (operands[3],
mep_expand_cbranch (operands)));
DONE;")
(define_expand "branch_true"
[(set (pc)
(if_then_else (match_operand 1 "" "")
(label_ref (match_operand 0 "" ""))
(pc)))]
""
"")
(define_expand "cstoresi4"
[(set (match_operand:SI 0 "register_operand" "")
(match_operator:SI 1 "ordered_comparison_operator"
[(match_operand:SI 2 "register_operand" "")
(match_operand:SI 3 "nonmemory_operand" "")]))]
""
"if (mep_expand_setcc (operands)) DONE; else FAIL;")
;; ------------------------------------------------------------
(define_insn "*slt"
[(set (match_operand:SI 0 "register_operand" "=z,z,r")
(lt:SI (match_operand:SI 1 "register_operand" "r,r,r")
(match_operand:SI 2 "nonmemory_operand" "r,M,I")))]
""
"slt3\\t%0, %1, %2"
[(set_attr "length" "2,2,4")])
(define_insn "*sltu"
[(set (match_operand:SI 0 "register_operand" "=z,z,r")
(ltu:SI (match_operand:SI 1 "register_operand" "r,r,r")
(match_operand:SI 2 "nonmemory_operand" "r,M,J")))]
""
"sltu3\\t%0, %1, %2"
[(set_attr "length" "2,2,4")])
(define_insn "*bcpeq_true"
[(set (pc)
(if_then_else (eq:SI (reg:SI CBCR_REGNO)
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
""
"bcpeq\t0, %l0"
[(set_attr "length" "4")])
(define_insn "*bcpeq_false"
[(set (pc)
(if_then_else (eq:SI (reg:SI CBCR_REGNO)
(const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))]
""
"bcpne\t0, %l0"
[(set_attr "length" "4")])
(define_insn "*bcpne_true"
[(set (pc)
(if_then_else (ne:SI (reg:SI CBCR_REGNO)
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
""
"bcpne\t0, %l0"
[(set_attr "length" "4")])
(define_insn "*bcpne_false"
[(set (pc)
(if_then_else (ne:SI (reg:SI CBCR_REGNO)
(const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))]
""
"bcpeq\t0, %l0"
[(set_attr "length" "4")])
;; ??? The lengths here aren't correct, since no attempt it made to
;; find "beqz" in the 256-byte range. However, this should not affect
;; bundling, since we never run core branches in parallel.
(define_insn "mep_beq_true"
[(set (pc)
(if_then_else (eq (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"* return mep_emit_cbranch (operands, 0);"
[(set_attr "length" "4")] )
(define_insn "*beq_false"
[(set (pc)
(if_then_else (eq (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
(pc)
(label_ref (match_operand 2 "" ""))))]
""
"* return mep_emit_cbranch (operands, 1);"
[(set_attr "length" "4")])
(define_insn "mep_bne_true"
[(set (pc)
(if_then_else (ne (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"* return mep_emit_cbranch (operands, 1); "
[(set_attr "length" "4")])
(define_insn "*bne_false"
[(set (pc)
(if_then_else (ne (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
(pc)
(label_ref (match_operand 2 "" ""))))]
""
"* return mep_emit_cbranch (operands, 0); "
[(set_attr "length" "4")])
(define_insn "mep_blti"
[(set (pc)
(if_then_else (lt (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "mep_imm4_operand" "N"))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"blti\\t%0, %1, %l2"
[(set_attr "length" "4")])
(define_insn "*bgei"
[(set (pc)
(if_then_else (ge (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "mep_imm4_operand" "N"))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"bgei\\t%0, %1, %l2"
[(set_attr "length" "4")])
;; ::::::::::::::::::::
;; ::
;; :: Call and branch instructions
;; ::
;; ::::::::::::::::::::
(define_expand "call"
[(parallel [(call (match_operand:QI 0 "" "")
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "" ""))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
])]
""
"
{
mep_expand_call (operands, 0);
DONE;
}")
(define_insn "call_internal"
[(call (mem (match_operand:SI 0 "mep_call_address_operand" "R,r"))
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "const_int_operand" ""))
(use (match_operand:SI 3 "mep_tp_operand" "b,b"))
(use (match_operand:SI 4 "mep_gp_operand" "v,v"))
(clobber (reg:SI LP_REGNO))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
]
""
{
static char const pattern[2][2][8] =
{
{ "bsrv\t%0", "jsrv\t%0" },
{ "bsr\t%0", "jsr\t%0" }
};
return pattern[mep_vliw_mode_match (operands[2])][which_alternative];
}
[(set_attr "length" "4,2")])
(define_expand "sibcall"
[(parallel [(call (match_operand:QI 0 "" "")
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "" ""))
(use (reg:SI LP_REGNO))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
])]
""
"")
(define_insn "*sibcall_internal"
[(call (mem (match_operand:SI 0 "mep_nearsym_operand" "s"))
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "const_int_operand" ""))
(use (reg:SI LP_REGNO))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
]
"SIBLING_CALL_P (insn)"
{
if (mep_vliw_jmp_match (operands[2]))
return "jmp\t%0";
else if (mep_vliw_mode_match (operands[2]))
return
"movu $0, %0\n\
jmp $0";
else
return
"ldc $12, $lp\n\
movh $11, %%hi(%0)\n\
xor3 $12, $12, 1\n\
add3 $11, $11, %%lo(%0+1)\n\
stc $12, $lp\n\
jmp $11";
}
[(set_attr "length" "48")
(set_attr "slot" "multi")])
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand:QI 1 "" "")
(match_operand:SI 2 "" "")))
(use (match_operand:SI 3 "" ""))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
])]
""
"
{
mep_expand_call (operands, 1);
DONE;
}")
(define_insn "call_value_internal"
[(set (match_operand 0 "register_operand" "=rx,rx")
(call (mem:SI (match_operand:SI 1 "mep_call_address_operand" "R,r"))
(match_operand:SI 2 "" "")))
(use (match_operand:SI 3 "const_int_operand" ""))
(use (match_operand:SI 4 "mep_tp_operand" "b,b"))
(use (match_operand:SI 5 "mep_gp_operand" "v,v"))
(clobber (reg:SI LP_REGNO))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
]
""
{
static char const pattern[2][2][8] =
{
{ "bsrv\t%1", "jsrv\t%1" },
{ "bsr\t%1", "jsr\t%1" }
};
return pattern[mep_vliw_mode_match (operands[3])][which_alternative];
}
[(set_attr "length" "4,2")])
(define_expand "sibcall_value"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand:QI 1 "" "")
(match_operand:SI 2 "" "")))
(use (match_operand:SI 3 "" ""))
(use (reg:SI LP_REGNO))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
])]
""
"")
(define_insn "*sibcall_value_internal"
[(set (match_operand 0 "register_operand" "=rx")
(call (mem (match_operand:SI 1 "mep_nearsym_operand" "s"))
(match_operand:SI 2 "" "")))
(use (match_operand:SI 3 "const_int_operand" ""))
(use (reg:SI LP_REGNO))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
]
"SIBLING_CALL_P (insn)"
{
if (mep_vliw_jmp_match (operands[3]))
return "jmp\t%1";
else if (mep_vliw_mode_match (operands[3]))
return
"movu $0, %1\n\
jmp $0";
else
return
"ldc $12, $lp\n\
movh $11, %%hi(%1)\n\
xor3 $12, $12, 1\n\
add3 $11, $11, %%lo(%1+1)\n\
stc $12, $lp\n\
jmp $11";
}
[(set_attr "length" "48")
(set_attr "slot" "multi")])
(define_insn "return_internal"
[(return)
(use (match_operand:SI 0 "register_operand" ""))]
""
"* return (REGNO (operands[0]) == LP_REGNO) ? \"ret\" : \"jmp\\t%0\";"
[(set_attr "length" "2")
(set_attr "stall" "ret")])
(define_insn "eh_return_internal"
[(return)
(use (reg:SI 10))
(use (reg:SI 11))
(use (reg:SI LP_REGNO))
(clobber (reg:SI REGSAVE_CONTROL_TEMP))
]
""
"ret"
[(set_attr "length" "2")
(set_attr "stall" "ret")])
;; The assembler replaces short jumps with long jumps as needed.
(define_insn "jump"
[(set (pc) (label_ref (match_operand 0 "" "")))]
""
"bra\\t%l0"
[(set_attr "length" "4")])
(define_insn "indirect_jump"
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
""
"jmp\\t%0"
[(set_attr "length" "2")])
(define_insn "tablejump"
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
(use (label_ref (match_operand 1 "" "")))]
""
"jmp\\t%0"
[(set_attr "length" "2")])
;; ::::::::::::::::::::
;; ::
;; :: Low Overhead Looping
;; ::
;; ::::::::::::::::::::
;; This insn is volatile because we'd like it to stay in its original
;; position, just before the loop header. If it stays there, we might
;; be able to convert it into a "repeat" insn.
(define_insn "doloop_begin_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI
[(match_operand:SI 1 "register_operand" "0")
(match_operand 2 "const_int_operand" "")] UNS_REPEAT_BEG))]
""
{ gcc_unreachable (); }
[(set_attr "length" "4")])
(define_expand "doloop_begin"
[(use (match_operand 0 "register_operand" ""))
(use (match_operand 1 "" ""))]
"!profile_arc_flag && TARGET_OPT_REPEAT"
"mep_emit_doloop (operands, 0);
DONE;
")
(define_insn "doloop_end_internal"
[(set (pc)
(if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+r,cxy,*m")
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))
(unspec [(match_operand 2 "const_int_operand" "")] UNS_REPEAT_END)
(clobber (match_scratch:SI 3 "=X,&r,&r"))]
""
{ gcc_unreachable (); }
;; Worst case length:
;;
;; lw <op3>,<op0> 4
;; add <op3>,-1 2
;; sw <op3>,<op0> 4
;; jmp <op1> 4
;; 1f:
[(set_attr "length" "14")
(set_attr "slot" "multi")])
(define_expand "doloop_end"
[(use (match_operand 0 "nonimmediate_operand" ""))
(use (label_ref (match_operand 1 "" "")))]
"!profile_arc_flag && TARGET_OPT_REPEAT"
"if (GET_CODE (operands[0]) == REG && GET_MODE (operands[0]) != SImode)
FAIL;
mep_emit_doloop (operands, 1);
DONE;
")
(define_insn "repeat"
[(set (reg:SI RPC_REGNO)
(unspec:SI [(match_operand:SI 0 "mep_r0_15_operand" "r")
(match_operand:SI 1 "" "")]
UNS_REPEAT_BEG))]
""
"repeat\\t%0,%l1"
[(set_attr "length" "4")])
(define_insn "repeat_end"
[(unspec [(const_int 0)] UNS_REPEAT_END)]
""
"# repeat end"
[(set_attr "length" "0")])
(define_insn "erepeat"
[(unspec [(match_operand 0 "" "")] UNS_EREPEAT_BEG)]
""
"erepeat\\t%l0"
[(set_attr "length" "4")])
(define_insn "erepeat_end"
[(unspec [(const_int 0)] UNS_EREPEAT_END)]
""
"# erepeat end"
[(set_attr "length" "0")
(set_attr "slot" "multi")])
;; ::::::::::::::::::::
;; ::
;; :: Prologue and Epilogue instructions
;; ::
;; ::::::::::::::::::::
(define_expand "prologue"
[(const_int 1)]
""
"
{
mep_expand_prologue ();
DONE;
}")
(define_expand "epilogue"
[(return)]
""
"
{
mep_expand_epilogue ();
DONE;
}")
(define_expand "eh_return"
[(use (match_operand:SI 0 "register_operand" "r"))]
""
"
{
mep_expand_eh_return (operands);
DONE;
}")
(define_insn_and_split "eh_epilogue"
[(unspec [(match_operand:SI 0 "register_operand" "r")] UNS_EH_EPILOGUE)
(use (reg:SI LP_REGNO))]
""
"#"
"epilogue_completed"
[(const_int 1)]
"mep_emit_eh_epilogue (operands); DONE;"
[(set_attr "slot" "multi")])
(define_expand "sibcall_epilogue"
[(const_int 0)]
""
"
{
mep_expand_sibcall_epilogue ();
DONE;
}")
(define_insn "mep_bb_trace_ret"
[(unspec_volatile [(const_int 0)] UNS_BB_TRACE_RET)]
""
"* return mep_emit_bb_trace_ret ();"
[(set_attr "slot" "multi")])
(define_insn "mep_disable_int"
[(unspec_volatile [(const_int 0)] UNS_DISABLE_INT)]
""
"di"
[(set_attr "length" "2")])
(define_insn "mep_enable_int"
[(unspec_volatile [(const_int 0)] UNS_ENABLE_INT)]
""
"ei"
[(set_attr "length" "2")])
(define_insn "mep_reti"
[(return)
(unspec_volatile [(const_int 0)] UNS_RETI)]
""
"reti"
[(set_attr "length" "2")])
;; ::::::::::::::::::::
;; ::
;; :: Miscellaneous instructions
;; ::
;; ::::::::::::::::::::
(define_insn "nop"
[(const_int 0)]
""
"nop"
[(set_attr "length" "2")])
(define_insn "nop32"
[(const_int 1)]
""
"or3\\t$0, $0, 0"
[(set_attr "length" "4")])
(define_insn "blockage"
[(unspec_volatile [(const_int 0)] UNS_BLOCKAGE)]
""
""
[(set_attr "length" "0")
(set_attr "slot" "multi")])
(define_insn "djmark"
[(unspec_volatile [(const_int 0)] 999)]
""
"# dj"
[(set_attr "length" "0")
(set_attr "slot" "multi")])
gcc/config/mep/mep.opt deleted 100644 → 0
; Target specific command line options for the MEP port of the compiler.
; Copyright (C) 2005-2016 Free Software Foundation, Inc.
; Contributed by Red Hat Inc.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>. */
Mask(IVC2)
mabsdiff
Target Mask(OPT_ABSDIFF)
Enable absolute difference instructions.
mall-opts
Target RejectNegative
Enable all optional instructions.
maverage
Target Mask(OPT_AVERAGE)
Enable average instructions.
mbased=
Target Joined Var(mep_based_cutoff) RejectNegative UInteger Init(0)
Variables this size and smaller go in the based section. (default 0).
mbitops
Target Mask(OPT_BITOPS)
Enable bit manipulation instructions.
mc=
Target Joined Var(mep_const_section) RejectNegative
Section to put all const variables in (tiny, near, far) (no default).
mclip
Target Mask(OPT_CLIP)
Enable clip instructions.
mconfig=
Target Joined Var(mep_config_string) RejectNegative
Configuration name.
mcop
Target Mask(COP)
Enable MeP Coprocessor.
mcop32
Target Mask(COP) RejectNegative
Enable MeP Coprocessor with 32-bit registers.
mcop64
Target Mask(64BIT_CR_REGS) RejectNegative
Enable MeP Coprocessor with 64-bit registers.
mivc2
Target RejectNegative Var(mep_deferred_options) Defer
Enable IVC2 scheduling.
mdc
Target Mask(DC) RejectNegative
Const variables default to the near section.
mdebug
Target Disabled Undocumented
mdiv
Target Mask(OPT_DIV)
Enable 32-bit divide instructions.
meb
Target InverseMask(LITTLE_ENDIAN) RejectNegative
Use big-endian byte order.
mel
Target Mask(LITTLE_ENDIAN) RejectNegative
Use little-endian byte order.
mfar
Driver RejectNegative
mio-volatile
Target Mask(IO_VOLATILE)
__io vars are volatile by default.
ml
Target Mask(L) RejectNegative
All variables default to the far section.
mleadz
Target Mask(OPT_LEADZ)
Enable leading zero instructions.
mlibrary
Target Mask(LIBRARY) RejectNegative Undocumented
mm
Target Mask(M) RejectNegative
All variables default to the near section.
mminmax
Target Mask(OPT_MINMAX)
Enable min/max instructions.
mmult
Target Mask(OPT_MULT)
Enable 32-bit multiply instructions.
mno-opts
Target RejectNegative
Disable all optional instructions.
mrand-tpgp
Target Mask(RAND_TPGP) RejectNegative Undocumented
mrepeat
Target Mask(OPT_REPEAT)
Allow gcc to use the repeat/erepeat instructions.
ms
Target Mask(S) RejectNegative
All variables default to the tiny section.
msatur
Target Mask(OPT_SATUR)
Enable saturation instructions.
msdram
Target
Use sdram version of runtime.
msim
Target RejectNegative
Use simulator runtime.
msimnovec
Target RejectNegative
Use simulator runtime without vectors.
mtf
Target Mask(TF) RejectNegative
All functions default to the far section.
mtiny=
Target Joined Var(mep_tiny_cutoff) RejectNegative UInteger Init(4)
Variables this size and smaller go in the tiny section. (default 4).
mvl32
Target InverseMask(OPT_VL64) Undocumented RejectNegative
mvl64
Target Mask(OPT_VL64) Undocumented RejectNegative
mvliw
Target Mask(VLIW) Undocumented
gcc/config/mep/predicates.md deleted 100644 → 0
;; Toshiba Media Processor Machine predicates
;; Copyright (C) 2009-2016 Free Software Foundation, Inc.
;; Contributed by Red Hat Inc.
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
;; (define_predicate "cgen_h_uint_7a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_6a2_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_22a4_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_sint_2a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_24a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_sint_6a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_5a4_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_2a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_16a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_3a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_5a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_sint_16a1_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_sint_5a8_immediate"
;; (match_code "const_int"))
;; (define_predicate "cgen_h_uint_4a1_immediate"
;; (match_code "const_int"))
(define_predicate "cgen_h_sint_7a2_immediate"
(match_code "const_int")
{ int i = INTVAL (op);
return ((i & 1) == 0 && i >= -128 && i < 128);
})
(define_predicate "cgen_h_sint_6a4_immediate"
(match_code "const_int")
{ int i = INTVAL (op);
return ((i & 3) == 0 && i >= -256 && i < 256);
})
;; This is used below, to simplify things.
(define_predicate "mep_subreg_operand"
(ior
(and (and (and (match_code "subreg")
(match_code "reg" "0"))
(match_test "REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER"))
(match_test "!(reload_completed || reload_in_progress)"))
(and (match_code "reg")
(match_test "REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
(define_predicate "symbolic_operand"
(match_code "const,symbol_ref,label_ref"))
(define_predicate "mep_farsym_operand"
(and (match_code "const,symbol_ref")
(match_test "mep_section_tag (op) == 'f'")))
(define_predicate "mep_nearsym_operand"
(and (match_code "const,symbol_ref,label_ref")
(match_test "mep_section_tag (op) != 'f'")))
(define_predicate "mep_movdest_operand"
(and (match_test "mep_section_tag (op) != 'f'")
(match_operand 0 "nonimmediate_operand")))
(define_predicate "mep_r0_15_operand"
(ior (match_operand 0 "mep_subreg_operand")
(and (match_code "reg")
(match_test "GR_REGNO_P (REGNO (op))"))))
(define_predicate "mep_r0_operand"
(and (match_code "reg")
(ior (match_test "REGNO (op) == 0")
(match_test "!(reload_completed || reload_in_progress)
&& REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
(define_predicate "mep_hi_operand"
(ior (match_operand 0 "mep_subreg_operand")
(and (match_code "reg")
(match_test "REGNO (op) == HI_REGNO"))))
(define_predicate "mep_lo_operand"
(ior (match_operand 0 "mep_subreg_operand")
(and (match_code "reg")
(match_test "REGNO (op) == LO_REGNO"))))
(define_predicate "mep_tp_operand"
(ior (match_operand 0 "mep_subreg_operand")
(and (match_code "reg")
(match_test "REGNO (op) == TP_REGNO"))))
(define_predicate "mep_gp_operand"
(ior (match_operand 0 "mep_subreg_operand")
(and (match_code "reg")
(match_test "REGNO (op) == GP_REGNO"))))
(define_predicate "mep_sp_operand"
(match_test "op == stack_pointer_rtx"))
(define_predicate "mep_tprel_operand"
(ior (match_operand 0 "mep_subreg_operand")
(and (match_code "reg")
(match_test "REGNO (op) < 8"))))
(define_predicate "mep_call_address_operand"
(and (match_test "mep_section_tag (op) != 'f'")
(and (ior (not (match_code "symbol_ref"))
(match_test "mep_section_tag (DECL_RTL (cfun->decl)) != 'f'
&& !mep_lookup_pragma_call (XSTR (op, 0))"))
(match_code "symbol_ref,reg"))))
(define_predicate "mep_Y_operand"
(and (match_code "mem")
(match_code "reg" "0")))
(define_predicate "mep_imm4_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
(define_predicate "mep_reg_or_imm4_operand"
(ior (match_code "reg")
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15"))))
(define_predicate "mep_imm7a4_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) < 128 && INTVAL (op) % 4 == 0")))
(define_predicate "mep_slad_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) == 2 || INTVAL (op) == 4")))
(define_predicate "mep_add_operand"
(ior (and (match_code "const")
(and (match_operand 0 "symbolic_operand")
(and (match_test "mep_section_tag(op) == 'b' || mep_section_tag(op) == 't'")
(ior (match_code "unspec" "0")
(and (match_code "plus" "0")
(match_code "unspec" "00"))))))
(match_code "const_int,reg")))
;; Return true if OP is an integer in the range 0..7 inclusive.
;; On the MeP-h1, shifts by such constants execute in a single stage
;; and shifts by larger values execute in two.
(define_predicate "mep_single_shift_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
;; Return true if OP is an operation that can be performed using bsetm,
;; bclrm or bnotm. The possibilities are:
;; bsetm: (ior X Y), Y has one bit set
;; bclrm: (and X Y), Y has one bit clear
;; bnotm: (xor X Y), Y has one bit set.
(define_predicate "mep_bit_operator"
(and (match_code "and,ior,xor")
(match_test "mep_bit_position_p (XEXP (op, 1), GET_CODE (op) != AND)")))
(define_predicate "mep_reload_operand"
(ior (and (match_code "reg")
(match_test "!ANY_CONTROL_REGNO_P (REGNO (op))"))
(and (match_code "mem,symbol_ref")
(match_test "mep_section_tag (op) != 'f'"))))
gcc/config/mep/t-mep deleted 100644 → 0
# -*- makefile -*-
# GCC makefile fragment for MeP
# Copyright (C) 2001-2016 Free Software Foundation, Inc.
# Contributed by Red Hat Inc
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>. */
# Force genpreds to be rebuilt in case MeP-Integrator changed the predicates
GTM_H = tm.h $(tm_file_list) $(srcdir)/config/mep/mep-intrin.h insn-constants.h
TCFLAGS = -mlibrary
mep-pragma.o: $(srcdir)/config/mep/mep-pragma.c $(CONFIG_H) $(SYSTEM_H) \
coretypes.h $(TM_H) $(TREE_H) $(RTL_H) $(C_PRAGMA_H) \
$(CPPLIB_H) hard-reg-set.h output.h $(srcdir)/config/mep/mep-protos.h \
function.h insn-config.h reload.h $(TARGET_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
MULTILIB_OPTIONS = mel mall-opts mfar
MULTILIB_DIRNAMES = el allopt far
MD_INCLUDES = \
$(srcdir)/config/mep/intrinsics.md \
$(srcdir)/config/mep/predicates.md \
$(srcdir)/config/mep/constraints.md
mep.o : $(srcdir)/config/mep/mep-intrin.h dumpfile.h
# begin-isas
MEP_CORE = ext_core1
MEP_COPRO = ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64
# end-isas
# To use this, you must have cgen and cgen/cpu in the same source tree as
# gcc.
cgen-maint :
S=`cd $(srcdir); pwd`; \
cd $$S/config/mep && \
guile -s $$S/../cgen/cgen-intrinsics.scm \
-s $$S/../cgen \
$(CGENFLAGS) \
-a $$S/../cgen/cpu/mep.cpu \
-m mep,c5 \
-i mep,$(MEP_CORE),$(MEP_COPRO) \
-K mep,$(MEP_CORE),$(MEP_COPRO) \
-M intrinsics.md \
-N mep-intrin.h \
-P intrinsics.h
# start-extra-headers
EXTRA_HEADERS = $(srcdir)/config/mep/intrinsics.h \
$(srcdir)/config/mep/default.h
# end-extra-headers
gcc/doc/install.texi
......@@ -3338,8 +3338,6 @@ information have to.
@item
@uref{#m68k-uclinux,,m68k-uclinux}
@item
@uref{#mep-x-elf,,mep-*-elf}
@item
@uref{#microblaze-x-elf,,microblaze-*-elf}
@item
@uref{#mips-x-x,,mips-*-*}
......@@ -4243,14 +4241,6 @@ both of which were ABI changes.
@html
<hr />
@end html
@anchor{mep-x-elf}
@heading mep-*-elf
Toshiba Media embedded Processor.
This configuration is intended for embedded systems.
@html
<hr />
@end html
@anchor{microblaze-x-elf}
@heading microblaze-*-elf
Xilinx MicroBlaze processor.
......
gcc/doc/md.texi
......@@ -2569,107 +2569,6 @@ Memory addressed using the small base register ($sb).
$r1h
@end table
@item MeP---@file{config/mep/constraints.md}
@table @code
@item a
The $sp register.
@item b
The $tp register.
@item c
Any control register.
@item d
Either the $hi or the $lo register.
@item em
Coprocessor registers that can be directly loaded ($c0-$c15).
@item ex
Coprocessor registers that can be moved to each other.
@item er
Coprocessor registers that can be moved to core registers.
@item h
The $hi register.
@item j
The $rpc register.
@item l
The $lo register.
@item t
Registers which can be used in $tp-relative addressing.
@item v
The $gp register.
@item x
The coprocessor registers.
@item y
The coprocessor control registers.
@item z
The $0 register.
@item A
User-defined register set A.
@item B
User-defined register set B.
@item C
User-defined register set C.
@item D
User-defined register set D.
@item I
Offsets for $gp-rel addressing.
@item J
Constants that can be used directly with boolean insns.
@item K
Constants that can be moved directly to registers.
@item L
Small constants that can be added to registers.
@item M
Long shift counts.
@item N
Small constants that can be compared to registers.
@item O
Constants that can be loaded into the top half of registers.
@item S
Signed 8-bit immediates.
@item T
Symbols encoded for $tp-rel or $gp-rel addressing.
@item U
Non-constant addresses for loading/saving coprocessor registers.
@item W
The top half of a symbol's value.
@item Y
A register indirect address without offset.
@item Z
Symbolic references to the control bus.
@end table
@item MicroBlaze---@file{config/microblaze/constraints.md}
@table @code
@item d
......
gcc/testsuite/ChangeLog
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* gcc.dg/tree-ssa/forwprop-28.c: Remove mep-* support.
* gcc.dg/tree-ssa/reassoc-32.c: Likewise.
* gcc.dg/tree-ssa/reassoc-33.c: Likewise.
* gcc.dg/tree-ssa/reassoc-34.c: Likewise.
* gcc.dg/tree-ssa/reassoc-35.c: Likewise.
* gcc.dg/tree-ssa/reassoc-36.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-2.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-3.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c: Likewise.
* gcc.dg/tree-ssa/ssa-thread-11.c: Likewise.
* gcc.dg/tree-ssa/vrp87.c: Likewise.
* lib/target-supports.exp: Likewise.
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* gcc.dg/attr-ms_struct-1.c: Stop testing interix.
* gcc.dg/attr-ms_struct-2.c: Likewise.
* gcc.dg/attr-ms_struct-packed1.c: Likewise.
......
gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c
/* Setting LOGICAL_OP_NON_SHORT_CIRCUIT to 0 leads to two conditional jumps
when evaluating an && condition. VRP is not able to optimize this. */
/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* } } } } } */
/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* } } } } } */
/* { dg-options "-O2 -fdump-tree-forwprop1-details" } */
extern char *frob (void);
......
gcc/testsuite/gcc.dg/tree-ssa/reassoc-32.c
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-options "-O2 -g -fdump-tree-optimized" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-2.c
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-options "-O2 -g -fdump-tree-optimized" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-3.c
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-options "-O2 -g -fdump-tree-optimized" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-options "-O2 -g -fdump-tree-optimized" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-options "-O2 -g -fdump-tree-optimized" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-do compile { target { ! { { logical_op_short_circuit && { ! avr-*-* } } || { m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* mips*-*-* } } } } } */
/* { dg-options "-O2 -g -fdump-tree-optimized" } */
/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* s390*-*-* i?86-*-* x86_64-*-* } } */
......
gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-11.c
/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* m32c*-*-* fr30*-*-* mcore*-*-* frv-*-* h8300-*-* m32r-*-* mn10300-*-* msp430-*-* pdp11-*-* rl78-*-* rx-*-* vax-*-*} } } } } */
/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-* bfin*-*-* v850*-*-* moxie*-*-* m32c*-*-* fr30*-*-* mcore*-*-* frv-*-* h8300-*-* m32r-*-* mn10300-*-* msp430-*-* pdp11-*-* rl78-*-* rx-*-* vax-*-*} } } } } */
/* { dg-options "-O2 -fdump-tree-vrp2-details" } */
/* { dg-final { scan-tree-dump-not "IRREDUCIBLE_LOOP" "vrp2" } } */
......
gcc/testsuite/gcc.dg/tree-ssa/vrp87.c
/* Setting LOGICAL_OP_NON_SHORT_CIRCUIT to 0 leads to two conditional jumps
when evaluating an && condition. */
/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* } } } } } */
/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* } } } } } */
/* { dg-options "-O2 -fdump-tree-fre1-details" } */
......
gcc/testsuite/lib/target-supports.exp
......@@ -575,7 +575,6 @@ proc check_profiling_available { test_what } {
|| [istarget m32c-*-elf]
|| [istarget m68k-*-elf]
|| [istarget m68k-*-uclinux*]
|| [istarget mep-*-elf]
|| [istarget mips*-*-elf*]
|| [istarget mmix-*-*]
|| [istarget mn10300-*-elf*]
......
libgcc/ChangeLog
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* config.host: Remove support for mep-*.
* config/mep/lib1funcs.S: Remove.
* config/mep/lib2funcs.c: Remove.
* config/mep/t-mep: Remove.
* config/mep/tramp.c: Remove.
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* config.host: Remove support for avr-rtems.
* config/avr/t-rtems: Remove.
......
libgcc/config.host
......@@ -136,8 +136,6 @@ m32r*-*-*)
;;
m68k-*-*)
;;
mep*-*-*)
;;
microblaze*-*-*)
cpu_type=microblaze
;;
......@@ -1296,10 +1294,6 @@ am33_2.0-*-linux*)
m32c-*-elf*|m32c-*-rtems*)
tmake_file="$tmake_file m32c/t-m32c"
;;
mep*-*-*)
tmake_file="mep/t-mep t-fdpbit"
extra_parts="crtbegin.o crtend.o"
;;
nvptx-*)
tmake_file="$tmake_file nvptx/t-nvptx"
extra_parts="crt0.o"
......
libgcc/config/mep/lib1funcs.S deleted 100644 → 0
/* libgcc routines for Toshiba Media Processor.
Copyright (C) 2001-2016 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3 of the License, or (at your
option) any later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#define SAVEALL \
add3 $sp, $sp, -16*4 ; \
sw $0, ($sp) ; \
sw $1, 4($sp) ; \
sw $2, 8($sp) ; \
sw $3, 12($sp) ; \
sw $4, 16($sp) ; \
sw $5, 20($sp) ; \
sw $6, 24($sp) ; \
sw $7, 28($sp) ; \
sw $8, 32($sp) ; \
sw $9, 36($sp) ; \
sw $10, 40($sp) ; \
sw $11, 44($sp) ; \
sw $12, 48($sp) ; \
sw $13, 52($sp) ; \
sw $14, 56($sp) ; \
ldc $5, $lp ; \
add $5, 3 ; \
mov $6, -4 ; \
and $5, $6
#define RESTOREALL \
stc $5, $lp ; \
lw $14, 56($sp) ; \
lw $13, 52($sp) ; \
lw $12, 48($sp) ; \
lw $11, 44($sp) ; \
lw $10, 40($sp) ; \
lw $9, 36($sp) ; \
lw $8, 32($sp) ; \
lw $7, 28($sp) ; \
lw $6, 24($sp) ; \
lw $5, 20($sp) ; \
lw $4, 16($sp) ; \
lw $3, 12($sp) ; \
lw $2, 8($sp) ; \
lw $1, 4($sp) ; \
lw $0, ($sp) ; \
add3 $sp, $sp, 16*4 ; \
ret
#ifdef L_mep_profile
.text
.global __mep_mcount
__mep_mcount:
SAVEALL
ldc $1, $lp
mov $2, $0
bsr __mep_mcount_2
RESTOREALL
#endif
#ifdef L_mep_bb_init_trace
.text
.global __mep_bb_init_trace_func
__mep_bb_init_trace_func:
SAVEALL
lw $1, ($5)
lw $2, 4($5)
add $5, 8
bsr __bb_init_trace_func
RESTOREALL
#endif
#ifdef L_mep_bb_init
.text
.global __mep_bb_init_func
__mep_bb_init_func:
SAVEALL
lw $1, ($5)
add $5, 4
bsr __bb_init_func
RESTOREALL
#endif
#ifdef L_mep_bb_trace
.text
.global __mep_bb_trace_func
__mep_bb_trace_func:
SAVEALL
movu $3, __bb
lw $1, ($5)
sw $1, ($3)
lw $2, 4($5)
sw $2, 4($3)
add $5, 8
bsr __bb_trace_func
RESTOREALL
#endif
#ifdef L_mep_bb_increment
.text
.global __mep_bb_increment_func
__mep_bb_increment_func:
SAVEALL
lw $1, ($5)
lw $0, ($1)
add $0, 1
sw $0, ($1)
add $5, 4
RESTOREALL
#endif
libgcc/config/mep/lib2funcs.c deleted 100644 → 0
/* libgcc routines for MeP.
Copyright (C) 2001-2016 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3 of the License, or (at your
option) any later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int word_type __attribute__ ((mode (__word__)));
USItype
__mulsi3 (USItype a, USItype b)
{
USItype c = 0;
while (a != 0)
{
if (a & 1)
c += b;
a >>= 1;
b <<= 1;
}
return c;
}
USItype
udivmodsi4(USItype num, USItype den, word_type modwanted)
{
USItype bit = 1;
USItype res = 0;
while (den < num && bit && !(den & (1L<<31)))
{
den <<=1;
bit <<=1;
}
while (bit)
{
if (num >= den)
{
num -= den;
res |= bit;
}
bit >>=1;
den >>=1;
}
if (modwanted) return num;
return res;
}
SItype
__divsi3 (SItype a, SItype b)
{
word_type neg = 0;
SItype res;
if (a < 0)
{
a = -a;
neg = !neg;
}
if (b < 0)
{
b = -b;
neg = !neg;
}
res = udivmodsi4 (a, b, 0);
if (neg)
res = -res;
return res;
}
SItype
__modsi3 (SItype a, SItype b)
{
word_type neg = 0;
SItype res;
if (a < 0)
{
a = -a;
neg = 1;
}
if (b < 0)
b = -b;
res = udivmodsi4 (a, b, 1);
if (neg)
res = -res;
return res;
}
SItype
__udivsi3 (SItype a, SItype b)
{
return udivmodsi4 (a, b, 0);
}
SItype
__umodsi3 (SItype a, SItype b)
{
return udivmodsi4 (a, b, 1);
}
libgcc/config/mep/t-mep deleted 100644 → 0
# profiling support
LIB1ASMSRC = mep/lib1funcs.S
LIB1ASMFUNCS = _mep_profile \
_mep_bb_init_trace \
_mep_bb_init \
_mep_bb_trace \
_mep_bb_increment
# multiply and divide routines
LIB2ADD = \
$(srcdir)/config/mep/lib2funcs.c \
$(srcdir)/config/mep/tramp.c
# Use -O0 instead of -O2 so we don't get complex relocations
CRTSTUFF_CFLAGS += -O0
libgcc/config/mep/tramp.c deleted 100644 → 0
/* Trampoline support for MeP
Copyright (C) 2004-2016 Free Software Foundation, Inc.
Contributed by Red Hat Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3 of the License, or (at your
option) any later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
7a0a ldc $10,$pc
c0ae000a lw $0,10($10)
caae000e lw $10,14($10)
10ae jmp $10
00000000 static chain
00000000 function address
*/
static inline int
cache_config_register(void) {
int rv;
asm ("ldc\t%0, $ccfg" : "=r" (rv));
return rv;
}
#define ICACHE_SIZE ((cache_config_register() >> 16) & 0x7f)
#define DCACHE_SIZE (cache_config_register() & 0x7f)
#define ICACHE_DATA_BASE 0x00300000
#define ICACHE_TAG_BASE 0x00310000
#define DCACHE_DATA_BASE 0x00320000
#define DCACHE_TAG_BASE 0x00330000
static inline void
flush_dcache (int addr)
{
asm volatile ("cache\t0, (%0)" : : "r" (addr));
}
void
__mep_trampoline_helper (unsigned long *tramp,
int function_address,
int static_chain);
void
__mep_trampoline_helper (unsigned long *tramp,
int function_address,
int static_chain)
{
int dsize, isize;
#ifdef __LITTLE_ENDIAN__
tramp[0] = 0xc0ae7a0a;
tramp[1] = 0xcaae000a;
tramp[2] = 0x10ae000e;
#else
tramp[0] = 0x7a0ac0ae;
tramp[1] = 0x000acaae;
tramp[2] = 0x000e10ae;
#endif
tramp[3] = static_chain;
tramp[4] = function_address;
dsize = DCACHE_SIZE;
isize = ICACHE_SIZE;
if (dsize)
{
flush_dcache ((int)tramp);
flush_dcache ((int)tramp+16);
}
if (isize)
{
int imask = (isize * 1024) - 1;
int tmask = ~imask;
unsigned int i;
volatile unsigned int *tags;
imask &= 0xffe0;
for (i=(unsigned int)tramp; i<(unsigned int)tramp+20; i+=16)
{
tags = (unsigned int *)(ICACHE_TAG_BASE + (i & imask));
if ((*tags & tmask) == (i & tmask))
*tags &= ~1;
}
}
}
libstdc++-v3/ChangeLog
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* configure.host: Remove mep-* support.
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* configure: Regenerate.
* configure.host: Remove support for knetbsd.
* crossconfig.m4: Likewise.
......
libstdc++-v3/configure.host
......@@ -114,10 +114,6 @@ case "${host_cpu}" in
hppa*)
try_cpu=hppa
;;
mep*)
EXTRA_CXX_FLAGS=-mm
try_cpu=generic
;;
mips*)
try_cpu=mips
;;
......
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