rs6000: Fix more testsuite fallout from rs6000_legitimate_address_p() fix. [PR93913]

	PR target/93913
	* gcc.target/powerpc/fold-vec-st-char.c (scan-assembler-times): Allow
	stxv and stxvx instructions as well.
	* gcc.target/powerpc/fold-vec-st-float.c: Likewise.
	* gcc.target/powerpc/fold-vec-st-int.c: Likewise.
	* gcc.target/powerpc/fold-vec-st-short.c: Likewise.

gcc/testsuite/ChangeLog

+2020-02-26  Peter Bergner  <bergner@linux.ibm.com>
+
+	PR target/93913
+	* gcc.target/powerpc/fold-vec-st-char.c (scan-assembler-times): Allow
+	stxv and stxvx instructions as well.
+	* gcc.target/powerpc/fold-vec-st-float.c: Likewise.
+	* gcc.target/powerpc/fold-vec-st-int.c: Likewise.
+	* gcc.target/powerpc/fold-vec-st-short.c: Likewise.
+
 2020-02-26  Patrick Palka  <ppalka@redhat.com>
 
 	* g++.dg/concepts/diagnostic2.C: New test.

gcc/testsuite/gcc.target/powerpc/fold-vec-st-char.c

@@ -91,4 +91,4 @@ testst_cst7 (vector bool char vbc1, int i1, signed char * vscp)
 	return vec_st(vbc1, 36, vscp);
 }
 
-/* { dg-final { scan-assembler-times {\mstvx\M} 14 } } */
+/* { dg-final { scan-assembler-times {\m(?:stvx|stxv|stxvx)\M} 14 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-st-float.c

@@ -31,4 +31,4 @@ testst_cst2 (vector float vf1, int i1, float * fp)
 	return vec_st(vf1, 24, fp);
 }
 
-/* { dg-final { scan-assembler-times {\mstvx\M}  4 } } */
+/* { dg-final { scan-assembler-times {\m(?:stvx|stxv|stxvx)\M} 4 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-st-int.c

@@ -80,5 +80,5 @@ testst_cst7 (vector bool int vbi1, int i1, signed int * vsip)
 	return vec_st(vbi1, 36, vsip);
 }
 
-/* { dg-final { scan-assembler-times {\mstvx\M}  14 } } */
+/* { dg-final { scan-assembler-times {\m(?:stvx|stxv|stxvx)\M} 14 } } */
 

gcc/testsuite/gcc.target/powerpc/fold-vec-st-short.c

@@ -80,4 +80,4 @@ testst_cst7 (vector bool short vbs1, int i1, signed short * vssp)
 	return vec_st(vbs1, 36, vssp);
 }
 
-/* { dg-final { scan-assembler-times {\mstvx\M} 14} } */
+/* { dg-final { scan-assembler-times {\m(?:stvx|stxv|stxvx)\M} 14} } */