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riscv-gcc-1
Commit 03158648 by Charles Baylis Committed by Christophe Lyon
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re PR target/59142 (internal compiler error while compiling OpenCV 2.4.7) 

2013-12-19  Charles Baylis  <charles.baylis@linaro.org>

	PR target/59142
	gcc/
	* arm/predicates.md (arm_hard_general_register_operand): New
	predicate.
	(arm_hard_register_operand): Remove.
	* config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand
	for all patterns.
	* config/arm/ldmstm.md: Regenerate.

From-SVN: r206124
parent 315d7bd4
Showing with 185 additions and 175 deletions
gcc/ChangeLog
2013-12-19 Charles Baylis <charles.baylis@linaro.org> 2013-12-19 Charles Baylis <charles.baylis@linaro.org>
PR target/59142 PR target/59142
* arm/predicates.md (arm_hard_general_register_operand): New
predicate.
(arm_hard_register_operand): Remove.
* config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand
for all patterns.
* config/arm/ldmstm.md: Regenerate.
2013-12-19 Charles Baylis <charles.baylis@linaro.org>
PR target/59142
* config/arm/predicates.md (vfp_hard_register_operand): New predicate. * config/arm/predicates.md (vfp_hard_register_operand): New predicate.
* config/arm/arm.md (vfp_pop_multiple_with_writeback): Use * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use
vfp_hard_register_operand. vfp_hard_register_operand.
gcc/config/arm/arm-ldmstm.ml
...@@ -70,7 +70,7 @@ let destreg nregs first op_type thumb = ...@@ -70,7 +70,7 @@ let destreg nregs first op_type thumb =
let write_ldm_set thumb nregs offset opnr first = let write_ldm_set thumb nregs offset opnr first =
let indent = " " in let indent = " " in
Printf.printf "%s" (if first then " [" else indent); Printf.printf "%s" (if first then " [" else indent);
Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr; Printf.printf "(set (match_operand:SI %d \"arm_hard_general_register_operand\" \"\")\n" opnr;
Printf.printf "%s (mem:SI " indent; Printf.printf "%s (mem:SI " indent;
begin if offset != 0 then Printf.printf "(plus:SI " end; begin if offset != 0 then Printf.printf "(plus:SI " end;
Printf.printf "%s" (destreg nregs first IN thumb); Printf.printf "%s" (destreg nregs first IN thumb);
...@@ -84,7 +84,7 @@ let write_stm_set thumb nregs offset opnr first = ...@@ -84,7 +84,7 @@ let write_stm_set thumb nregs offset opnr first =
begin if offset != 0 then Printf.printf "(plus:SI " end; begin if offset != 0 then Printf.printf "(plus:SI " end;
Printf.printf "%s" (destreg nregs first IN thumb); Printf.printf "%s" (destreg nregs first IN thumb);
begin if offset != 0 then Printf.printf " (const_int %d))" offset end; begin if offset != 0 then Printf.printf " (const_int %d))" offset end;
Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_general_register_operand\" \"\"))" indent opnr
let write_ldm_peep_set extra_indent nregs opnr first = let write_ldm_peep_set extra_indent nregs opnr first =
let indent = " " ^ extra_indent in let indent = " " ^ extra_indent in
......
gcc/config/arm/ldmstm.md
...@@ -23,15 +23,15 @@ ...@@ -23,15 +23,15 @@
(define_insn "*ldm4_ia" (define_insn "*ldm4_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) (mem:SI (match_operand:SI 5 "s_register_operand" "rk")))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 8)))) (const_int 8))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 12))))])] (const_int 12))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
...@@ -42,15 +42,15 @@ ...@@ -42,15 +42,15 @@
(define_insn "*thumb_ldm4_ia" (define_insn "*thumb_ldm4_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_operand:SI 5 "s_register_operand" "l"))) (mem:SI (match_operand:SI 5 "s_register_operand" "l")))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 8)))) (const_int 8))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 12))))])] (const_int 12))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
...@@ -61,15 +61,15 @@ ...@@ -61,15 +61,15 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 5 "s_register_operand" "+&rk") [(set (match_operand:SI 5 "s_register_operand" "+&rk")
(plus:SI (match_dup 5) (const_int 16))) (plus:SI (match_dup 5) (const_int 16)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 5))) (mem:SI (match_dup 5)))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 8)))) (const_int 8))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 12))))])] (const_int 12))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
...@@ -82,15 +82,15 @@ ...@@ -82,15 +82,15 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 5 "s_register_operand" "+&l") [(set (match_operand:SI 5 "s_register_operand" "+&l")
(plus:SI (match_dup 5) (const_int 16))) (plus:SI (match_dup 5) (const_int 16)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 5))) (mem:SI (match_dup 5)))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 8)))) (const_int 8))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 12))))])] (const_int 12))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
...@@ -100,13 +100,13 @@ ...@@ -100,13 +100,13 @@
(define_insn "*stm4_ia" (define_insn "*stm4_ia"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 4))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 8))) (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 12))) (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%(ia%)\t%5, {%1, %2, %3, %4}" "stm%(ia%)\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
...@@ -118,13 +118,13 @@ ...@@ -118,13 +118,13 @@
[(set (match_operand:SI 5 "s_register_operand" "+&rk") [(set (match_operand:SI 5 "s_register_operand" "+&rk")
(plus:SI (match_dup 5) (const_int 16))) (plus:SI (match_dup 5) (const_int 16)))
(set (mem:SI (match_dup 5)) (set (mem:SI (match_dup 5))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 4))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 8))) (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 12))) (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stm%(ia%)\t%5!, {%1, %2, %3, %4}" "stm%(ia%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
...@@ -136,29 +136,29 @@ ...@@ -136,29 +136,29 @@
[(set (match_operand:SI 5 "s_register_operand" "+&l") [(set (match_operand:SI 5 "s_register_operand" "+&l")
(plus:SI (match_dup 5) (const_int 16))) (plus:SI (match_dup 5) (const_int 16)))
(set (mem:SI (match_dup 5)) (set (mem:SI (match_dup 5))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 4))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 8))) (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 12))) (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
"stm%(ia%)\t%5!, {%1, %2, %3, %4}" "stm%(ia%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store4")]) [(set_attr "type" "store4")])
(define_insn "*ldm4_ib" (define_insn "*ldm4_ib"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 8)))) (const_int 8))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 12)))) (const_int 12))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 16))))])] (const_int 16))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4" "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
...@@ -170,16 +170,16 @@ ...@@ -170,16 +170,16 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 5 "s_register_operand" "+&rk") [(set (match_operand:SI 5 "s_register_operand" "+&rk")
(plus:SI (match_dup 5) (const_int 16))) (plus:SI (match_dup 5) (const_int 16)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 8)))) (const_int 8))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 12)))) (const_int 12))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int 16))))])] (const_int 16))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 5" "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
...@@ -190,13 +190,13 @@ ...@@ -190,13 +190,13 @@
(define_insn "*stm4_ib" (define_insn "*stm4_ib"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 8))) (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 12))) (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4" "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"stm%(ib%)\t%5, {%1, %2, %3, %4}" "stm%(ib%)\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
...@@ -207,13 +207,13 @@ ...@@ -207,13 +207,13 @@
[(set (match_operand:SI 5 "s_register_operand" "+&rk") [(set (match_operand:SI 5 "s_register_operand" "+&rk")
(plus:SI (match_dup 5) (const_int 16))) (plus:SI (match_dup 5) (const_int 16)))
(set (mem:SI (plus:SI (match_dup 5) (const_int 4))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 8))) (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 12))) (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 5" "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
"stm%(ib%)\t%5!, {%1, %2, %3, %4}" "stm%(ib%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
...@@ -221,16 +221,16 @@ ...@@ -221,16 +221,16 @@
(define_insn "*ldm4_da" (define_insn "*ldm4_da"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
(const_int -12)))) (const_int -12))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -4)))) (const_int -4))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 5)))])] (mem:SI (match_dup 5)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4" "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"ldm%(da%)\t%5, {%1, %2, %3, %4}" "ldm%(da%)\t%5, {%1, %2, %3, %4}"
...@@ -241,16 +241,16 @@ ...@@ -241,16 +241,16 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 5 "s_register_operand" "+&rk") [(set (match_operand:SI 5 "s_register_operand" "+&rk")
(plus:SI (match_dup 5) (const_int -16))) (plus:SI (match_dup 5) (const_int -16)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -12)))) (const_int -12))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -4)))) (const_int -4))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 5)))])] (mem:SI (match_dup 5)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 5" "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
"ldm%(da%)\t%5!, {%1, %2, %3, %4}" "ldm%(da%)\t%5!, {%1, %2, %3, %4}"
...@@ -260,13 +260,13 @@ ...@@ -260,13 +260,13 @@
(define_insn "*stm4_da" (define_insn "*stm4_da"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -8))) (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -4))) (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (match_dup 5)) (set (mem:SI (match_dup 5))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4" "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"stm%(da%)\t%5, {%1, %2, %3, %4}" "stm%(da%)\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
...@@ -277,13 +277,13 @@ ...@@ -277,13 +277,13 @@
[(set (match_operand:SI 5 "s_register_operand" "+&rk") [(set (match_operand:SI 5 "s_register_operand" "+&rk")
(plus:SI (match_dup 5) (const_int -16))) (plus:SI (match_dup 5) (const_int -16)))
(set (mem:SI (plus:SI (match_dup 5) (const_int -12))) (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -8))) (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -4))) (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (match_dup 5)) (set (mem:SI (match_dup 5))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 5" "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
"stm%(da%)\t%5!, {%1, %2, %3, %4}" "stm%(da%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
...@@ -291,16 +291,16 @@ ...@@ -291,16 +291,16 @@
(define_insn "*ldm4_db" (define_insn "*ldm4_db"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
(const_int -16)))) (const_int -16))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -12)))) (const_int -12))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -4))))])] (const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
...@@ -313,16 +313,16 @@ ...@@ -313,16 +313,16 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 5 "s_register_operand" "+&rk") [(set (match_operand:SI 5 "s_register_operand" "+&rk")
(plus:SI (match_dup 5) (const_int -16))) (plus:SI (match_dup 5) (const_int -16)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -16)))) (const_int -16))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -12)))) (const_int -12))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 4 "arm_hard_register_operand" "") (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 5) (mem:SI (plus:SI (match_dup 5)
(const_int -4))))])] (const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
...@@ -334,13 +334,13 @@ ...@@ -334,13 +334,13 @@
(define_insn "*stm4_db" (define_insn "*stm4_db"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -12))) (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -8))) (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -4))) (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%(db%)\t%5, {%1, %2, %3, %4}" "stm%(db%)\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
...@@ -352,13 +352,13 @@ ...@@ -352,13 +352,13 @@
[(set (match_operand:SI 5 "s_register_operand" "+&rk") [(set (match_operand:SI 5 "s_register_operand" "+&rk")
(plus:SI (match_dup 5) (const_int -16))) (plus:SI (match_dup 5) (const_int -16)))
(set (mem:SI (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -16)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -12))) (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -8))) (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
(match_operand:SI 3 "arm_hard_register_operand" "")) (match_operand:SI 3 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int -4))) (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
(match_operand:SI 4 "arm_hard_register_operand" ""))])] (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stm%(db%)\t%5!, {%1, %2, %3, %4}" "stm%(db%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
...@@ -474,12 +474,12 @@ ...@@ -474,12 +474,12 @@
(define_insn "*ldm3_ia" (define_insn "*ldm3_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) (mem:SI (match_operand:SI 4 "s_register_operand" "rk")))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 8))))])] (const_int 8))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
...@@ -490,12 +490,12 @@ ...@@ -490,12 +490,12 @@
(define_insn "*thumb_ldm3_ia" (define_insn "*thumb_ldm3_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_operand:SI 4 "s_register_operand" "l"))) (mem:SI (match_operand:SI 4 "s_register_operand" "l")))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 8))))])] (const_int 8))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
...@@ -506,12 +506,12 @@ ...@@ -506,12 +506,12 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 4 "s_register_operand" "+&rk") [(set (match_operand:SI 4 "s_register_operand" "+&rk")
(plus:SI (match_dup 4) (const_int 12))) (plus:SI (match_dup 4) (const_int 12)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 4))) (mem:SI (match_dup 4)))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 8))))])] (const_int 8))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
...@@ -524,12 +524,12 @@ ...@@ -524,12 +524,12 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 4 "s_register_operand" "+&l") [(set (match_operand:SI 4 "s_register_operand" "+&l")
(plus:SI (match_dup 4) (const_int 12))) (plus:SI (match_dup 4) (const_int 12)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 4))) (mem:SI (match_dup 4)))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 8))))])] (const_int 8))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
...@@ -539,11 +539,11 @@ ...@@ -539,11 +539,11 @@
(define_insn "*stm3_ia" (define_insn "*stm3_ia"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 4))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 8))) (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%(ia%)\t%4, {%1, %2, %3}" "stm%(ia%)\t%4, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
...@@ -555,11 +555,11 @@ ...@@ -555,11 +555,11 @@
[(set (match_operand:SI 4 "s_register_operand" "+&rk") [(set (match_operand:SI 4 "s_register_operand" "+&rk")
(plus:SI (match_dup 4) (const_int 12))) (plus:SI (match_dup 4) (const_int 12)))
(set (mem:SI (match_dup 4)) (set (mem:SI (match_dup 4))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 4))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 8))) (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%(ia%)\t%4!, {%1, %2, %3}" "stm%(ia%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
...@@ -571,24 +571,24 @@ ...@@ -571,24 +571,24 @@
[(set (match_operand:SI 4 "s_register_operand" "+&l") [(set (match_operand:SI 4 "s_register_operand" "+&l")
(plus:SI (match_dup 4) (const_int 12))) (plus:SI (match_dup 4) (const_int 12)))
(set (mem:SI (match_dup 4)) (set (mem:SI (match_dup 4))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 4))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 8))) (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
"stm%(ia%)\t%4!, {%1, %2, %3}" "stm%(ia%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "store3")]) [(set_attr "type" "store3")])
(define_insn "*ldm3_ib" (define_insn "*ldm3_ib"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 8)))) (const_int 8))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 12))))])] (const_int 12))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3" "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
...@@ -600,13 +600,13 @@ ...@@ -600,13 +600,13 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 4 "s_register_operand" "+&rk") [(set (match_operand:SI 4 "s_register_operand" "+&rk")
(plus:SI (match_dup 4) (const_int 12))) (plus:SI (match_dup 4) (const_int 12)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 8)))) (const_int 8))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int 12))))])] (const_int 12))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4" "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
...@@ -617,11 +617,11 @@ ...@@ -617,11 +617,11 @@
(define_insn "*stm3_ib" (define_insn "*stm3_ib"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 8))) (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3" "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"stm%(ib%)\t%4, {%1, %2, %3}" "stm%(ib%)\t%4, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
...@@ -632,11 +632,11 @@ ...@@ -632,11 +632,11 @@
[(set (match_operand:SI 4 "s_register_operand" "+&rk") [(set (match_operand:SI 4 "s_register_operand" "+&rk")
(plus:SI (match_dup 4) (const_int 12))) (plus:SI (match_dup 4) (const_int 12)))
(set (mem:SI (plus:SI (match_dup 4) (const_int 4))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 8))) (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4" "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"stm%(ib%)\t%4!, {%1, %2, %3}" "stm%(ib%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
...@@ -644,13 +644,13 @@ ...@@ -644,13 +644,13 @@
(define_insn "*ldm3_da" (define_insn "*ldm3_da"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int -4)))) (const_int -4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 4)))])] (mem:SI (match_dup 4)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3" "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"ldm%(da%)\t%4, {%1, %2, %3}" "ldm%(da%)\t%4, {%1, %2, %3}"
...@@ -661,13 +661,13 @@ ...@@ -661,13 +661,13 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 4 "s_register_operand" "+&rk") [(set (match_operand:SI 4 "s_register_operand" "+&rk")
(plus:SI (match_dup 4) (const_int -12))) (plus:SI (match_dup 4) (const_int -12)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int -4)))) (const_int -4))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 4)))])] (mem:SI (match_dup 4)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4" "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"ldm%(da%)\t%4!, {%1, %2, %3}" "ldm%(da%)\t%4!, {%1, %2, %3}"
...@@ -677,11 +677,11 @@ ...@@ -677,11 +677,11 @@
(define_insn "*stm3_da" (define_insn "*stm3_da"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int -4))) (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (match_dup 4)) (set (mem:SI (match_dup 4))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3" "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"stm%(da%)\t%4, {%1, %2, %3}" "stm%(da%)\t%4, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
...@@ -692,11 +692,11 @@ ...@@ -692,11 +692,11 @@
[(set (match_operand:SI 4 "s_register_operand" "+&rk") [(set (match_operand:SI 4 "s_register_operand" "+&rk")
(plus:SI (match_dup 4) (const_int -12))) (plus:SI (match_dup 4) (const_int -12)))
(set (mem:SI (plus:SI (match_dup 4) (const_int -8))) (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int -4))) (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (match_dup 4)) (set (mem:SI (match_dup 4))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4" "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"stm%(da%)\t%4!, {%1, %2, %3}" "stm%(da%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
...@@ -704,13 +704,13 @@ ...@@ -704,13 +704,13 @@
(define_insn "*ldm3_db" (define_insn "*ldm3_db"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
(const_int -12)))) (const_int -12))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int -4))))])] (const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
...@@ -723,13 +723,13 @@ ...@@ -723,13 +723,13 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 4 "s_register_operand" "+&rk") [(set (match_operand:SI 4 "s_register_operand" "+&rk")
(plus:SI (match_dup 4) (const_int -12))) (plus:SI (match_dup 4) (const_int -12)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int -12)))) (const_int -12))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 4) (mem:SI (plus:SI (match_dup 4)
(const_int -4))))])] (const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
...@@ -741,11 +741,11 @@ ...@@ -741,11 +741,11 @@
(define_insn "*stm3_db" (define_insn "*stm3_db"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int -8))) (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int -4))) (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%(db%)\t%4, {%1, %2, %3}" "stm%(db%)\t%4, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
...@@ -757,11 +757,11 @@ ...@@ -757,11 +757,11 @@
[(set (match_operand:SI 4 "s_register_operand" "+&rk") [(set (match_operand:SI 4 "s_register_operand" "+&rk")
(plus:SI (match_dup 4) (const_int -12))) (plus:SI (match_dup 4) (const_int -12)))
(set (mem:SI (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -12)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int -8))) (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
(match_operand:SI 2 "arm_hard_register_operand" "")) (match_operand:SI 2 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int -4))) (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
(match_operand:SI 3 "arm_hard_register_operand" ""))])] (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%(db%)\t%4!, {%1, %2, %3}" "stm%(db%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
...@@ -863,9 +863,9 @@ ...@@ -863,9 +863,9 @@
(define_insn "*ldm2_ia" (define_insn "*ldm2_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) (mem:SI (match_operand:SI 3 "s_register_operand" "rk")))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int 4))))])] (const_int 4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
...@@ -876,9 +876,9 @@ ...@@ -876,9 +876,9 @@
(define_insn "*thumb_ldm2_ia" (define_insn "*thumb_ldm2_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_operand:SI 3 "s_register_operand" "l"))) (mem:SI (match_operand:SI 3 "s_register_operand" "l")))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int 4))))])] (const_int 4))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
...@@ -889,9 +889,9 @@ ...@@ -889,9 +889,9 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 3 "s_register_operand" "+&rk") [(set (match_operand:SI 3 "s_register_operand" "+&rk")
(plus:SI (match_dup 3) (const_int 8))) (plus:SI (match_dup 3) (const_int 8)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 3))) (mem:SI (match_dup 3)))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int 4))))])] (const_int 4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
...@@ -904,9 +904,9 @@ ...@@ -904,9 +904,9 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 3 "s_register_operand" "+&l") [(set (match_operand:SI 3 "s_register_operand" "+&l")
(plus:SI (match_dup 3) (const_int 8))) (plus:SI (match_dup 3) (const_int 8)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 3))) (mem:SI (match_dup 3)))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int 4))))])] (const_int 4))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
...@@ -916,9 +916,9 @@ ...@@ -916,9 +916,9 @@
(define_insn "*stm2_ia" (define_insn "*stm2_ia"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 3) (const_int 4))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stm%(ia%)\t%3, {%1, %2}" "stm%(ia%)\t%3, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
...@@ -930,9 +930,9 @@ ...@@ -930,9 +930,9 @@
[(set (match_operand:SI 3 "s_register_operand" "+&rk") [(set (match_operand:SI 3 "s_register_operand" "+&rk")
(plus:SI (match_dup 3) (const_int 8))) (plus:SI (match_dup 3) (const_int 8)))
(set (mem:SI (match_dup 3)) (set (mem:SI (match_dup 3))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 3) (const_int 4))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%(ia%)\t%3!, {%1, %2}" "stm%(ia%)\t%3!, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
...@@ -944,19 +944,19 @@ ...@@ -944,19 +944,19 @@
[(set (match_operand:SI 3 "s_register_operand" "+&l") [(set (match_operand:SI 3 "s_register_operand" "+&l")
(plus:SI (match_dup 3) (const_int 8))) (plus:SI (match_dup 3) (const_int 8)))
(set (mem:SI (match_dup 3)) (set (mem:SI (match_dup 3))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 3) (const_int 4))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
"stm%(ia%)\t%3!, {%1, %2}" "stm%(ia%)\t%3!, {%1, %2}"
[(set_attr "type" "store2")]) [(set_attr "type" "store2")])
(define_insn "*ldm2_ib" (define_insn "*ldm2_ib"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int 8))))])] (const_int 8))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 2" "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
...@@ -968,10 +968,10 @@ ...@@ -968,10 +968,10 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 3 "s_register_operand" "+&rk") [(set (match_operand:SI 3 "s_register_operand" "+&rk")
(plus:SI (match_dup 3) (const_int 8))) (plus:SI (match_dup 3) (const_int 8)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int 4)))) (const_int 4))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int 8))))])] (const_int 8))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3" "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
...@@ -982,9 +982,9 @@ ...@@ -982,9 +982,9 @@
(define_insn "*stm2_ib" (define_insn "*stm2_ib"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 2" "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
"stm%(ib%)\t%3, {%1, %2}" "stm%(ib%)\t%3, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
...@@ -995,9 +995,9 @@ ...@@ -995,9 +995,9 @@
[(set (match_operand:SI 3 "s_register_operand" "+&rk") [(set (match_operand:SI 3 "s_register_operand" "+&rk")
(plus:SI (match_dup 3) (const_int 8))) (plus:SI (match_dup 3) (const_int 8)))
(set (mem:SI (plus:SI (match_dup 3) (const_int 4))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3" "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"stm%(ib%)\t%3!, {%1, %2}" "stm%(ib%)\t%3!, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
...@@ -1005,10 +1005,10 @@ ...@@ -1005,10 +1005,10 @@
(define_insn "*ldm2_da" (define_insn "*ldm2_da"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
(const_int -4)))) (const_int -4))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 3)))])] (mem:SI (match_dup 3)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 2" "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
"ldm%(da%)\t%3, {%1, %2}" "ldm%(da%)\t%3, {%1, %2}"
...@@ -1019,10 +1019,10 @@ ...@@ -1019,10 +1019,10 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 3 "s_register_operand" "+&rk") [(set (match_operand:SI 3 "s_register_operand" "+&rk")
(plus:SI (match_dup 3) (const_int -8))) (plus:SI (match_dup 3) (const_int -8)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int -4)))) (const_int -4))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (match_dup 3)))])] (mem:SI (match_dup 3)))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3" "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"ldm%(da%)\t%3!, {%1, %2}" "ldm%(da%)\t%3!, {%1, %2}"
...@@ -1032,9 +1032,9 @@ ...@@ -1032,9 +1032,9 @@
(define_insn "*stm2_da" (define_insn "*stm2_da"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (match_dup 3)) (set (mem:SI (match_dup 3))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 2" "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
"stm%(da%)\t%3, {%1, %2}" "stm%(da%)\t%3, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
...@@ -1045,9 +1045,9 @@ ...@@ -1045,9 +1045,9 @@
[(set (match_operand:SI 3 "s_register_operand" "+&rk") [(set (match_operand:SI 3 "s_register_operand" "+&rk")
(plus:SI (match_dup 3) (const_int -8))) (plus:SI (match_dup 3) (const_int -8)))
(set (mem:SI (plus:SI (match_dup 3) (const_int -4))) (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (match_dup 3)) (set (mem:SI (match_dup 3))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 3" "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
"stm%(da%)\t%3!, {%1, %2}" "stm%(da%)\t%3!, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
...@@ -1055,10 +1055,10 @@ ...@@ -1055,10 +1055,10 @@
(define_insn "*ldm2_db" (define_insn "*ldm2_db"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_register_operand" "") [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int -4))))])] (const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
...@@ -1071,10 +1071,10 @@ ...@@ -1071,10 +1071,10 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 3 "s_register_operand" "+&rk") [(set (match_operand:SI 3 "s_register_operand" "+&rk")
(plus:SI (match_dup 3) (const_int -8))) (plus:SI (match_dup 3) (const_int -8)))
(set (match_operand:SI 1 "arm_hard_register_operand" "") (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int -8)))) (const_int -8))))
(set (match_operand:SI 2 "arm_hard_register_operand" "") (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(mem:SI (plus:SI (match_dup 3) (mem:SI (plus:SI (match_dup 3)
(const_int -4))))])] (const_int -4))))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
...@@ -1086,9 +1086,9 @@ ...@@ -1086,9 +1086,9 @@
(define_insn "*stm2_db" (define_insn "*stm2_db"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 3) (const_int -4))) (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stm%(db%)\t%3, {%1, %2}" "stm%(db%)\t%3, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
...@@ -1100,9 +1100,9 @@ ...@@ -1100,9 +1100,9 @@
[(set (match_operand:SI 3 "s_register_operand" "+&rk") [(set (match_operand:SI 3 "s_register_operand" "+&rk")
(plus:SI (match_dup 3) (const_int -8))) (plus:SI (match_dup 3) (const_int -8)))
(set (mem:SI (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -8)))
(match_operand:SI 1 "arm_hard_register_operand" "")) (match_operand:SI 1 "arm_hard_general_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 3) (const_int -4))) (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
(match_operand:SI 2 "arm_hard_register_operand" ""))])] (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%(db%)\t%3!, {%1, %2}" "stm%(db%)\t%3!, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
......
gcc/config/arm/predicates.md
...@@ -54,10 +54,10 @@ ...@@ -54,10 +54,10 @@
(match_operand 0 "s_register_operand"))) (match_operand 0 "s_register_operand")))
;; Any hard register. ;; Any hard register.
(define_predicate "arm_hard_register_operand" (define_predicate "arm_hard_general_register_operand"
(match_code "reg") (match_code "reg")
{ {
return REGNO (op) < FIRST_PSEUDO_REGISTER; return REGNO (op) <= LAST_ARM_REGNUM;
}) })
;; A low register. ;; A low register.
......
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