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Commit 021b5e6b by Kyrylo Tkachov Committed by Kyrylo Tkachov
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arm.c (enum arm_builtins): Add crypto builtins. 

2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	 * config/arm/arm.c (enum arm_builtins): Add crypto builtins.
	 (arm_init_neon_builtins): Handle crypto builtins.
	 (bdesc_2arg): Likewise.
	 (bdesc_1arg): Likewise.
	 (bdesc_3arg): New table.
	 (arm_expand_ternop_builtin): New function.
	 (arm_expand_unop_builtin): Handle sha1h explicitly.
	 (arm_expand_builtin): Handle ternary builtins.
	 * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS):
	 Define __ARM_FEATURE_CRYPTO.
	 * config/arm/arm.md: Include crypto.md.
	 (is_neon_type): Add crypto types.
	 * config/arm/arm_neon_builtins.def: Add TImode reinterprets.
	 * config/arm/crypto.def: New.
	 * config/arm/crypto.md: Likewise.
	 * config/arm/iterators.md (CRYPTO_UNARY): New int iterator.
	 (CRYPTO_BINARY): Likewise.
	 (CRYPTO_TERNARY): Likewise.
	 (CRYPTO_SELECTING): Likewise.
	 (crypto_pattern): New int attribute.
	 (crypto_size_sfx): Likewise.
	 (crypto_mode): Likewise.
	 (crypto_type): Likewise.
	 * config/arm/neon-gen.ml: Handle poly64_t and poly128_t types.
	 Handle crypto intrinsics.
	 * config/arm/neon.ml: Add support for poly64 and polt128 types
	 and intrinsics. Define crypto intrinsics.
	 * config/arm/neon.md (neon_vreinterpretti<mode>): New pattern.
	 (neon_vreinterpretv16qi<mode>): Use VQXMOV mode iterator.
	 (neon_vreinterpretv8hi<mode>): Likewise.
	 (neon_vreinterpretv4si<mode>): Likewise.
	 (neon_vreinterpretv4sf<mode>): Likewise.
	 (neon_vreinterpretv2di<mode>): Likewise.
	 * config/arm/unspecs.md (UNSPEC_AESD, UNSPEC_AESE, UNSPEC_AESIMC,
	 UNSPEC_AESMC, UNSPEC_SHA1C, UNSPEC_SHA1M, UNSPEC_SHA1P, UNSPEC_SHA1H,
	 UNSPEC_SHA1SU0, UNSPEC_SHA1SU1, UNSPEC_SHA256H, UNSPEC_SHA256H2,
	 UNSPEC_SHA256SU0, UNSPEC_SHA256SU1, VMULLP64): Define.
	 * config/arm/arm_neon.h: Regenerate.

From-SVN: r206130
parent b78e932d
Showing with 311 additions and 51 deletions
gcc/ChangeLog
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (enum arm_builtins): Add crypto builtins.
(arm_init_neon_builtins): Handle crypto builtins.
(bdesc_2arg): Likewise.
(bdesc_1arg): Likewise.
(bdesc_3arg): New table.
(arm_expand_ternop_builtin): New function.
(arm_expand_unop_builtin): Handle sha1h explicitly.
(arm_expand_builtin): Handle ternary builtins.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS):
Define __ARM_FEATURE_CRYPTO.
* config/arm/arm.md: Include crypto.md.
(is_neon_type): Add crypto types.
* config/arm/arm_neon_builtins.def: Add TImode reinterprets.
* config/arm/crypto.def: New.
* config/arm/crypto.md: Likewise.
* config/arm/iterators.md (CRYPTO_UNARY): New int iterator.
(CRYPTO_BINARY): Likewise.
(CRYPTO_TERNARY): Likewise.
(CRYPTO_SELECTING): Likewise.
(crypto_pattern): New int attribute.
(crypto_size_sfx): Likewise.
(crypto_mode): Likewise.
(crypto_type): Likewise.
* config/arm/neon-gen.ml: Handle poly64_t and poly128_t types.
Handle crypto intrinsics.
* config/arm/neon.ml: Add support for poly64 and polt128 types
and intrinsics. Define crypto intrinsics.
* config/arm/neon.md (neon_vreinterpretti<mode>): New pattern.
(neon_vreinterpretv16qi<mode>): Use VQXMOV mode iterator.
(neon_vreinterpretv8hi<mode>): Likewise.
(neon_vreinterpretv4si<mode>): Likewise.
(neon_vreinterpretv4sf<mode>): Likewise.
(neon_vreinterpretv2di<mode>): Likewise.
* config/arm/unspecs.md (UNSPEC_AESD, UNSPEC_AESE, UNSPEC_AESIMC,
UNSPEC_AESMC, UNSPEC_SHA1C, UNSPEC_SHA1M, UNSPEC_SHA1P, UNSPEC_SHA1H,
UNSPEC_SHA1SU0, UNSPEC_SHA1SU1, UNSPEC_SHA256H, UNSPEC_SHA256H2,
UNSPEC_SHA256SU0, UNSPEC_SHA256SU1, VMULLP64): Define.
* config/arm/arm_neon.h: Regenerate.
2013-12-19 H.J. Lu <hongjiu.lu@intel.com>
PR driver/59321
gcc/config/arm/arm.h
......@@ -49,6 +49,8 @@ extern char arm_arch_name[];
builtin_define ("__ARM_FEATURE_QBIT"); \
if (TARGET_ARM_SAT) \
builtin_define ("__ARM_FEATURE_SAT"); \
if (TARGET_CRYPTO) \
builtin_define ("__ARM_FEATURE_CRYPTO"); \
if (unaligned_access) \
builtin_define ("__ARM_FEATURE_UNALIGNED"); \
if (TARGET_CRC32) \
......
gcc/config/arm/arm.md
......@@ -293,7 +293,7 @@
neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\
neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\
neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\
neon_mul_h_long, neon_mul_s_long, neon_mul_h_scalar,\
neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\
neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\
neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\
neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\
......@@ -355,7 +355,9 @@
neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\
neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\
neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\
neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q")
neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aes,\
crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow, crypto_sha256_fast,\
crypto_sha256_slow")
(const_string "yes")
(const_string "no")))
......@@ -12918,6 +12920,8 @@
(include "thumb2.md")
;; Neon patterns
(include "neon.md")
;; Crypto patterns
(include "crypto.md")
;; Synchronization Primitives
(include "sync.md")
;; Fixed-point patterns
......
gcc/config/arm/arm_neon.h
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/arm/arm_neon_builtins.def
......@@ -158,11 +158,12 @@ VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di),
VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di),
VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di),
VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di),
VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di),
VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di),
VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di),
VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di),
VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di),
VAR6 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di, ti),
VAR6 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di, ti),
VAR6 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di, ti),
VAR6 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di, ti),
VAR6 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di, ti),
VAR6 (REINTERP, vreinterpretti, v16qi, v8hi, v4si, v4sf, v2di, ti),
VAR10 (LOAD1, vld1,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
VAR10 (LOAD1LANE, vld1_lane,
......
gcc/config/arm/crypto.def 0 → 100644
/* Cryptographic instruction builtin definitions.
Copyright (C) 2013
Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
CRYPTO2 (aesd, AESD, v16uqi, v16uqi, v16uqi)
CRYPTO2 (aese, AESE, v16uqi, v16uqi, v16uqi)
CRYPTO1 (aesimc, AESIMC, v16uqi, v16uqi)
CRYPTO1 (aesmc, AESMC, v16uqi, v16uqi)
CRYPTO1 (sha1h, SHA1H, v4usi, v4usi)
CRYPTO2 (sha1su1, SHA1SU1, v4usi, v4usi, v4usi)
CRYPTO2 (sha256su0, SHA256SU0, v4usi, v4usi, v4usi)
CRYPTO3 (sha1c, SHA1C, v4usi, v4usi, v4usi, v4usi)
CRYPTO3 (sha1m, SHA1M, v4usi, v4usi, v4usi, v4usi)
CRYPTO3 (sha1p, SHA1P, v4usi, v4usi, v4usi, v4usi)
CRYPTO3 (sha1su0, SHA1SU0, v4usi, v4usi, v4usi, v4usi)
CRYPTO3 (sha256h, SHA256H, v4usi, v4usi, v4usi, v4usi)
CRYPTO3 (sha256h2, SHA256H2, v4usi, v4usi, v4usi, v4usi)
CRYPTO3 (sha256su1, SHA256SU1, v4usi, v4usi, v4usi, v4usi)
CRYPTO2 (vmullp64, VMULLP64, uti, udi, udi)
gcc/config/arm/crypto.md 0 → 100644
;; ARMv8-A crypto patterns.
;; Copyright (C) 2013 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_insn "crypto_<crypto_pattern>"
[(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
(unspec:<crypto_mode> [(match_operand:<crypto_mode> 1
"register_operand" "w")]
CRYPTO_UNARY))]
"TARGET_CRYPTO"
"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1"
[(set_attr "type" "<crypto_type>")]
)
(define_insn "crypto_<crypto_pattern>"
[(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
(unspec:<crypto_mode> [(match_operand:<crypto_mode> 1 "register_operand" "0")
(match_operand:<crypto_mode> 2 "register_operand" "w")]
CRYPTO_BINARY))]
"TARGET_CRYPTO"
"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2"
[(set_attr "type" "<crypto_type>")]
)
(define_insn "crypto_<crypto_pattern>"
[(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
(unspec:<crypto_mode> [(match_operand:<crypto_mode> 1 "register_operand" "0")
(match_operand:<crypto_mode> 2 "register_operand" "w")
(match_operand:<crypto_mode> 3 "register_operand" "w")]
CRYPTO_TERNARY))]
"TARGET_CRYPTO"
"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2, %q3"
[(set_attr "type" "<crypto_type>")]
)
(define_insn "crypto_sha1h"
[(set (match_operand:V4SI 0 "register_operand" "=w")
(zero_extend:V4SI
(unspec:SI [(vec_select:SI
(match_operand:V4SI 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))]
UNSPEC_SHA1H)))]
"TARGET_CRYPTO"
"sha1h.32\\t%q0, %q1"
[(set_attr "type" "crypto_sha1_fast")]
)
(define_insn "crypto_vmullp64"
[(set (match_operand:TI 0 "register_operand" "=w")
(unspec:TI [(match_operand:DI 1 "register_operand" "w")
(match_operand:DI 2 "register_operand" "w")]
UNSPEC_VMULLP64))]
"TARGET_CRYPTO"
"vmull.p64\\t%q0, %P1, %P2"
[(set_attr "type" "neon_mul_d_long")]
)
(define_insn "crypto_<crypto_pattern>"
[(set (match_operand:V4SI 0 "register_operand" "=w")
(unspec:<crypto_mode>
[(match_operand:<crypto_mode> 1 "register_operand" "0")
(vec_select:SI
(match_operand:<crypto_mode> 2 "register_operand" "w")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))
(match_operand:<crypto_mode> 3 "register_operand" "w")]
CRYPTO_SELECTING))]
"TARGET_CRYPTO"
"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2, %q3"
[(set_attr "type" "<crypto_type>")]
)
gcc/config/arm/iterators.md
......@@ -204,6 +204,17 @@
(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW])
(define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC])
(define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE
UNSPEC_SHA1SU1 UNSPEC_SHA256SU0])
(define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H
UNSPEC_SHA256H2 UNSPEC_SHA256SU1])
(define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
UNSPEC_SHA1P])
;;----------------------------------------------------------------------------
;; Mode attributes
;;----------------------------------------------------------------------------
......@@ -530,6 +541,40 @@
(UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI")
(UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")])
(define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc")
(UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd")
(UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1")
(UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c")
(UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p")
(UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h")
(UNSPEC_SHA256H2 "sha256h2")
(UNSPEC_SHA256SU1 "sha256su1")])
(define_int_attr crypto_type
[(UNSPEC_AESE "crypto_aes") (UNSPEC_AESD "crypto_aes")
(UNSPEC_AESMC "crypto_aes") (UNSPEC_AESIMC "crypto_aes")
(UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow")
(UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast")
(UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow")
(UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast")
(UNSPEC_SHA256SU1 "crypto_sha256_slow")])
(define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8")
(UNSPEC_AESIMC "8") (UNSPEC_AESD "8")
(UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32")
(UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32")
(UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32")
(UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32")
(UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")])
(define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI")
(UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI")
(UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI")
(UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI")
(UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI")
(UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI")
(UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")])
;; Both kinds of return insn.
(define_code_iterator returns [return simple_return])
(define_code_attr return_str [(return "") (simple_return "simple_")])
......
gcc/config/arm/neon-gen.ml
......@@ -114,6 +114,7 @@ let rec signed_ctype = function
| T_uint32x4 -> T_int32x4
| T_uint64x1 -> T_int64x1
| T_uint64x2 -> T_int64x2
| T_poly64x2 -> T_int64x2
(* Cast to types defined by mode in arm.c, not random types pulled in from
the <stdint.h> header in use. This fixes incompatible pointer errors when
compiling with C++. *)
......@@ -125,6 +126,8 @@ let rec signed_ctype = function
| T_float32 -> T_floatSF
| T_poly8 -> T_intQI
| T_poly16 -> T_intHI
| T_poly64 -> T_intDI
| T_poly128 -> T_intTI
| T_arrayof (n, elt) -> T_arrayof (n, signed_ctype elt)
| T_ptrto elt -> T_ptrto (signed_ctype elt)
| T_const elt -> T_const (signed_ctype elt)
......@@ -362,80 +365,96 @@ let print_ops ops =
abase : "ARM" base name for the type (i.e. int in int8x8_t).
esize : element size.
enum : element count.
alevel: architecture level at which available.
*)
type fpulevel = CRYPTO | ALL
let deftypes () =
let typeinfo = [
(* Doubleword vector types. *)
"__builtin_neon_qi", "int", 8, 8;
"__builtin_neon_hi", "int", 16, 4;
"__builtin_neon_si", "int", 32, 2;
"__builtin_neon_di", "int", 64, 1;
"__builtin_neon_hf", "float", 16, 4;
"__builtin_neon_sf", "float", 32, 2;
"__builtin_neon_poly8", "poly", 8, 8;
"__builtin_neon_poly16", "poly", 16, 4;
"__builtin_neon_uqi", "uint", 8, 8;
"__builtin_neon_uhi", "uint", 16, 4;
"__builtin_neon_usi", "uint", 32, 2;
"__builtin_neon_udi", "uint", 64, 1;
"__builtin_neon_qi", "int", 8, 8, ALL;
"__builtin_neon_hi", "int", 16, 4, ALL;
"__builtin_neon_si", "int", 32, 2, ALL;
"__builtin_neon_di", "int", 64, 1, ALL;
"__builtin_neon_hf", "float", 16, 4, ALL;
"__builtin_neon_sf", "float", 32, 2, ALL;
"__builtin_neon_poly8", "poly", 8, 8, ALL;
"__builtin_neon_poly16", "poly", 16, 4, ALL;
"__builtin_neon_poly64", "poly", 64, 1, CRYPTO;
"__builtin_neon_uqi", "uint", 8, 8, ALL;
"__builtin_neon_uhi", "uint", 16, 4, ALL;
"__builtin_neon_usi", "uint", 32, 2, ALL;
"__builtin_neon_udi", "uint", 64, 1, ALL;
(* Quadword vector types. *)
"__builtin_neon_qi", "int", 8, 16;
"__builtin_neon_hi", "int", 16, 8;
"__builtin_neon_si", "int", 32, 4;
"__builtin_neon_di", "int", 64, 2;
"__builtin_neon_sf", "float", 32, 4;
"__builtin_neon_poly8", "poly", 8, 16;
"__builtin_neon_poly16", "poly", 16, 8;
"__builtin_neon_uqi", "uint", 8, 16;
"__builtin_neon_uhi", "uint", 16, 8;
"__builtin_neon_usi", "uint", 32, 4;
"__builtin_neon_udi", "uint", 64, 2
"__builtin_neon_qi", "int", 8, 16, ALL;
"__builtin_neon_hi", "int", 16, 8, ALL;
"__builtin_neon_si", "int", 32, 4, ALL;
"__builtin_neon_di", "int", 64, 2, ALL;
"__builtin_neon_sf", "float", 32, 4, ALL;
"__builtin_neon_poly8", "poly", 8, 16, ALL;
"__builtin_neon_poly16", "poly", 16, 8, ALL;
"__builtin_neon_poly64", "poly", 64, 2, CRYPTO;
"__builtin_neon_uqi", "uint", 8, 16, ALL;
"__builtin_neon_uhi", "uint", 16, 8, ALL;
"__builtin_neon_usi", "uint", 32, 4, ALL;
"__builtin_neon_udi", "uint", 64, 2, ALL
] in
List.iter
(fun (cbase, abase, esize, enum) ->
(fun (cbase, abase, esize, enum, fpulevel) ->
let attr =
match enum with
1 -> ""
| _ -> Printf.sprintf "\t__attribute__ ((__vector_size__ (%d)))"
(esize * enum / 8) in
Format.printf "typedef %s %s%dx%d_t%s;@\n" cbase abase esize enum attr)
if fpulevel == CRYPTO then
Format.printf "#ifdef __ARM_FEATURE_CRYPTO\n";
Format.printf "typedef %s %s%dx%d_t%s;@\n" cbase abase esize enum attr;
if fpulevel == CRYPTO then
Format.printf "#endif\n";)
typeinfo;
Format.print_newline ();
(* Extra types not in <stdint.h>. *)
Format.printf "typedef float float32_t;\n";
Format.printf "typedef __builtin_neon_poly8 poly8_t;\n";
Format.printf "typedef __builtin_neon_poly16 poly16_t;\n"
Format.printf "typedef __builtin_neon_poly16 poly16_t;\n";
Format.printf "#ifdef __ARM_FEATURE_CRYPTO\n";
Format.printf "typedef __builtin_neon_poly64 poly64_t;\n";
Format.printf "typedef __builtin_neon_poly128 poly128_t;\n";
Format.printf "#endif\n"
(* Output structs containing arrays, for load & store instructions etc. *)
(* Output structs containing arrays, for load & store instructions etc.
poly128_t is deliberately not included here because it has no array types
defined for it. *)
let arrtypes () =
let typeinfo = [
"int", 8; "int", 16;
"int", 32; "int", 64;
"uint", 8; "uint", 16;
"uint", 32; "uint", 64;
"float", 32; "poly", 8;
"poly", 16
"int", 8, ALL; "int", 16, ALL;
"int", 32, ALL; "int", 64, ALL;
"uint", 8, ALL; "uint", 16, ALL;
"uint", 32, ALL; "uint", 64, ALL;
"float", 32, ALL; "poly", 8, ALL;
"poly", 16, ALL; "poly", 64, CRYPTO
] in
let writestruct elname elsize regsize arrsize =
let writestruct elname elsize regsize arrsize fpulevel =
let elnum = regsize / elsize in
let structname =
Printf.sprintf "%s%dx%dx%d_t" elname elsize elnum arrsize in
let sfmt = start_function () in
Format.printf "typedef struct %s" structname;
Format.printf "%stypedef struct %s"
(if fpulevel == CRYPTO then "#ifdef __ARM_FEATURE_CRYPTO\n" else "") structname;
open_braceblock sfmt;
Format.printf "%s%dx%d_t val[%d];" elname elsize elnum arrsize;
close_braceblock sfmt;
Format.printf " %s;" structname;
Format.printf " %s;%s" structname (if fpulevel == CRYPTO then "\n#endif\n" else "");
end_function sfmt;
in
for n = 2 to 4 do
List.iter
(fun (elname, elsize) ->
writestruct elname elsize 64 n;
writestruct elname elsize 128 n)
(fun (elname, elsize, alevel) ->
writestruct elname elsize 64 n alevel;
writestruct elname elsize 128 n alevel)
typeinfo
done
......@@ -491,6 +510,8 @@ let _ =
print_ops ops;
Format.print_newline ();
print_ops reinterp;
print_ops reinterpq;
Format.printf "%s" crypto_intrinsics;
print_lines [
"#ifdef __cplusplus";
"}";
......
gcc/config/arm/neon.md
......@@ -4259,9 +4259,19 @@
DONE;
})
(define_expand "neon_vreinterpretti<mode>"
[(match_operand:TI 0 "s_register_operand" "")
(match_operand:VQXMOV 1 "s_register_operand" "")]
"TARGET_NEON"
{
neon_reinterpret (operands[0], operands[1]);
DONE;
})
(define_expand "neon_vreinterpretv16qi<mode>"
[(match_operand:V16QI 0 "s_register_operand" "")
(match_operand:VQX 1 "s_register_operand" "")]
(match_operand:VQXMOV 1 "s_register_operand" "")]
"TARGET_NEON"
{
neon_reinterpret (operands[0], operands[1]);
......@@ -4270,7 +4280,7 @@
(define_expand "neon_vreinterpretv8hi<mode>"
[(match_operand:V8HI 0 "s_register_operand" "")
(match_operand:VQX 1 "s_register_operand" "")]
(match_operand:VQXMOV 1 "s_register_operand" "")]
"TARGET_NEON"
{
neon_reinterpret (operands[0], operands[1]);
......@@ -4279,7 +4289,7 @@
(define_expand "neon_vreinterpretv4si<mode>"
[(match_operand:V4SI 0 "s_register_operand" "")
(match_operand:VQX 1 "s_register_operand" "")]
(match_operand:VQXMOV 1 "s_register_operand" "")]
"TARGET_NEON"
{
neon_reinterpret (operands[0], operands[1]);
......@@ -4288,7 +4298,7 @@
(define_expand "neon_vreinterpretv4sf<mode>"
[(match_operand:V4SF 0 "s_register_operand" "")
(match_operand:VQX 1 "s_register_operand" "")]
(match_operand:VQXMOV 1 "s_register_operand" "")]
"TARGET_NEON"
{
neon_reinterpret (operands[0], operands[1]);
......@@ -4297,7 +4307,7 @@
(define_expand "neon_vreinterpretv2di<mode>"
[(match_operand:V2DI 0 "s_register_operand" "")
(match_operand:VQX 1 "s_register_operand" "")]
(match_operand:VQXMOV 1 "s_register_operand" "")]
"TARGET_NEON"
{
neon_reinterpret (operands[0], operands[1]);
......
gcc/config/arm/unspecs.md
......@@ -155,6 +155,21 @@
UNSPEC_CRC32CB
UNSPEC_CRC32CH
UNSPEC_CRC32CW
UNSPEC_AESD
UNSPEC_AESE
UNSPEC_AESIMC
UNSPEC_AESMC
UNSPEC_SHA1C
UNSPEC_SHA1M
UNSPEC_SHA1P
UNSPEC_SHA1H
UNSPEC_SHA1SU0
UNSPEC_SHA1SU1
UNSPEC_SHA256H
UNSPEC_SHA256H2
UNSPEC_SHA256SU0
UNSPEC_SHA256SU1
UNSPEC_VMULLP64
UNSPEC_LOAD_COUNT
UNSPEC_VABD
UNSPEC_VABDL
......
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