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riscv-gcc-1
Commit 0218c012 by Uros Bizjak Committed by Uros Bizjak
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i386.md (fix_trunc<mode>di_sse): Remove "x" from "xm" alternative. 

	* config/i386/i386.md (fix_trunc<mode>di_sse): Remove "x" from "xm"
	alternative.
	(fix_trunc<mode>si_sse): Ditto.
	(*floatsisf2_mixed, *floatsisf2_sse): Ditto.
	(*floatsidf2_mixed, *floatsidf2_sse): Ditto.
	(*floatdisf2_mixed, *floatdisf2_sse): Ditto.
	(*floatdidf2_mixed, *floatdidf2_sse): Ditto.
	(floathi<mode>2): Rename from floathisf2 and floathidf2. Macroize
	expander using SSEMODEF mode macro.
	(floatsi<mode>2): Rename from floatsisf2 and floashidf2. Macroize
	expander using SSEMODEF mode macro.
	(*floathi<mode>2_i387): Rename from *floathisf2_i387 and
	*floathidf2_i387. Macroize insn using X87MODEF12 mode macro.
	(*floatsi<mode>2_i387): Rename from *floatsisf2_i387 and
	*floatsidf2_i387. Macroize insn using X87MODEF12 mode macro.
	(*floatdi<mode>2_i387): Rename from *floatdisf2_i387 and
	*floatdidf2_i387. Macroize insn using X87MODEF12 mode macro.
	(float<mode>xf2): Rename from floathixf2, floatsixf2 and floatdixf2.
	Macroize insn using X87MODEF mode macro.

From-SVN: r123693
parent 11202768
Showing with 89 additions and 143 deletions
gcc/ChangeLog
2007-04-10 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (fix_trunc<mode>di_sse): Remove "x" from "xm"
alternative.
(fix_trunc<mode>si_sse): Ditto.
(*floatsisf2_mixed, *floatsisf2_sse): Ditto.
(*floatsidf2_mixed, *floatsidf2_sse): Ditto.
(*floatdisf2_mixed, *floatdisf2_sse): Ditto.
(*floatdidf2_mixed, *floatdidf2_sse): Ditto.
(floathi<mode>2): Rename from floathisf2 and floathidf2. Macroize
expander using SSEMODEF mode macro.
(floatsi<mode>2): Rename from floatsisf2 and floashidf2. Macroize
expander using SSEMODEF mode macro.
(*floathi<mode>2_i387): Rename from *floathisf2_i387 and
*floathidf2_i387. Macroize insn using X87MODEF12 mode macro.
(*floatsi<mode>2_i387): Rename from *floatsisf2_i387 and
*floatsidf2_i387. Macroize insn using X87MODEF12 mode macro.
(*floatdi<mode>2_i387): Rename from *floatdisf2_i387 and
*floatdidf2_i387. Macroize insn using X87MODEF12 mode macro.
(float<mode>xf2): Rename from floathixf2, floatsixf2 and floatdixf2.
Macroize insn using X87MODEF mode macro.
2007-04-09 H.J. Lu <hongjiu.lu@intel.com> 2007-04-09 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/sse.md (sse2_pinsrw): Removed. * config/i386/sse.md (sse2_pinsrw): Removed.
......
gcc/config/i386/i386.md
...@@ -4184,7 +4184,7 @@ ...@@ -4184,7 +4184,7 @@
;; When SSE is available, it is always faster to use it! ;; When SSE is available, it is always faster to use it!
(define_insn "fix_trunc<mode>di_sse" (define_insn "fix_trunc<mode>di_sse"
[(set (match_operand:DI 0 "register_operand" "=r,r") [(set (match_operand:DI 0 "register_operand" "=r,r")
(fix:DI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,xm")))] (fix:DI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,m")))]
"TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) "TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode)
&& (!TARGET_FISTTP || TARGET_SSE_MATH)" && (!TARGET_FISTTP || TARGET_SSE_MATH)"
"cvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}" "cvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
...@@ -4195,7 +4195,7 @@ ...@@ -4195,7 +4195,7 @@
(define_insn "fix_trunc<mode>si_sse" (define_insn "fix_trunc<mode>si_sse"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(fix:SI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,xm")))] (fix:SI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,m")))]
"SSE_FLOAT_MODE_P (<MODE>mode) "SSE_FLOAT_MODE_P (<MODE>mode)
&& (!TARGET_FISTTP || TARGET_SSE_MATH)" && (!TARGET_FISTTP || TARGET_SSE_MATH)"
"cvtts<ssemodefsuffix>2si\t{%1, %0|%0, %1}" "cvtts<ssemodefsuffix>2si\t{%1, %0|%0, %1}"
...@@ -4482,40 +4482,44 @@ ...@@ -4482,40 +4482,44 @@
;; Even though we only accept memory inputs, the backend _really_ ;; Even though we only accept memory inputs, the backend _really_
;; wants to be able to do this between registers. ;; wants to be able to do this between registers.
(define_expand "floathisf2" (define_expand "floathi<mode>2"
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SSEMODEF 0 "register_operand" "")
(float:SF (match_operand:HI 1 "nonimmediate_operand" "")))] (float:SSEMODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
"TARGET_80387 || TARGET_SSE_MATH" "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{ {
if (TARGET_SSE_MATH) if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
{ {
emit_insn (gen_floatsisf2 (operands[0], emit_insn
convert_to_mode (SImode, operands[1], 0))); (gen_floatsi<mode>2 (operands[0],
convert_to_mode (SImode, operands[1], 0)));
DONE; DONE;
} }
}) })
(define_insn "*floathisf2_i387" (define_insn "*floathi<mode>2_i387"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
(float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))] (float:X87MODEF12
"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)" (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)"
"@ "@
fild%z1\t%1 fild%z1\t%1
#" #"
[(set_attr "type" "fmov,multi") [(set_attr "type" "fmov,multi")
(set_attr "mode" "SF") (set_attr "mode" "<MODE>")
(set_attr "unit" "*,i387") (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_expand "floatsisf2" (define_expand "floatsi<mode>2"
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SSEMODEF 0 "register_operand" "")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] (float:SSEMODEF (match_operand:SI 1 "nonimmediate_operand" "")))]
"TARGET_80387 || TARGET_SSE_MATH" "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"") "")
(define_insn "*floatsisf2_mixed" (define_insn "*floatsisf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f,?f,x,x") [(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))] (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,m")))]
"TARGET_MIX_SSE_I387" "TARGET_MIX_SSE_I387"
"@ "@
fild%z1\t%1 fild%z1\t%1
...@@ -4531,7 +4535,7 @@ ...@@ -4531,7 +4535,7 @@
(define_insn "*floatsisf2_sse" (define_insn "*floatsisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x,x") [(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))] (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
"TARGET_SSE_MATH" "TARGET_SSE_MATH"
"cvtsi2ss\t{%1, %0|%0, %1}" "cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
...@@ -4540,15 +4544,43 @@ ...@@ -4540,15 +4544,43 @@
(set_attr "amdfam10_decode" "vector,double") (set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatsisf2_i387" (define_insn "*floatsidf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))] (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,m")))]
"TARGET_SSE2 && TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
cvtsi2sd\t{%1, %0|%0, %1}
cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "DF")
(set_attr "unit" "*,i387,*,*")
(set_attr "athlon_decode" "*,*,double,direct")
(set_attr "amdfam10_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")])
(define_insn "*floatsidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=x,x")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
"TARGET_SSE2 && TARGET_SSE_MATH"
"cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")])
(define_insn "*floatsi<mode>2_i387"
[(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
(float:X87MODEF12
(match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387" "TARGET_80387"
"@ "@
fild%z1\t%1 fild%z1\t%1
#" #"
[(set_attr "type" "fmov,multi") [(set_attr "type" "fmov,multi")
(set_attr "mode" "SF") (set_attr "mode" "<MODE>")
(set_attr "unit" "*,i387") (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
...@@ -4560,7 +4592,7 @@ ...@@ -4560,7 +4592,7 @@
(define_insn "*floatdisf2_mixed" (define_insn "*floatdisf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f,?f,x,x") [(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))] (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,m")))]
"TARGET_64BIT && TARGET_MIX_SSE_I387" "TARGET_64BIT && TARGET_MIX_SSE_I387"
"@ "@
fild%z1\t%1 fild%z1\t%1
...@@ -4576,7 +4608,7 @@ ...@@ -4576,7 +4608,7 @@
(define_insn "*floatdisf2_sse" (define_insn "*floatdisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x,x") [(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))] (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,m")))]
"TARGET_64BIT && TARGET_SSE_MATH" "TARGET_64BIT && TARGET_SSE_MATH"
"cvtsi2ss{q}\t{%1, %0|%0, %1}" "cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
...@@ -4585,88 +4617,6 @@ ...@@ -4585,88 +4617,6 @@
(set_attr "amdfam10_decode" "vector,double") (set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatdisf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "SF")
(set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_expand "floathidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
if (TARGET_SSE2 && TARGET_SSE_MATH)
{
emit_insn (gen_floatsidf2 (operands[0],
convert_to_mode (SImode, operands[1], 0)));
DONE;
}
})
(define_insn "*floathidf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
"@
fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "DF")
(set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_insn "*floatsidf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
"TARGET_SSE2 && TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
cvtsi2sd\t{%1, %0|%0, %1}
cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "DF")
(set_attr "unit" "*,i387,*,*")
(set_attr "athlon_decode" "*,*,double,direct")
(set_attr "amdfam10_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")])
(define_insn "*floatsidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=x,x")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
"TARGET_SSE2 && TARGET_SSE_MATH"
"cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")])
(define_insn "*floatsidf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "DF")
(set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_expand "floatdidf2" (define_expand "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "") [(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
...@@ -4681,7 +4631,7 @@ ...@@ -4681,7 +4631,7 @@
(define_insn "*floatdidf2_mixed" (define_insn "*floatdidf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f,?f,x,x") [(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))] (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,m")))]
"TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387" "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
"@ "@
fild%z1\t%1 fild%z1\t%1
...@@ -4697,7 +4647,7 @@ ...@@ -4697,7 +4647,7 @@
(define_insn "*floatdidf2_sse" (define_insn "*floatdidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=x,x") [(set (match_operand:DF 0 "register_operand" "=x,x")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))] (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,m")))]
"TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH" "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
"cvtsi2sd{q}\t{%1, %0|%0, %1}" "cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
...@@ -4706,45 +4656,22 @@ ...@@ -4706,45 +4656,22 @@
(set_attr "amdfam10_decode" "vector,double") (set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatdidf2_i387" (define_insn "*floatdi<mode>2_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))] (float:X87MODEF12
(match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387" "TARGET_80387"
"@ "@
fild%z1\t%1 fild%z1\t%1
#" #"
[(set_attr "type" "fmov,multi") [(set_attr "type" "fmov,multi")
(set_attr "mode" "DF") (set_attr "mode" "<MODE>")
(set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_insn "floathixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_insn "floatsixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(set_attr "unit" "*,i387") (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "floatdixf2" (define_insn "float<mode>xf2"
[(set (match_operand:XF 0 "register_operand" "=f,f") [(set (match_operand:XF 0 "register_operand" "=f,f")
(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))] (float:XF (match_operand:X87MODEI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387" "TARGET_80387"
"@ "@
fild%z1\t%1 fild%z1\t%1
...@@ -4807,9 +4734,6 @@ ...@@ -4807,9 +4734,6 @@
DONE; DONE;
}) })
;; SSE extract/set expanders
;; Add instructions ;; Add instructions
;; %%% splits for addditi3 ;; %%% splits for addditi3
......
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