Skip to content

R
riscv-gcc-1
Commit 015a2622 by Uros Bizjak
Options

* config/i386/i386.md 

	(*float<SWI48x:mode><MODEF:mode>2_mixed_with_temp): Use SWI48 mode
	iterator instead of SWI48x.  Update insn constraint.
	(*float<SWI48x:mode><MODEF:mode>2_mixed_interunit): Ditto.
	(*float<SWI48x:mode><MODEF:mode>2_mixed_nointerunit): Ditto.
	(*float<SWI48x:mode><MODEF:mode>2_sse_with_temp): Ditto.
	(*float<SWI48x:mode><MODEF:mode>2_sse_interunit): Ditto.
	(*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit): Ditto.
	(*float<SWI48x:mode><MODEF:mode>2 splitters): Ditto.
	(lrint<MODEF:mode><SWI48x:mode>2): Ditto.

From-SVN: r193692
parent c3e3d235
Showing with 64 additions and 62 deletions
gcc/ChangeLog
2012-11-21 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md
(*float<SWI48x:mode><MODEF:mode>2_mixed_with_temp): Use SWI48 mode
iterator instead of SWI48x. Update insn constraint.
(*float<SWI48x:mode><MODEF:mode>2_mixed_interunit): Ditto.
(*float<SWI48x:mode><MODEF:mode>2_mixed_nointerunit): Ditto.
(*float<SWI48x:mode><MODEF:mode>2_sse_with_temp): Ditto.
(*float<SWI48x:mode><MODEF:mode>2_sse_interunit): Ditto.
(*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit): Ditto.
(*float<SWI48x:mode><MODEF:mode>2 splitters): Ditto.
(lrint<MODEF:mode><SWI48x:mode>2): Ditto.
2012-11-21 Marcus Shawcroft <marcus.shawcroft@arm.com> 2012-11-21 Marcus Shawcroft <marcus.shawcroft@arm.com>
* Makefile.in (gengtype-lex.o): Add dependency on $(BCONFIG_H). * Makefile.in (gengtype-lex.o): Add dependency on $(BCONFIG_H).
...@@ -95,13 +108,14 @@ ...@@ -95,13 +108,14 @@
(peephole2 to shorten x87->SSE reload sequences): Remove peephole2. (peephole2 to shorten x87->SSE reload sequences): Remove peephole2.
* config/i386/i386.h (enum ix86_tune_indices) * config/i386/i386.h (enum ix86_tune_indices)
<IX86_TUNE_SHORTEN_X87_SSE>: Remove. <IX86_TUNE_SHORTEN_X87_SSE>: Remove.
* config/i386/i386.h (initial_ix86_tune_features): Update. (TARGET_SHORTEN_X87_SSE): Remove.
* config/i386/i386.c (initial_ix86_tune_features): Update.
2012-11-20 Vladimir Makarov <vmakarov@redhat.com> 2012-11-20 Vladimir Makarov <vmakarov@redhat.com>
PR target/19398 PR target/19398
* lra-constraints.c (process_alt_operands): Discourage reloads * lra-constraints.c (process_alt_operands): Discourage reloads
through secodnary memory. through secondary memory.
2012-11-20 David Edelsohn <dje.gcc@gmail.com> 2012-11-20 David Edelsohn <dje.gcc@gmail.com>
gcc/config/i386/i386.md
...@@ -4906,13 +4906,12 @@ ...@@ -4906,13 +4906,12 @@
(set_attr "bdver1_decode" "*,direct") (set_attr "bdver1_decode" "*,direct")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_with_temp" (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed_with_temp"
[(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x") [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x")
(float:MODEF (float:MODEF
(match_operand:SWI48x 1 "nonimmediate_operand" "m,?r,r,m"))) (match_operand:SWI48 1 "nonimmediate_operand" "m,?r,r,m")))
(clobber (match_operand:SWI48x 2 "memory_operand" "=X,m,m,X"))] (clobber (match_operand:SWI48 2 "memory_operand" "=X,m,m,X"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387"
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387"
"#" "#"
[(set_attr "type" "fmov,multi,sseicvt,sseicvt") [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "<MODEF:MODE>") (set_attr "mode" "<MODEF:MODE>")
...@@ -4924,10 +4923,9 @@ ...@@ -4924,10 +4923,9 @@
(define_split (define_split
[(set (match_operand:MODEF 0 "register_operand") [(set (match_operand:MODEF 0 "register_operand")
(float:MODEF (match_operand:SWI48x 1 "register_operand"))) (float:MODEF (match_operand:SWI48 1 "register_operand")))
(clobber (match_operand:SWI48x 2 "memory_operand"))] (clobber (match_operand:SWI48 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& TARGET_INTER_UNIT_CONVERSIONS && TARGET_INTER_UNIT_CONVERSIONS
&& reload_completed && reload_completed
&& (SSE_REG_P (operands[0]) && (SSE_REG_P (operands[0])
...@@ -4937,10 +4935,9 @@ ...@@ -4937,10 +4935,9 @@
(define_split (define_split
[(set (match_operand:MODEF 0 "register_operand") [(set (match_operand:MODEF 0 "register_operand")
(float:MODEF (match_operand:SWI48x 1 "register_operand"))) (float:MODEF (match_operand:SWI48 1 "register_operand")))
(clobber (match_operand:SWI48x 2 "memory_operand"))] (clobber (match_operand:SWI48 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed && reload_completed
&& (SSE_REG_P (operands[0]) && (SSE_REG_P (operands[0])
...@@ -4949,24 +4946,23 @@ ...@@ -4949,24 +4946,23 @@
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (float:MODEF (match_dup 2)))]) (set (match_dup 0) (float:MODEF (match_dup 2)))])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_interunit" (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed_interunit"
[(set (match_operand:MODEF 0 "register_operand" "=f,x,x") [(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
(float:MODEF (float:MODEF
(match_operand:SWI48x 1 "nonimmediate_operand" "m,r,m")))] (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))" && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
"@ "@
fild%Z1\t%1 fild%Z1\t%1
%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1} %vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}
%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}" %vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "fmov,sseicvt,sseicvt") [(set_attr "type" "fmov,sseicvt,sseicvt")
(set_attr "prefix" "orig,maybe_vex,maybe_vex") (set_attr "prefix" "orig,maybe_vex,maybe_vex")
(set_attr "mode" "<MODEF:MODE>") (set_attr "mode" "<MODEF:MODE>")
(set (attr "prefix_rex") (set (attr "prefix_rex")
(if_then_else (if_then_else
(and (eq_attr "prefix" "maybe_vex") (and (eq_attr "prefix" "maybe_vex")
(match_test "<SWI48x:MODE>mode == DImode")) (match_test "<SWI48:MODE>mode == DImode"))
(const_string "1") (const_string "1")
(const_string "*"))) (const_string "*")))
(set_attr "unit" "i387,*,*") (set_attr "unit" "i387,*,*")
...@@ -4975,23 +4971,22 @@ ...@@ -4975,23 +4971,22 @@
(set_attr "bdver1_decode" "*,double,direct") (set_attr "bdver1_decode" "*,double,direct")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_nointerunit" (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed_nointerunit"
[(set (match_operand:MODEF 0 "register_operand" "=f,x") [(set (match_operand:MODEF 0 "register_operand" "=f,x")
(float:MODEF (float:MODEF
(match_operand:SWI48x 1 "memory_operand" "m,m")))] (match_operand:SWI48 1 "memory_operand" "m,m")))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))" && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
"@ "@
fild%Z1\t%1 fild%Z1\t%1
%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}" %vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "fmov,sseicvt") [(set_attr "type" "fmov,sseicvt")
(set_attr "prefix" "orig,maybe_vex") (set_attr "prefix" "orig,maybe_vex")
(set_attr "mode" "<MODEF:MODE>") (set_attr "mode" "<MODEF:MODE>")
(set (attr "prefix_rex") (set (attr "prefix_rex")
(if_then_else (if_then_else
(and (eq_attr "prefix" "maybe_vex") (and (eq_attr "prefix" "maybe_vex")
(match_test "<SWI48x:MODE>mode == DImode")) (match_test "<SWI48:MODE>mode == DImode"))
(const_string "1") (const_string "1")
(const_string "*"))) (const_string "*")))
(set_attr "athlon_decode" "*,direct") (set_attr "athlon_decode" "*,direct")
...@@ -5165,13 +5160,12 @@ ...@@ -5165,13 +5160,12 @@
DONE; DONE;
}) })
(define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_with_temp" (define_insn "*float<SWI48:mode><MODEF:mode>2_sse_with_temp"
[(set (match_operand:MODEF 0 "register_operand" "=x,x") [(set (match_operand:MODEF 0 "register_operand" "=x,x")
(float:MODEF (float:MODEF
(match_operand:SWI48x 1 "nonimmediate_operand" "r,m"))) (match_operand:SWI48 1 "nonimmediate_operand" "r,m")))
(clobber (match_operand:SWI48x 2 "memory_operand" "=m,X"))] (clobber (match_operand:SWI48 2 "memory_operand" "=m,X"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
"#" "#"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "<MODEF:MODE>") (set_attr "mode" "<MODEF:MODE>")
...@@ -5180,21 +5174,20 @@ ...@@ -5180,21 +5174,20 @@
(set_attr "bdver1_decode" "double,direct") (set_attr "bdver1_decode" "double,direct")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_interunit" (define_insn "*float<SWI48:mode><MODEF:mode>2_sse_interunit"
[(set (match_operand:MODEF 0 "register_operand" "=x,x") [(set (match_operand:MODEF 0 "register_operand" "=x,x")
(float:MODEF (float:MODEF
(match_operand:SWI48x 1 "nonimmediate_operand" "r,m")))] (match_operand:SWI48 1 "nonimmediate_operand" "r,m")))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))" && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
"%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}" "%vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
(set_attr "prefix" "maybe_vex") (set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODEF:MODE>") (set_attr "mode" "<MODEF:MODE>")
(set (attr "prefix_rex") (set (attr "prefix_rex")
(if_then_else (if_then_else
(and (eq_attr "prefix" "maybe_vex") (and (eq_attr "prefix" "maybe_vex")
(match_test "<SWI48x:MODE>mode == DImode")) (match_test "<SWI48:MODE>mode == DImode"))
(const_string "1") (const_string "1")
(const_string "*"))) (const_string "*")))
(set_attr "athlon_decode" "double,direct") (set_attr "athlon_decode" "double,direct")
...@@ -5204,10 +5197,9 @@ ...@@ -5204,10 +5197,9 @@
(define_split (define_split
[(set (match_operand:MODEF 0 "register_operand") [(set (match_operand:MODEF 0 "register_operand")
(float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand"))) (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))
(clobber (match_operand:SWI48x 2 "memory_operand"))] (clobber (match_operand:SWI48 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed && reload_completed
&& (SSE_REG_P (operands[0]) && (SSE_REG_P (operands[0])
...@@ -5215,21 +5207,20 @@ ...@@ -5215,21 +5207,20 @@
&& SSE_REG_P (SUBREG_REG (operands[0]))))" && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 0) (float:MODEF (match_dup 1)))]) [(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit" (define_insn "*float<SWI48:mode><MODEF:mode>2_sse_nointerunit"
[(set (match_operand:MODEF 0 "register_operand" "=x") [(set (match_operand:MODEF 0 "register_operand" "=x")
(float:MODEF (float:MODEF
(match_operand:SWI48x 1 "memory_operand" "m")))] (match_operand:SWI48 1 "memory_operand" "m")))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))" && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
"%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}" "%vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
(set_attr "prefix" "maybe_vex") (set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODEF:MODE>") (set_attr "mode" "<MODEF:MODE>")
(set (attr "prefix_rex") (set (attr "prefix_rex")
(if_then_else (if_then_else
(and (eq_attr "prefix" "maybe_vex") (and (eq_attr "prefix" "maybe_vex")
(match_test "<SWI48x:MODE>mode == DImode")) (match_test "<SWI48:MODE>mode == DImode"))
(const_string "1") (const_string "1")
(const_string "*"))) (const_string "*")))
(set_attr "athlon_decode" "direct") (set_attr "athlon_decode" "direct")
...@@ -5239,10 +5230,9 @@ ...@@ -5239,10 +5230,9 @@
(define_split (define_split
[(set (match_operand:MODEF 0 "register_operand") [(set (match_operand:MODEF 0 "register_operand")
(float:MODEF (match_operand:SWI48x 1 "register_operand"))) (float:MODEF (match_operand:SWI48 1 "register_operand")))
(clobber (match_operand:SWI48x 2 "memory_operand"))] (clobber (match_operand:SWI48 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed && reload_completed
&& (SSE_REG_P (operands[0]) && (SSE_REG_P (operands[0])
...@@ -5253,10 +5243,9 @@ ...@@ -5253,10 +5243,9 @@
(define_split (define_split
[(set (match_operand:MODEF 0 "register_operand") [(set (match_operand:MODEF 0 "register_operand")
(float:MODEF (match_operand:SWI48x 1 "memory_operand"))) (float:MODEF (match_operand:SWI48 1 "memory_operand")))
(clobber (match_operand:SWI48x 2 "memory_operand"))] (clobber (match_operand:SWI48 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& reload_completed && reload_completed
&& (SSE_REG_P (operands[0]) && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG || (GET_CODE (operands[0]) == SUBREG
...@@ -14867,12 +14856,11 @@ ...@@ -14867,12 +14856,11 @@
UNSPEC_FIST))] UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387") "TARGET_USE_FANCY_MATH_387")
(define_expand "lrint<MODEF:mode><SWI48x:mode>2" (define_expand "lrint<MODEF:mode><SWI48:mode>2"
[(set (match_operand:SWI48x 0 "nonimmediate_operand") [(set (match_operand:SWI48 0 "nonimmediate_operand")
(unspec:SWI48x [(match_operand:MODEF 1 "register_operand")] (unspec:SWI48 [(match_operand:MODEF 1 "register_operand")]
UNSPEC_FIX_NOTRUNC))] UNSPEC_FIX_NOTRUNC))]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH")
&& ((<SWI48x:MODE>mode != DImode) || TARGET_64BIT)")
(define_expand "lround<X87MODEF:mode><SWI248x:mode>2" (define_expand "lround<X87MODEF:mode><SWI248x:mode>2"
[(match_operand:SWI248x 0 "nonimmediate_operand") [(match_operand:SWI248x 0 "nonimmediate_operand")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment