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Commit 008a11cc by Tamar Christina Committed by Tamar Christina
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re PR target/82641 (Unable to enable crc32 for a certain function with target… 

re PR target/82641 (Unable to enable crc32 for a certain function with target attribute on ARM (aarch32))

2017-11-10  Tamar Christina  <tamar.christina@arm.com>

	PR target/82641
	* config/arm/arm.c
	(arm_option_override): Refactor.
	(arm_option_reconfigure_globals): New.
	(arm_options_perform_arch_sanity_checks): New.
	* config/arm/arm-protos.h (arm_option_reconfigure_globals): New prototype.
	(arm_options_perform_arch_sanity_checks): Likewise

From-SVN: r254632
parent cd764269
Showing with 161 additions and 132 deletions
gcc/ChangeLog
2017-11-10 Tamar Christina <tamar.christina@arm.com>
PR target/82641
* config/arm/arm.c
(arm_option_override): Refactor.
(arm_option_reconfigure_globals): New.
(arm_options_perform_arch_sanity_checks): New.
* config/arm/arm-protos.h (arm_option_reconfigure_globals): New prototype.
(arm_options_perform_arch_sanity_checks): Likewise
2017-11-10 Pat Haugen <pthaugen@us.ibm.com> 2017-11-10 Pat Haugen <pthaugen@us.ibm.com>
* rs6000/power9.md (power9-qpdiv): Correct DFU pipe usage. * rs6000/power9.md (power9-qpdiv): Correct DFU pipe usage.
gcc/config/arm/arm-protos.h
...@@ -224,6 +224,8 @@ extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *, ...@@ -224,6 +224,8 @@ extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
extern void arm_configure_build_target (struct arm_build_target *, extern void arm_configure_build_target (struct arm_build_target *,
struct cl_target_option *, struct cl_target_option *,
struct gcc_options *, bool); struct gcc_options *, bool);
extern void arm_option_reconfigure_globals (void);
extern void arm_options_perform_arch_sanity_checks (void);
extern void arm_pr_long_calls (struct cpp_reader *); extern void arm_pr_long_calls (struct cpp_reader *);
extern void arm_pr_no_long_calls (struct cpp_reader *); extern void arm_pr_no_long_calls (struct cpp_reader *);
extern void arm_pr_long_calls_off (struct cpp_reader *); extern void arm_pr_long_calls_off (struct cpp_reader *);
......
gcc/config/arm/arm.c
...@@ -3335,8 +3335,9 @@ arm_option_override (void) ...@@ -3335,8 +3335,9 @@ arm_option_override (void)
SUBTARGET_OVERRIDE_OPTIONS; SUBTARGET_OVERRIDE_OPTIONS;
#endif #endif
sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_active_target.arch_pp_name); /* Initialize boolean versions of the architectural flags, for use
arm_base_arch = arm_active_target.base_arch; in the arm.md file and for enabling feature flags. */
arm_option_reconfigure_globals ();
arm_tune = arm_active_target.tune_core; arm_tune = arm_active_target.tune_core;
tune_flags = arm_active_target.tune_flags; tune_flags = arm_active_target.tune_flags;
...@@ -3346,16 +3347,6 @@ arm_option_override (void) ...@@ -3346,16 +3347,6 @@ arm_option_override (void)
if (TARGET_APCS_FRAME) if (TARGET_APCS_FRAME)
flag_shrink_wrap = false; flag_shrink_wrap = false;
/* BPABI targets use linker tricks to allow interworking on cores
without thumb support. */
if (TARGET_INTERWORK
&& !TARGET_BPABI
&& !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb))
{
warning (0, "target CPU does not support interworking" );
target_flags &= ~MASK_INTERWORK;
}
if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
{ {
warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
...@@ -3371,43 +3362,6 @@ arm_option_override (void) ...@@ -3371,43 +3362,6 @@ arm_option_override (void)
if (TARGET_APCS_REENT) if (TARGET_APCS_REENT)
warning (0, "APCS reentrant code not supported. Ignored"); warning (0, "APCS reentrant code not supported. Ignored");
/* Initialize boolean versions of the architectural flags, for use
in the arm.md file. */
arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m);
arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4);
arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5);
arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5e);
arm_arch5te = arm_arch5e
&& bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6);
arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6k);
arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm);
arm_arch6m = arm_arch6 && !arm_arch_notm;
arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7);
arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7em);
arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8);
arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_1);
arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_2);
arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2);
arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale);
arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt);
arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2);
arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv);
arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv);
arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32);
arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse);
arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16);
arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae);
if (arm_fp16_inst)
{
if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
error ("selected fp16 options are incompatible");
arm_fp16_format = ARM_FP16_FORMAT_IEEE;
}
/* Set up some tuning parameters. */ /* Set up some tuning parameters. */
arm_ld_sched = (tune_flags & TF_LDSCHED) != 0; arm_ld_sched = (tune_flags & TF_LDSCHED) != 0;
arm_tune_strongarm = (tune_flags & TF_STRONG) != 0; arm_tune_strongarm = (tune_flags & TF_STRONG) != 0;
...@@ -3416,86 +3370,11 @@ arm_option_override (void) ...@@ -3416,86 +3370,11 @@ arm_option_override (void)
arm_tune_cortex_a9 = (arm_tune == TARGET_CPU_cortexa9) != 0; arm_tune_cortex_a9 = (arm_tune == TARGET_CPU_cortexa9) != 0;
arm_m_profile_small_mul = (tune_flags & TF_SMALLMUL) != 0; arm_m_profile_small_mul = (tune_flags & TF_SMALLMUL) != 0;
/* And finally, set up some quirks. */
arm_arch_no_volatile_ce
= bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_no_volatile_ce);
arm_arch6kz = arm_arch6k && bitmap_bit_p (arm_active_target.isa,
isa_bit_quirk_armv6kz);
/* V5 code we generate is completely interworking capable, so we turn off
TARGET_INTERWORK here to avoid many tests later on. */
/* XXX However, we must pass the right pre-processor defines to CPP
or GLD can get confused. This is a hack. */
if (TARGET_INTERWORK)
arm_cpp_interwork = 1;
if (arm_arch5)
target_flags &= ~MASK_INTERWORK;
if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
error ("iwmmxt abi requires an iwmmxt capable cpu");
/* If soft-float is specified then don't use FPU. */
if (TARGET_SOFT_FLOAT)
arm_fpu_attr = FPU_NONE;
else
arm_fpu_attr = FPU_VFP;
if (TARGET_AAPCS_BASED)
{
if (TARGET_CALLER_INTERWORKING)
error ("AAPCS does not support -mcaller-super-interworking");
else
if (TARGET_CALLEE_INTERWORKING)
error ("AAPCS does not support -mcallee-super-interworking");
}
/* __fp16 support currently assumes the core has ldrh. */
if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
sorry ("__fp16 and no ldrh");
if (TARGET_AAPCS_BASED)
{
if (arm_abi == ARM_ABI_IWMMXT)
arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
else if (TARGET_HARD_FLOAT_ABI)
{
arm_pcs_default = ARM_PCS_AAPCS_VFP;
if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2))
error ("-mfloat-abi=hard: selected processor lacks an FPU");
}
else
arm_pcs_default = ARM_PCS_AAPCS;
}
else
{
if (arm_float_abi == ARM_FLOAT_ABI_HARD)
sorry ("-mfloat-abi=hard and VFP");
if (arm_abi == ARM_ABI_APCS)
arm_pcs_default = ARM_PCS_APCS;
else
arm_pcs_default = ARM_PCS_ATPCS;
}
/* For arm2/3 there is no need to do any scheduling if we are doing /* For arm2/3 there is no need to do any scheduling if we are doing
software floating-point. */ software floating-point. */
if (TARGET_SOFT_FLOAT && (tune_flags & TF_NO_MODE32)) if (TARGET_SOFT_FLOAT && (tune_flags & TF_NO_MODE32))
flag_schedule_insns = flag_schedule_insns_after_reload = 0; flag_schedule_insns = flag_schedule_insns_after_reload = 0;
/* Use the cp15 method if it is available. */
if (target_thread_pointer == TP_AUTO)
{
if (arm_arch6k && !TARGET_THUMB1)
target_thread_pointer = TP_CP15;
else
target_thread_pointer = TP_SOFT;
}
/* Override the default structure alignment for AAPCS ABI. */ /* Override the default structure alignment for AAPCS ABI. */
if (!global_options_set.x_arm_structure_size_boundary) if (!global_options_set.x_arm_structure_size_boundary)
{ {
...@@ -3669,14 +3548,6 @@ arm_option_override (void) ...@@ -3669,14 +3548,6 @@ arm_option_override (void)
if (target_slow_flash_data || target_pure_code) if (target_slow_flash_data || target_pure_code)
arm_disable_literal_pool = true; arm_disable_literal_pool = true;
if (use_cmse && !arm_arch_cmse)
error ("target CPU does not support ARMv8-M Security Extensions");
/* We don't clear D16-D31 VFP registers for cmse_nonsecure_call functions
and ARMv8-M Baseline and Mainline do not allow such configuration. */
if (use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM)
error ("ARMv8-M Security Extensions incompatible with selected FPU");
/* Disable scheduling fusion by default if it's not armv7 processor /* Disable scheduling fusion by default if it's not armv7 processor
or doesn't prefer ldrd/strd. */ or doesn't prefer ldrd/strd. */
if (flag_schedule_fusion == 2 if (flag_schedule_fusion == 2
...@@ -3686,6 +3557,7 @@ arm_option_override (void) ...@@ -3686,6 +3557,7 @@ arm_option_override (void)
/* Need to remember initial options before they are overriden. */ /* Need to remember initial options before they are overriden. */
init_optimize = build_optimization_node (&global_options); init_optimize = build_optimization_node (&global_options);
arm_options_perform_arch_sanity_checks ();
arm_option_override_internal (&global_options, &global_options_set); arm_option_override_internal (&global_options, &global_options_set);
arm_option_check_internal (&global_options); arm_option_check_internal (&global_options);
arm_option_params_internal (); arm_option_params_internal ();
...@@ -3701,6 +3573,151 @@ arm_option_override (void) ...@@ -3701,6 +3573,151 @@ arm_option_override (void)
thumb_flipper = TARGET_THUMB; thumb_flipper = TARGET_THUMB;
} }
/* Reconfigure global status flags from the active_target.isa. */
void
arm_option_reconfigure_globals (void)
{
sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_active_target.arch_pp_name);
arm_base_arch = arm_active_target.base_arch;
/* Initialize boolean versions of the architectural flags, for use
in the arm.md file. */
arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m);
arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4);
arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5);
arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5e);
arm_arch5te = arm_arch5e
&& bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6);
arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6k);
arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm);
arm_arch6m = arm_arch6 && !arm_arch_notm;
arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7);
arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7em);
arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8);
arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_1);
arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_2);
arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2);
arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale);
arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt);
arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2);
arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv);
arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv);
arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32);
arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse);
arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16);
arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae);
if (arm_fp16_inst)
{
if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
error ("selected fp16 options are incompatible");
arm_fp16_format = ARM_FP16_FORMAT_IEEE;
}
/* And finally, set up some quirks. */
arm_arch_no_volatile_ce
= bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_no_volatile_ce);
arm_arch6kz = arm_arch6k && bitmap_bit_p (arm_active_target.isa,
isa_bit_quirk_armv6kz);
/* Use the cp15 method if it is available. */
if (target_thread_pointer == TP_AUTO)
{
if (arm_arch6k && !TARGET_THUMB1)
target_thread_pointer = TP_CP15;
else
target_thread_pointer = TP_SOFT;
}
}
/* Perform some validation between the desired architecture and the rest of the
options. */
void
arm_options_perform_arch_sanity_checks (void)
{
/* V5 code we generate is completely interworking capable, so we turn off
TARGET_INTERWORK here to avoid many tests later on. */
/* XXX However, we must pass the right pre-processor defines to CPP
or GLD can get confused. This is a hack. */
if (TARGET_INTERWORK)
arm_cpp_interwork = 1;
if (arm_arch5)
target_flags &= ~MASK_INTERWORK;
if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
error ("iwmmxt abi requires an iwmmxt capable cpu");
/* BPABI targets use linker tricks to allow interworking on cores
without thumb support. */
if (TARGET_INTERWORK
&& !TARGET_BPABI
&& !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb))
{
warning (0, "target CPU does not support interworking" );
target_flags &= ~MASK_INTERWORK;
}
/* If soft-float is specified then don't use FPU. */
if (TARGET_SOFT_FLOAT)
arm_fpu_attr = FPU_NONE;
else
arm_fpu_attr = FPU_VFP;
if (TARGET_AAPCS_BASED)
{
if (TARGET_CALLER_INTERWORKING)
error ("AAPCS does not support -mcaller-super-interworking");
else
if (TARGET_CALLEE_INTERWORKING)
error ("AAPCS does not support -mcallee-super-interworking");
}
/* __fp16 support currently assumes the core has ldrh. */
if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
sorry ("__fp16 and no ldrh");
if (use_cmse && !arm_arch_cmse)
error ("target CPU does not support ARMv8-M Security Extensions");
/* We don't clear D16-D31 VFP registers for cmse_nonsecure_call functions
and ARMv8-M Baseline and Mainline do not allow such configuration. */
if (use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM)
error ("ARMv8-M Security Extensions incompatible with selected FPU");
if (TARGET_AAPCS_BASED)
{
if (arm_abi == ARM_ABI_IWMMXT)
arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
else if (TARGET_HARD_FLOAT_ABI)
{
arm_pcs_default = ARM_PCS_AAPCS_VFP;
if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2))
error ("-mfloat-abi=hard: selected processor lacks an FPU");
}
else
arm_pcs_default = ARM_PCS_AAPCS;
}
else
{
if (arm_float_abi == ARM_FLOAT_ABI_HARD)
sorry ("-mfloat-abi=hard and VFP");
if (arm_abi == ARM_ABI_APCS)
arm_pcs_default = ARM_PCS_APCS;
else
arm_pcs_default = ARM_PCS_ATPCS;
}
}
static void static void
arm_add_gc_roots (void) arm_add_gc_roots (void)
{ {
......
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