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riscv-gcc-1
Commit 003bb7f3 by James Greenhalgh Committed by James Greenhalgh
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[AArch64, AArch32][Insn classification refactoring 6/N] Remove "neon_type" attribute 

gcc/
	* config/aarch64/aarch64.md: Rename r_2_f and f_2_r where appropriate.
	* config/arm/arm.md (attribute "neon_type"): Delete.  Move attribute
	values to config/arm/types.md.  Update patterns where appropriate.
	* config/arm/types.md (type): Add Neon types.
	* config/arm/neon.md: Remove "neon_type" attribute,
	use "type" attribute everywhere appropriate.
	* doc/md.texi: Change references to neon_type to refer to type.
	* config/arm/vfp.md: Update patterns for attribute changes.
	* config/arm/arm.c (cortexa7_older_only): Update for attribute change.
	* config/arm/arm1020e.md: Update for attribute change.
	* config/arm/cortex-a15-neon.md: Update for attribute change.
	* config/arm/cortex-a15.md: Update for attribute change.
	* config/arm/cortex-a5.md: Update for attribute change.
	* config/arm/cortex-a53.md: Update for attribute change.
	* config/arm/cortex-a7.md: Update for attribute change.
	* config/arm/cortex-a8-neon.md: Update for attribute change.
	* config/arm/cortex-a8.md: Update for attribute change.
	* config/arm/cortex-a9-neon.md: Update for attribute change.
	* config/arm/cortex-a9.md: Update for attribute change.
	* config/arm/cortex-m4-fpu.md: Update for attribute change.
	* config/arm/cortex-r4f.md: Update for attribute change.
	* config/arm/iterators.md: Update comment referring to neon_type.
	* config/arm/iwmmxt.md: Update for attribute change.
	* config/arm/marvell-pj4.md: Update for attribute change.
	* config/arm/neon-schedgen.ml (emit_insn_reservations): Update for
	attribute change.
	* config/arm/vfp11.md: Update for attribute change.


Co-Authored-By: Sofiane Naci <sofiane.naci@arm.com>

From-SVN: r202272
parent fbe0dc78
Showing with 271 additions and 237 deletions
gcc/config/aarch64/aarch64.md
......@@ -909,7 +909,7 @@
str\\t%q1, %0"
[(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \
load2,store2,store2,fpsimd_load,fpsimd_store")
(set_attr "type" "mov_reg,r_2_f,f_2_r,*, \
(set_attr "type" "mov_reg,f_mcr,f_mrc,*, \
load2,store2,store2,f_loadd,f_stored")
(set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI")
......@@ -964,7 +964,7 @@
[(set_attr "v8type" "fmovi2f,fmovf2i,\
fmov,fconst,fpsimd_load,\
fpsimd_store,fpsimd_load,fpsimd_store,fmov")
(set_attr "type" "r_2_f,f_2_r,mov_reg,fconsts,\
(set_attr "type" "f_mcr,f_mrc,mov_reg,fconsts,\
f_loads,f_stores,f_loads,f_stores,mov_reg")
(set_attr "mode" "SF")]
)
......@@ -987,7 +987,7 @@
[(set_attr "v8type" "fmovi2f,fmovf2i,\
fmov,fconst,fpsimd_load,\
fpsimd_store,fpsimd_load,fpsimd_store,move")
(set_attr "type" "r_2_f,f_2_r,mov_reg,fconstd,\
(set_attr "type" "f_mcr,f_mrc,mov_reg,fconstd,\
f_loadd,f_stored,f_loadd,f_stored,mov_reg")
(set_attr "mode" "DF")]
)
......@@ -1027,7 +1027,7 @@
ldp\\t%0, %H0, %1
stp\\t%1, %H1, %0"
[(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2")
(set_attr "type" "arlo_reg,mov_reg,r_2_f,f_2_r,fconstd,fconstd,\
(set_attr "type" "arlo_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\
f_loadd,f_stored,f_loadd,f_stored")
(set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4")
......@@ -4031,7 +4031,7 @@
"reload_completed || reload_in_progress"
"fmov\\t%x0, %d1"
[(set_attr "v8type" "fmovf2i")
(set_attr "type" "f_2_r")
(set_attr "type" "f_mrc")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
......@@ -4044,7 +4044,7 @@
"reload_completed || reload_in_progress"
"fmov\\t%x0, %1.d[1]"
[(set_attr "v8type" "fmovf2i")
(set_attr "type" "f_2_r")
(set_attr "type" "f_mrc")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
......@@ -4056,7 +4056,7 @@
"reload_completed || reload_in_progress"
"fmov\\t%0.d[1], %x1"
[(set_attr "v8type" "fmovi2f")
(set_attr "type" "r_2_f")
(set_attr "type" "f_mcr")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
......@@ -4067,7 +4067,7 @@
"reload_completed || reload_in_progress"
"fmov\\t%d0, %x1"
[(set_attr "v8type" "fmovi2f")
(set_attr "type" "r_2_f")
(set_attr "type" "f_mcr")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
......@@ -4079,7 +4079,7 @@
"reload_completed || reload_in_progress"
"fmov\\t%d0, %d1"
[(set_attr "v8type" "fmovi2f")
(set_attr "type" "r_2_f")
(set_attr "type" "f_mcr")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
......
gcc/config/arm/arm.c
......@@ -8975,7 +8975,8 @@ cortexa7_older_only (rtx insn)
case TYPE_FMACD:
case TYPE_FDIVS:
case TYPE_FDIVD:
case TYPE_F_2_R:
case TYPE_F_MRC:
case TYPE_F_MRRC:
case TYPE_F_FLAG:
case TYPE_F_LOADS:
case TYPE_F_STORES:
......
gcc/config/arm/arm.md
......@@ -252,73 +252,6 @@
; initialized by arm_option_override()
(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
;; Classification of NEON instructions for scheduling purposes.
(define_attr "neon_type"
"neon_int_1,\
neon_int_2,\
neon_int_3,\
neon_int_4,\
neon_int_5,\
neon_vqneg_vqabs,\
neon_vmov,\
neon_vaba,\
neon_vsma,\
neon_vaba_qqq,\
neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
neon_mul_qqq_8_16_32_ddd_32,\
neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
neon_mla_qqq_8_16,\
neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
neon_mla_qqq_32_qqd_32_scalar,\
neon_mul_ddd_16_scalar_32_16_long_scalar,\
neon_mul_qqd_32_scalar,\
neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
neon_shift_1,\
neon_shift_2,\
neon_shift_3,\
neon_vshl_ddd,\
neon_vqshl_vrshl_vqrshl_qqq,\
neon_vsra_vrsra,\
neon_fp_vadd_ddd_vabs_dd,\
neon_fp_vadd_qqq_vabs_qq,\
neon_fp_vsum,\
neon_fp_vmul_ddd,\
neon_fp_vmul_qqd,\
neon_fp_vmla_ddd,\
neon_fp_vmla_qqq,\
neon_fp_vmla_ddd_scalar,\
neon_fp_vmla_qqq_scalar,\
neon_fp_vrecps_vrsqrts_ddd,\
neon_fp_vrecps_vrsqrts_qqq,\
neon_bp_simple,\
neon_bp_2cycle,\
neon_bp_3cycle,\
neon_ldr,\
neon_str,\
neon_vld1_1_2_regs,\
neon_vld1_3_4_regs,\
neon_vld2_2_regs_vld1_vld2_all_lanes,\
neon_vld2_4_regs,\
neon_vld3_vld4,\
neon_vst1_1_2_regs_vst2_2_regs,\
neon_vst1_3_4_regs,\
neon_vst2_4_regs_vst3_vst4,\
neon_vst3_vst4,\
neon_vld1_vld2_lane,\
neon_vld3_vld4_lane,\
neon_vst1_vst2_lane,\
neon_vst3_vst4_lane,\
neon_vld3_vld4_all_lanes,\
neon_mcr,\
neon_mcr_2_mcrr,\
neon_mrc,\
neon_mrrc,\
neon_ldm_2,\
neon_stm_2,\
none"
(const_string "none"))
; condition codes: this one is used by final_prescan_insn to speed up
; conditionalizing instructions. It saves having to scan the rtl to see if
; it uses or alters the condition codes.
......@@ -344,7 +277,32 @@
(ior (eq_attr "is_thumb1" "yes")
(eq_attr "type" "call"))
(const_string "clob")
(if_then_else (eq_attr "neon_type" "none")
(if_then_else (eq_attr "type"
"!neon_int_1, neon_int_2, neon_int_3, neon_int_4, neon_int_5,\
neon_vqneg_vqabs, neon_vmov, neon_vaba, neon_vsma, neon_vaba_qqq,\
neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
neon_mul_qqq_8_16_32_ddd_32,\
neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
neon_mla_qqq_8_16,\
neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
neon_mla_qqq_32_qqd_32_scalar,\
neon_mul_ddd_16_scalar_32_16_long_scalar, neon_mul_qqd_32_scalar,\
neon_mla_ddd_16_scalar_qdd_32_16_long_scalar, neon_shift_1,\
neon_shift_2, neon_shift_3, neon_vshl_ddd,\
neon_vqshl_vrshl_vqrshl_qqq, neon_vsra_vrsra,\
neon_fp_vadd_ddd_vabs_dd, neon_fp_vadd_qqq_vabs_qq, neon_fp_vsum,\
neon_fp_vmul_ddd, neon_fp_vmul_qqd, neon_fp_vmla_ddd,\
neon_fp_vmla_qqq, neon_fp_vmla_ddd_scalar, neon_fp_vmla_qqq_scalar,\
neon_fp_vrecps_vrsqrts_ddd, neon_fp_vrecps_vrsqrts_qqq,\
neon_bp_simple, neon_bp_2cycle, neon_bp_3cycle, neon_ldr, neon_str,\
neon_vld1_1_2_regs, neon_vld1_3_4_regs,\
neon_vld2_2_regs_vld1_vld2_all_lanes, neon_vld2_4_regs,\
neon_vld3_vld4, neon_vst1_1_2_regs_vst2_2_regs, neon_vst1_3_4_regs,\
neon_vst2_4_regs_vst3_vst4, neon_vst3_vst4, neon_vld1_vld2_lane,\
neon_vld3_vld4_lane, neon_vst1_vst2_lane, neon_vst3_vst4_lane,\
neon_vld3_vld4_all_lanes, neon_mcr, neon_mcr_2_mcrr, neon_mrc,\
neon_mrrc, neon_ldm_2, neon_stm_2")
(const_string "nocond")
(const_string "unconditional"))))
......@@ -2179,7 +2137,7 @@
gen_highpart_mode (SImode, DImode, operands[2]));
}"
[(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
[(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,
avoid_neon_for_64bits,avoid_neon_for_64bits")
(set_attr "length" "*,*,8,8,8,8,*,*")
......@@ -3014,7 +2972,7 @@
gen_highpart_mode (SImode, DImode, operands[2]));
}"
[(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
[(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
(set_attr "length" "*,*,8,8,8,8,*,*")
(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")]
)
......@@ -3193,7 +3151,7 @@
}"
[(set_attr "length" "*,8,8,8,8,*")
(set_attr "neon_type" "neon_int_1,*,*,*,*,neon_int_1")
(set_attr "type" "neon_int_1,*,*,*,*,neon_int_1")
(set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")]
)
......@@ -4960,7 +4918,7 @@
}"
[(set_attr "length" "*,8,8,*")
(set_attr "predicable" "no,yes,yes,no")
(set_attr "neon_type" "neon_int_1,*,*,neon_int_1")
(set_attr "type" "neon_int_1,*,*,neon_int_1")
(set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")]
)
......
gcc/config/arm/arm1020e.md
......@@ -316,7 +316,7 @@
(define_insn_reservation "v10_c2v" 4
(and (eq_attr "vfp10" "yes")
(eq_attr "type" "r_2_f"))
(eq_attr "type" "f_mcr,f_mcrr"))
"1020a_e+1020l_e+v10_ls1,v10_ls2")
(define_insn_reservation "v10_fstores" 1
......@@ -331,7 +331,7 @@
(define_insn_reservation "v10_v2c" 1
(and (eq_attr "vfp10" "yes")
(eq_attr "type" "f_2_r"))
(eq_attr "type" "f_mrc,f_mrrc"))
"1020a_e+1020l_e,1020l_m,1020l_w")
(define_insn_reservation "v10_to_cpsr" 2
......
gcc/config/arm/cortex-a15.md
......@@ -61,25 +61,22 @@
;; Simple ALU without shift
(define_insn_reservation "cortex_a15_alu" 2
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg")
(eq_attr "neon_type" "none")))
mvn_imm,mvn_reg"))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift")
(eq_attr "neon_type" "none")))
(eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift"))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
|(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
;; ALU ops with register controlled shift
(define_insn_reservation "cortex_a15_alu_shift_reg" 3
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")
(eq_attr "neon_type" "none")))
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
"(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
|(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
|(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
......@@ -89,15 +86,13 @@
;; 32-bit multiplies
(define_insn_reservation "cortex_a15_mult32" 3
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "mul32" "yes")
(eq_attr "neon_type" "none")))
(eq_attr "mul32" "yes"))
"ca15_issue1,ca15_mx")
;; 64-bit multiplies
(define_insn_reservation "cortex_a15_mult64" 4
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "mul64" "yes")
(eq_attr "neon_type" "none")))
(eq_attr "mul64" "yes"))
"ca15_issue1,ca15_mx*2")
;; Integer divide
......@@ -114,8 +109,7 @@
;; Block all issue pipes for a cycle
(define_insn_reservation "cortex_a15_block" 1
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "block")
(eq_attr "neon_type" "none")))
(eq_attr "type" "block"))
"ca15_issue3")
;; Branch execution Unit
......@@ -124,8 +118,7 @@
;; No latency as there is no result
(define_insn_reservation "cortex_a15_branch" 0
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "branch")
(eq_attr "neon_type" "none")))
(eq_attr "type" "branch"))
"ca15_issue1,ca15_bx")
;; Load-store execution Unit
......@@ -133,29 +126,25 @@
;; Loads of up to two words.
(define_insn_reservation "cortex_a15_load1" 4
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "load_byte,load1,load2")
(eq_attr "neon_type" "none")))
(eq_attr "type" "load_byte,load1,load2"))
"ca15_issue1,ca15_ls,ca15_ldr,nothing")
;; Loads of three or four words.
(define_insn_reservation "cortex_a15_load3" 5
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "load3,load4")
(eq_attr "neon_type" "none")))
(eq_attr "type" "load3,load4"))
"ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing")
;; Stores of up to two words.
(define_insn_reservation "cortex_a15_store1" 0
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "store1,store2")
(eq_attr "neon_type" "none")))
(eq_attr "type" "store1,store2"))
"ca15_issue1,ca15_ls,ca15_str")
;; Stores of three or four words.
(define_insn_reservation "cortex_a15_store3" 0
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "store3,store4")
(eq_attr "neon_type" "none")))
(eq_attr "type" "store3,store4"))
"ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str")
;; We include Neon.md here to ensure that the branch can block the Neon units.
......@@ -165,8 +154,7 @@
;; pipeline. The result however is available the next cycle.
(define_insn_reservation "cortex_a15_call" 1
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "call")
(eq_attr "neon_type" "none")))
(eq_attr "type" "call"))
"ca15_issue3,\
ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx_ij+ca15_cx_ik+ca15_ls1+ca15_ls2+\
ca15_cx_imac1+ca15_cx_ialu1+ca15_cx_ialu2+ca15_cx_ishf+\
......
gcc/config/arm/cortex-a5.md
......@@ -243,12 +243,12 @@
(define_insn_reservation "cortex_a5_r2f" 4
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "r_2_f"))
(eq_attr "type" "f_mcr,f_mcrr"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_f2r" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "f_2_r"))
(eq_attr "type" "f_mrc,f_mrrc"))
"cortex_a5_ex1")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/cortex-a53.md
......@@ -244,12 +244,12 @@
(define_insn_reservation "cortex_a53_r2f" 4
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "r_2_f"))
(eq_attr "type" "f_mcr,f_mcrr"))
"cortex_a53_slot0")
(define_insn_reservation "cortex_a53_f2r" 2
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "f_2_r"))
(eq_attr "type" "f_mrc,f_mrrc"))
"cortex_a53_slot0")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/cortex-a8.md
......@@ -85,9 +85,7 @@
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
(ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none"))
(eq_attr "type" "clz")))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,clz"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
......
gcc/config/arm/cortex-a9.md
......@@ -80,10 +80,9 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
;; which can go down E2 without any problem.
(define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift")
(eq_attr "neon_type" "none")))
mov_shift_reg,mov_shift"))
"cortex_a9_p0_default|cortex_a9_p1_default")
;; An instruction using the shifter will go down E1.
......@@ -200,7 +199,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
;; Pipelining for VFP instructions.
;; Issue happens either along load store unit or the VFP / Neon unit.
;; Pipeline Instruction Classification.
;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r
;; FPS - fcpys, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc
;; FP_ADD - fadds, faddd, fcmps (1)
;; FPMUL - fmul{s,d}, fmac{s,d}, ffma{s,d}
;; FPDIV - fdiv{s,d}
......@@ -213,7 +212,8 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
(define_insn_reservation "cortex_a9_fps" 2
(and (eq_attr "tune" "cortexa9")
(eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag"))
(eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd,\
f_mcr, f_mcrr, f_mrc, f_mrrc, f_flag"))
"ca9_issue_vfp_neon + ca9fps")
(define_bypass 1
......
gcc/config/arm/cortex-m4-fpu.md
......@@ -40,7 +40,7 @@
(define_insn_reservation "cortex_m4_vmov_2" 2
(and (eq_attr "tune" "cortexm4")
(eq_attr "type" "f_2_r,r_2_f"))
(eq_attr "type" "f_mrc,f_mrrc,f_mcr,f_mcrr"))
"cortex_m4_ex_v*2")
(define_insn_reservation "cortex_m4_fmuls" 2
......
gcc/config/arm/cortex-r4f.md
......@@ -83,12 +83,12 @@
(define_insn_reservation "cortex_r4_mcr" 2
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "r_2_f"))
(eq_attr "type" "f_mcr,f_mcrr"))
"cortex_r4_issue_ab")
(define_insn_reservation "cortex_r4_mrc" 3
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "f_2_r"))
(eq_attr "type" "f_mrc,f_mrrc"))
"cortex_r4_issue_ab")
;; Bypasses for normal (not early) regs.
......
gcc/config/arm/iterators.md
......@@ -391,7 +391,7 @@
(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
(V8HI "x") (V4SI "t") (V4SF "t")])
;; Predicates used for setting neon_type
;; Predicates used for setting type for neon instructions
(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
(V4HI "false") (V8HI "false")
......
gcc/config/arm/iwmmxt.md
......@@ -155,7 +155,8 @@
(const_int 8)
(const_int 4))]
(const_int 4)))
(set_attr "type" "*,*,*,load2,store2,wmmx_wmov,wmmx_tmcrr,wmmx_tmrrc,wmmx_wldr,wmmx_wstr,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
(set_attr "type" "*,*,*,load2,store2,*,*,*,*,*,f_mcrr,f_mrrc,\
ffarithd,f_loadd,f_stored")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*")
(set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")]
)
......@@ -187,7 +188,8 @@
default:
gcc_unreachable ();
}"
[(set_attr "type" "*,*,*,*,load1,store1,wmmx_tmcr,wmmx_tmrc,wmmx_wldr,wmmx_wstr,r_2_f,f_2_r,fcpys,f_loads,f_stores")
[(set_attr "type" "*,*,*,*,load1,store1,*,*,*,*,f_mcr,f_mrc,\
fcpys,f_loads,f_stores")
(set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*")
(set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*")
......
gcc/config/arm/marvell-pj4.md
......@@ -201,9 +201,9 @@
(define_insn_reservation "pj4_vfp_to_core" 7
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "f_2_r,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
(eq_attr "type" "f_mrc,f_mrrc,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
(define_insn_reservation "pj4_core_to_vfp" 2
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "r_2_f")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
(eq_attr "type" "f_mcr,f_mcrr")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
gcc/config/arm/neon-schedgen.ml
......@@ -480,7 +480,7 @@ let emit_insn_reservations core =
Printf.printf "(define_insn_reservation \"%s_%s\" %d\n"
corestring producer latency;
Printf.printf " (and (eq_attr \"tune\" \"%s\")\n" tunestring;
Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer;
Printf.printf " (eq_attr \"type\" \"%s\"))\n" producer;
let str =
match reservation with
Mul -> "dp" | Mul_2cycle -> "dp_2" | Mul_4cycle -> "dp_4"
......
gcc/config/arm/types.md
......@@ -39,11 +39,14 @@
; call subroutine call.
; clz count leading zeros (CLZ).
; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
; f_2_r transfer from float to core (no memory needed).
; f_cvt conversion between float and integral.
; f_flag transfer of co-processor flags to the CPSR.
; f_load[d,s] double/single load from memory. Used for VFP unit.
; f_mcr transfer arm to vfp reg.
; f_mcrr transfer two arm regs to vfp reg.
; f_minmax[d,s] double/single floating point minimum/maximum.
; f_mrc transfer vfp to arm reg.
; f_mrrc transfer vfp to two arm regs.
; f_rint[d,s] double/single floating point rount to integral.
; f_sel[d,s] double/single floating byte select.
; f_store[d,s] double/single store to memory. Used for VFP unit.
......@@ -77,7 +80,6 @@
; mvn_reg inverting move instruction, register.
; mvn_shift inverting move instruction, shifted operand by a constant.
; mvn_shift_reg inverting move instruction, shifted operand by a register.
; r_2_f transfer from core to float.
; sdiv signed division.
; shift simple shift operation (LSL, LSR, ASR, ROR) with an
; immediate.
......@@ -181,6 +183,71 @@
; wmmx_wunpckih
; wmmx_wunpckil
; wmmx_wxor
;
; The classification below is for NEON instructions.
;
; neon_bp_2cycle
; neon_bp_3cycle
; neon_bp_simple
; neon_fp_vadd_ddd_vabs_dd
; neon_fp_vadd_qqq_vabs_qq
; neon_fp_vmla_ddd_scalar
; neon_fp_vmla_ddd
; neon_fp_vmla_qqq_scalar
; neon_fp_vmla_qqq
; neon_fp_vmul_ddd
; neon_fp_vmul_qqd
; neon_fp_vrecps_vrsqrts_ddd
; neon_fp_vrecps_vrsqrts_qqq
; neon_fp_vsum
; neon_int_1
; neon_int_2
; neon_int_3
; neon_int_4
; neon_int_5
; neon_ldm_2
; neon_ldr
; neon_mcr_2_mcrr
; neon_mcr
; neon_mla_ddd_16_scalar_qdd_32_16_long_scalar
; neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long
; neon_mla_ddd_8_16_qdd_16_8_long_32_16_long
; neon_mla_qqq_32_qqd_32_scalar
; neon_mla_qqq_8_16
; neon_mrc
; neon_mrrc
; neon_mul_ddd_16_scalar_32_16_long_scalar
; neon_mul_ddd_8_16_qdd_16_8_long_32_16_long
; neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar
; neon_mul_qqd_32_scalar
; neon_mul_qqq_8_16_32_ddd_32
; neon_shift_1
; neon_shift_2
; neon_shift_3
; neon_stm_2
; neon_str
; neon_vaba_qqq
; neon_vaba
; neon_vld1_1_2_regs
; neon_vld1_3_4_regs
; neon_vld1_vld2_lane
; neon_vld2_2_regs_vld1_vld2_all_lanes
; neon_vld2_4_regs
; neon_vld3_vld4_all_lanes
; neon_vld3_vld4_lane
; neon_vld3_vld4
; neon_vmov
; neon_vqneg_vqabs
; neon_vqshl_vrshl_vqrshl_qqq
; neon_vshl_ddd
; neon_vsma
; neon_vsra_vrsra
; neon_vst1_1_2_regs_vst2_2_regs
; neon_vst1_3_4_regs
; neon_vst1_vst2_lane
; neon_vst2_4_regs_vst3_vst4
; neon_vst3_vst4_lane
; neon_vst3_vst4
(define_attr "type"
"arlo_imm,\
......@@ -192,13 +259,16 @@
call,\
clz,\
extend,\
f_2_r,\
f_cvt,\
f_flag,\
f_loadd,\
f_loads,\
f_mcr,\
f_mcrr,\
f_minmaxd,\
f_minmaxs,\
f_mrc,\
f_mrrc,\
f_rintd,\
f_rints,\
f_seld,\
......@@ -241,7 +311,6 @@
mvn_reg,\
mvn_shift,\
mvn_shift_reg,\
r_2_f,\
sdiv,\
shift,\
shift_reg,\
......@@ -337,7 +406,69 @@
wmmx_wunpckel,\
wmmx_wunpckih,\
wmmx_wunpckil,\
wmmx_wxor"
wmmx_wxor,\
neon_bp_2cycle,\
neon_bp_3cycle,\
neon_bp_simple,\
neon_fp_vadd_ddd_vabs_dd,\
neon_fp_vadd_qqq_vabs_qq,\
neon_fp_vmla_ddd_scalar,\
neon_fp_vmla_ddd,\
neon_fp_vmla_qqq_scalar,\
neon_fp_vmla_qqq,\
neon_fp_vmul_ddd,\
neon_fp_vmul_qqd,\
neon_fp_vrecps_vrsqrts_ddd,\
neon_fp_vrecps_vrsqrts_qqq,\
neon_fp_vsum,\
neon_int_1,\
neon_int_2,\
neon_int_3,\
neon_int_4,\
neon_int_5,\
neon_ldm_2,\
neon_ldr,\
neon_mcr_2_mcrr,\
neon_mcr,\
neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
neon_mla_qqq_32_qqd_32_scalar,\
neon_mla_qqq_8_16,\
neon_mrc,\
neon_mrrc,\
neon_mul_ddd_16_scalar_32_16_long_scalar,\
neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
neon_mul_qqd_32_scalar,\
neon_mul_qqq_8_16_32_ddd_32,\
neon_shift_1,\
neon_shift_2,\
neon_shift_3,\
neon_stm_2,\
neon_str,\
neon_vaba_qqq,\
neon_vaba,\
neon_vld1_1_2_regs,\
neon_vld1_3_4_regs,\
neon_vld1_vld2_lane,\
neon_vld2_2_regs_vld1_vld2_all_lanes,\
neon_vld2_4_regs,\
neon_vld3_vld4_all_lanes,\
neon_vld3_vld4_lane,\
neon_vld3_vld4,\
neon_vmov,\
neon_vqneg_vqabs,\
neon_vqshl_vrshl_vqrshl_qqq,\
neon_vshl_ddd,\
neon_vsma,\
neon_vsra_vrsra,\
neon_vst1_1_2_regs_vst2_2_regs,\
neon_vst1_3_4_regs,\
neon_vst1_vst2_lane,\
neon_vst2_4_regs_vst3_vst4,\
neon_vst3_vst4_lane,\
neon_vst3_vst4"
(const_string "arlo_reg"))
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
......
gcc/config/arm/vfp.md
......@@ -53,8 +53,7 @@
}
"
[(set_attr "predicable" "yes")
(set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
)
......@@ -101,9 +100,8 @@
"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
(set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores")
(set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
(set_attr "neon_type" "*,*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
(set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
)
......@@ -146,8 +144,7 @@
gcc_unreachable ();
}
"
[(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
(set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
[(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
(set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
(eq_attr "alternative" "2") (const_int 12)
(eq_attr "alternative" "3") (const_int 16)
......@@ -195,8 +192,7 @@
gcc_unreachable ();
}
"
[(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
(set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
[(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
(eq_attr "alternative" "2") (const_int 12)
(eq_attr "alternative" "3") (const_int 16)
......@@ -264,8 +260,8 @@
}
"
[(set_attr "conds" "unconditional")
(set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
(set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
(set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\
load1,store1,fcpys,*,f_mcr,f_mrc,*")
(set_attr "length" "4,4,4,4,4,4,4,4,8")]
)
......@@ -315,7 +311,7 @@
}
"
[(set_attr "conds" "unconditional")
(set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
(set_attr "type" "load1,store1,fcpys,*,f_mcr,f_mrc,*")
(set_attr "length" "4,4,4,4,4,4,8")]
)
......@@ -355,8 +351,7 @@
"
[(set_attr "predicable" "yes")
(set_attr "type"
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
(set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
"f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
(set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
)
......@@ -393,8 +388,7 @@
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type"
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
(set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
"f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
(set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
)
......@@ -434,9 +428,8 @@
}
}
"
[(set_attr "type"
"r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
(set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
[(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
load2,store2,ffarithd,*")
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
......@@ -480,9 +473,8 @@
}
}
"
[(set_attr "type"
"r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
(set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
[(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
f_stored,load2,store2,ffarithd,*")
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
......@@ -517,8 +509,7 @@
fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "4,4,8,4,4,8,4,4,8")
(set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
(set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
(set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
)
(define_insn "*thumb2_movsfcc_vfp"
......@@ -541,8 +532,7 @@
ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "6,6,10,6,6,10,6,6,10")
(set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
(set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
(set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
)
(define_insn "*movdfcc_vfp"
......@@ -565,8 +555,7 @@
fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
[(set_attr "conds" "use")
(set_attr "length" "4,4,8,4,4,8,4,4,8")
(set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
(set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
(set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
)
(define_insn "*thumb2_movdfcc_vfp"
......@@ -589,8 +578,7 @@
ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
[(set_attr "conds" "use")
(set_attr "length" "6,6,10,6,6,10,6,6,10")
(set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
(set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
(set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
)
......
gcc/config/arm/vfp11.md
......@@ -77,12 +77,12 @@
;; Moves to/from arm regs also use the load/store pipeline.
(define_insn_reservation "vfp_fload" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_loads,f_loadd,r_2_f"))
(eq_attr "type" "f_loads,f_loadd,f_mcr,f_mcrr"))
"vfp_ls")
(define_insn_reservation "vfp_fstore" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_stores,f_stored,f_2_r"))
(eq_attr "type" "f_stores,f_stored,f_mrc,f_mrrc"))
"vfp_ls")
(define_insn_reservation "vfp_to_cpsr" 4
......
gcc/doc/md.texi
......@@ -9651,7 +9651,7 @@ Here's an example of int iterators in action, taken from the ARM port:
QABSNEG))]
"TARGET_NEON"
"vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
[(set_attr "neon_type" "neon_vqneg_vqabs")]
[(set_attr "type" "neon_vqneg_vqabs")]
)
@end smallexample
......@@ -9666,7 +9666,7 @@ This is equivalent to:
UNSPEC_VQABS))]
"TARGET_NEON"
"vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
[(set_attr "neon_type" "neon_vqneg_vqabs")]
[(set_attr "type" "neon_vqneg_vqabs")]
)
(define_insn "neon_vqneg<mode>"
......@@ -9676,7 +9676,7 @@ This is equivalent to:
UNSPEC_VQNEG))]
"TARGET_NEON"
"vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
[(set_attr "neon_type" "neon_vqneg_vqabs")]
[(set_attr "type" "neon_vqneg_vqabs")]
)
@end smallexample
......
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