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lvzhengyang
macroplacement
Repository
597e45ac45b300d3d12c1925ad2ecaac7743969d
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macroplacement
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nvdla
rtl
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Added NVDLA details and updated the README
· 5d3cbda9
...
Signed-off-by: sakundu <sakundu@ucsd.edu>
sakundu
committed
Jul 03, 2022
5d3cbda9
Name
Last commit
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..
AN2D4PO4.v
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CKLNQD12.v
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CKLNQD12PO4.v
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HLS_cdp_icvt.v
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HLS_cdp_ocvt.v
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HLS_fp16_to_fp17.v
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HLS_fp16_to_fp32.v
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HLS_fp17_add.v
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HLS_fp17_mul.v
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HLS_fp17_sub.v
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HLS_fp17_to_fp16.v
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HLS_fp17_to_fp32.v
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HLS_fp32_add.v
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HLS_fp32_mul.v
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HLS_fp32_sub.v
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HLS_fp32_to_fp16.v
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HLS_fp32_to_fp17.v
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HLS_uint16_to_fp17.v
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LNQD1PO4.v
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MUX2D4.v
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MUX2HDD2.v
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NV_BLKBOX_BUFFER.v
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NV_BLKBOX_SINK.v
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NV_BLKBOX_SRC0.v
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NV_BLKBOX_SRC0_X.v
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NV_CLK_gate_power.v
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NV_DW02_tree.v
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NV_DW_lsd.v
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NV_DW_minmax.v
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NV_HWACC_NVDLA_tick_defines.vh
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NV_NVDLA_BDMA_cq.v
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NV_NVDLA_BDMA_csb.v
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NV_NVDLA_BDMA_gate.v
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NV_NVDLA_BDMA_load.v
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NV_NVDLA_BDMA_reg.v
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NV_NVDLA_BDMA_store.v
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NV_NVDLA_CACC_CALC_int8.v
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NV_NVDLA_CACC_assembly_buffer.v
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NV_NVDLA_CACC_assembly_ctrl.v
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NV_NVDLA_CACC_calculator.v
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NV_NVDLA_CACC_delivery_buffer.v
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NV_NVDLA_CACC_delivery_ctrl.v
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NV_NVDLA_CACC_dual_reg.v
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NV_NVDLA_CACC_regfile.v
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NV_NVDLA_CACC_single_reg.v
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NV_NVDLA_CACC_slcg.v
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NV_NVDLA_CDMA_CVT_cell.v
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NV_NVDLA_CDMA_DC_fifo.v
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NV_NVDLA_CDMA_IMG_ctrl.v
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NV_NVDLA_CDMA_IMG_fifo.v
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NV_NVDLA_CDMA_IMG_pack.v
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NV_NVDLA_CDMA_IMG_sg.v
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NV_NVDLA_CDMA_IMG_sg2pack_fifo.v
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NV_NVDLA_CDMA_WG_fifo.v
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NV_NVDLA_CDMA_WT_8ATMM_fifo.v
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NV_NVDLA_CDMA_WT_fifo.v
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NV_NVDLA_CDMA_WT_sp_arb.v
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NV_NVDLA_CDMA_WT_wgs_fifo.v
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NV_NVDLA_CDMA_WT_wrr_arb.v
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NV_NVDLA_CDMA_cvt.v
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NV_NVDLA_CDMA_dc.v
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NV_NVDLA_CDMA_dma_mux.v
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NV_NVDLA_CDMA_dual_reg.v
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NV_NVDLA_CDMA_img.v
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NV_NVDLA_CDMA_regfile.v
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NV_NVDLA_CDMA_shared_buffer.v
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NV_NVDLA_CDMA_single_reg.v
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NV_NVDLA_CDMA_slcg.v
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NV_NVDLA_CDMA_status.v
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NV_NVDLA_CDMA_wg.v
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NV_NVDLA_CDMA_wt.v
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NV_NVDLA_CDP_DP_INTP_unit.v
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NV_NVDLA_CDP_DP_LUT_CTRL_unit.v
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NV_NVDLA_CDP_DP_LUT_ctrl.v
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NV_NVDLA_CDP_DP_MUL_unit.v
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NV_NVDLA_CDP_DP_bufferin.v
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NV_NVDLA_CDP_DP_bufferin_tp1.v
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NV_NVDLA_CDP_DP_cvtin.v
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NV_NVDLA_CDP_DP_cvtout.v
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NV_NVDLA_CDP_DP_data_fifo.v
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NV_NVDLA_CDP_DP_intp.v
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NV_NVDLA_CDP_DP_intpinfo_fifo.v
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NV_NVDLA_CDP_DP_lut.v
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NV_NVDLA_CDP_DP_mul.v
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NV_NVDLA_CDP_DP_nan.v
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NV_NVDLA_CDP_DP_sum.v
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NV_NVDLA_CDP_DP_sumpd_fifo.v
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NV_NVDLA_CDP_DP_syncfifo.v
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NV_NVDLA_CDP_HLS_icvt.v
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NV_NVDLA_CDP_HLS_ocvt.v
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NV_NVDLA_CDP_RDMA_REG_dual.v
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NV_NVDLA_CDP_RDMA_REG_single.v
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NV_NVDLA_CDP_RDMA_cq.v
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NV_NVDLA_CDP_RDMA_eg.v
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NV_NVDLA_CDP_RDMA_ig.v
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NV_NVDLA_CDP_RDMA_lat_fifo.v
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NV_NVDLA_CDP_RDMA_reg.v
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NV_NVDLA_CDP_RDMA_ro_fifo.v
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NV_NVDLA_CDP_REG_dual.v
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NV_NVDLA_CDP_REG_single.v
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NV_NVDLA_CDP_WDMA_dat_fifo.v
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NV_NVDLA_CDP_dp.v
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NV_NVDLA_CDP_rdma.v
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NV_NVDLA_CDP_reg.v
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NV_NVDLA_CDP_slcg.v
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NV_NVDLA_CDP_wdma.v
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NV_NVDLA_CFGROM_rom.v
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NV_NVDLA_CMAC_CORE_active.v
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NV_NVDLA_CMAC_CORE_cfg.v
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NV_NVDLA_CMAC_CORE_mac.v
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NV_NVDLA_CMAC_CORE_rt_in.v
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NV_NVDLA_CMAC_CORE_rt_out.v
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NV_NVDLA_CMAC_CORE_slcg.v
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NV_NVDLA_CMAC_REG_dual.v
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NV_NVDLA_CMAC_REG_single.v
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NV_NVDLA_CMAC_core.v
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NV_NVDLA_CMAC_reg.v
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NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v
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NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v
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NV_NVDLA_CSC_SG_dat_fifo.v
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NV_NVDLA_CSC_SG_wt_fifo.v
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NV_NVDLA_CSC_WL_dec.v
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NV_NVDLA_CSC_dl.v
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NV_NVDLA_CSC_dual_reg.v
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NV_NVDLA_CSC_pra_cell.v
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NV_NVDLA_CSC_regfile.v
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NV_NVDLA_CSC_sg.v
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NV_NVDLA_CSC_single_reg.v
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NV_NVDLA_CSC_slcg.v
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NV_NVDLA_CSC_wl.v
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NV_NVDLA_DMAIF_rdreq.v
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NV_NVDLA_DMAIF_rdrsp.v
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NV_NVDLA_DMAIF_wr.v
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NV_NVDLA_GLB_CSB_reg.v
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NV_NVDLA_GLB_csb.v
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NV_NVDLA_GLB_fc.v
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NV_NVDLA_GLB_ic.v
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NV_NVDLA_HLS_saturate.v
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NV_NVDLA_HLS_shiftleftsu.v
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NV_NVDLA_HLS_shiftrightsatsu.v
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NV_NVDLA_HLS_shiftrightss.v
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NV_NVDLA_HLS_shiftrightsu.v
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NV_NVDLA_HLS_shiftrightusz.v
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NV_NVDLA_MCIF_CSB_reg.v
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NV_NVDLA_MCIF_READ_IG_arb.v
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NV_NVDLA_MCIF_READ_IG_bpt.v
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NV_NVDLA_MCIF_READ_IG_cvt.v
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NV_NVDLA_MCIF_READ_eg.v
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NV_NVDLA_MCIF_READ_ig.v
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NV_NVDLA_MCIF_WRITE_IG_arb.v
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NV_NVDLA_MCIF_WRITE_IG_bpt.v
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NV_NVDLA_MCIF_WRITE_IG_cvt.v
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NV_NVDLA_MCIF_WRITE_cq.v
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NV_NVDLA_MCIF_WRITE_eg.v
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NV_NVDLA_MCIF_WRITE_ig.v
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NV_NVDLA_MCIF_csb.v
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NV_NVDLA_MCIF_define.vh
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NV_NVDLA_MCIF_read.v
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NV_NVDLA_MCIF_write.v
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NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v
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NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v
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NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v
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NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v
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NV_NVDLA_NOCIF_DRAM_READ_cq.v
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NV_NVDLA_NOCIF_DRAM_READ_eg.v
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NV_NVDLA_NOCIF_DRAM_READ_ig.v
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NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v
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NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v
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NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v
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NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v
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NV_NVDLA_NOCIF_DRAM_WRITE_cq.v
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NV_NVDLA_NOCIF_DRAM_WRITE_eg.v
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NV_NVDLA_NOCIF_DRAM_WRITE_ig.v
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NV_NVDLA_NOCIF_DRAM_read.v
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NV_NVDLA_NOCIF_DRAM_write.v
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NV_NVDLA_NOCIF_dram.v
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NV_NVDLA_PDP_CORE_cal1d.v
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NV_NVDLA_PDP_CORE_cal2d.v
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NV_NVDLA_PDP_CORE_preproc.v
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NV_NVDLA_PDP_CORE_unit1d.v
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NV_NVDLA_PDP_RDMA_REG_dual.v
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NV_NVDLA_PDP_RDMA_REG_single.v
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NV_NVDLA_PDP_RDMA_cq.v
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NV_NVDLA_PDP_RDMA_eg.v
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NV_NVDLA_PDP_RDMA_ig.v
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NV_NVDLA_PDP_RDMA_lat_fifo.v
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NV_NVDLA_PDP_RDMA_reg.v
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NV_NVDLA_PDP_RDMA_ro_fifo.v
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NV_NVDLA_PDP_REG_dual.v
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NV_NVDLA_PDP_REG_single.v
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NV_NVDLA_PDP_SDPIN_ro_fifo.v
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NV_NVDLA_PDP_WDMA_DAT_fifo.v
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NV_NVDLA_PDP_WDMA_cmd.v
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NV_NVDLA_PDP_WDMA_dat.v
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NV_NVDLA_PDP_core.v
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NV_NVDLA_PDP_nan.v
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NV_NVDLA_PDP_rdma.v
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NV_NVDLA_PDP_reg.v
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NV_NVDLA_PDP_slcg.v
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NV_NVDLA_PDP_wdma.v
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NV_NVDLA_RT_cacc2glb.v
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NV_NVDLA_RT_cmac_a2cacc.v
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NV_NVDLA_RT_cmac_b2cacc.v
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NV_NVDLA_RT_csb2cacc.v
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NV_NVDLA_RT_csb2cmac.v
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NV_NVDLA_RT_csc2cmac_a.v
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NV_NVDLA_RT_csc2cmac_b.v
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NV_NVDLA_RT_sdp2nocif.v
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NV_NVDLA_RUBIK_dma.v
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NV_NVDLA_RUBIK_dr2drc.v
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NV_NVDLA_RUBIK_dual_reg.v
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NV_NVDLA_RUBIK_fifo.v
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NV_NVDLA_RUBIK_intr.v
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NV_NVDLA_RUBIK_regfile.v
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NV_NVDLA_RUBIK_rf_core.v
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NV_NVDLA_RUBIK_rf_ctrl.v
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NV_NVDLA_RUBIK_rf_rcmd.v
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NV_NVDLA_RUBIK_rf_wcmd.v
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NV_NVDLA_RUBIK_seq_gen.v
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NV_NVDLA_RUBIK_single_reg.v
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NV_NVDLA_RUBIK_slcg.v
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NV_NVDLA_RUBIK_wr_req.v
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NV_NVDLA_RUBIK_wrdma_cmd.v
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NV_NVDLA_RUBIK_wrdma_data.v
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NV_NVDLA_SDP_BRDMA_cq_lib.v
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NV_NVDLA_SDP_BRDMA_gate.v
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NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v
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NV_NVDLA_SDP_CORE_Y_lut.v
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NV_NVDLA_SDP_CORE_gate.v
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NV_NVDLA_SDP_CORE_pack.v
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NV_NVDLA_SDP_CORE_unpack.v
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NV_NVDLA_SDP_CORE_y.v
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NV_NVDLA_SDP_ERDMA_cq_lib.v
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NV_NVDLA_SDP_ERDMA_gate.v
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NV_NVDLA_SDP_ERDMA_lat_fifo_lib.v
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NV_NVDLA_SDP_HLS_C_int.v
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NV_NVDLA_SDP_HLS_X_int_alu.v
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NV_NVDLA_SDP_HLS_X_int_mul.v
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NV_NVDLA_SDP_HLS_X_int_relu.v
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NV_NVDLA_SDP_HLS_X_int_trt.v
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NV_NVDLA_SDP_HLS_Y_cvt_top.v
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NV_NVDLA_SDP_HLS_Y_idx_top.v
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NV_NVDLA_SDP_HLS_Y_inp_top.v
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NV_NVDLA_SDP_HLS_Y_int_alu.v
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NV_NVDLA_SDP_HLS_Y_int_core.v
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NV_NVDLA_SDP_HLS_Y_int_cvt.v
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NV_NVDLA_SDP_HLS_Y_int_idx.v
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NV_NVDLA_SDP_HLS_Y_int_inp.v
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NV_NVDLA_SDP_HLS_Y_int_mul.v
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NV_NVDLA_SDP_HLS_c.v
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NV_NVDLA_SDP_HLS_lut_expn.v
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NV_NVDLA_SDP_HLS_lut_line.v
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NV_NVDLA_SDP_HLS_prelu.v
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NV_NVDLA_SDP_HLS_relu.v
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NV_NVDLA_SDP_HLS_sync2data.v
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NV_NVDLA_SDP_HLS_x1_int.v
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NV_NVDLA_SDP_HLS_x2_int.v
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NV_NVDLA_SDP_MRDMA_EG_cmd.v
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NV_NVDLA_SDP_MRDMA_EG_din.v
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NV_NVDLA_SDP_MRDMA_EG_dout.v
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NV_NVDLA_SDP_MRDMA_EG_lat_fifo_lib.v
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NV_NVDLA_SDP_MRDMA_cq_lib.v
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NV_NVDLA_SDP_MRDMA_eg.v
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NV_NVDLA_SDP_MRDMA_gate.v
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NV_NVDLA_SDP_MRDMA_ig.v
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NV_NVDLA_SDP_NRDMA_cq_lib.v
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NV_NVDLA_SDP_NRDMA_gate.v
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NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v
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NV_NVDLA_SDP_RDMA_EG_ro.v
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NV_NVDLA_SDP_RDMA_REG_dual.v
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NV_NVDLA_SDP_RDMA_REG_single.v
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NV_NVDLA_SDP_RDMA_dmaif.v
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NV_NVDLA_SDP_RDMA_eg.v
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NV_NVDLA_SDP_RDMA_ig.v
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NV_NVDLA_SDP_RDMA_pack.v
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NV_NVDLA_SDP_RDMA_reg.v
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NV_NVDLA_SDP_RDMA_unpack.v
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NV_NVDLA_SDP_REG_dual.v
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NV_NVDLA_SDP_REG_single.v
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NV_NVDLA_SDP_WDMA_DAT_in.v
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NV_NVDLA_SDP_WDMA_DAT_out.v
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NV_NVDLA_SDP_WDMA_cmd.v
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NV_NVDLA_SDP_WDMA_dat.v
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NV_NVDLA_SDP_WDMA_gate.v
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NV_NVDLA_SDP_WDMA_intr.v
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NV_NVDLA_SDP_WDMA_unpack.v
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NV_NVDLA_SDP_brdma.v
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NV_NVDLA_SDP_cmux.v
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NV_NVDLA_SDP_core.v
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NV_NVDLA_SDP_erdma.v
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NV_NVDLA_SDP_mrdma.v
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NV_NVDLA_SDP_nrdma.v
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NV_NVDLA_SDP_rdma.v
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NV_NVDLA_SDP_reg.v
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NV_NVDLA_SDP_wdma.v
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NV_NVDLA_XXIF_libs.v
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NV_NVDLA_apb2csb.v
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NV_NVDLA_bdma.v
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NV_NVDLA_cacc.v
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NV_NVDLA_cbuf.v
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NV_NVDLA_cdma.v
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NV_NVDLA_cdp.v
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NV_NVDLA_cfgrom.v
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NV_NVDLA_cmac.v
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NV_NVDLA_core_reset.v
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NV_NVDLA_csb_master.v
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NV_NVDLA_csc.v
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NV_NVDLA_glb.v
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NV_NVDLA_mcif.v
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NV_NVDLA_nocif.v
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NV_NVDLA_partition_a.v
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NV_NVDLA_partition_c.v
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NV_NVDLA_partition_m.v
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NV_NVDLA_partition_o.v
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NV_NVDLA_partition_p.v
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NV_NVDLA_pdp.v
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NV_NVDLA_reset.v
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NV_NVDLA_rubik.v
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NV_NVDLA_sdp.v
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NV_NVDLA_ssync3d.v
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NV_NVDLA_ssync3d_c.v
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NV_NVDLA_sync3d.v
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NV_NVDLA_sync3d_c.v
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NV_NVDLA_sync3d_s.v
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NV_nvdla.v
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OR2D1.v
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PGAOPV_AN2D2PO4.v
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PGAOPV_DFCNQD2PO4.v
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PGAOPV_INVD2PO4.v
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RAMDP_128X11_GL_M2_E2.v
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RAMDP_128X6_GL_M2_E2.v
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RAMDP_16X128_GL_M1_E2.v
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RAMDP_16X14_GL_M1_E2.v
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RAMDP_16X16_GL_M1_E2.v
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RAMDP_16X256_GL_M1_E2.v
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RAMDP_16X272_GL_M1_E2.v
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RAMDP_16X64_GL_M1_E2.v
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RAMDP_16X66_GL_M1_E2.v
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RAMDP_20X16_GL_M1_E2.v
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RAMDP_20X288_GL_M1_E2.v
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RAMDP_20X32_GL_M1_E2.v
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RAMDP_20X80_GL_M1_E2.v
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RAMDP_20X8_GL_M1_E2.v
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RAMDP_256X4_GL_M2_E2.v
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RAMDP_256X7_GL_M2_E2.v
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RAMDP_256X8_GL_M2_E2.v
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RAMDP_32X16_GL_M1_E2.v
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RAMDP_32X32_GL_M1_E2.v
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RAMDP_32X64_GL_M1_E2.v
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RAMDP_60X22_GL_M1_E2.v
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RAMDP_64X10_GL_M2_E2.v
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RAMDP_64X14_GL_M2_E2.v
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RAMDP_64X16_GL_M2_E2.v
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RAMDP_64X18_GL_M2_E2.v
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RAMDP_64X32_GL_M1_E2.v
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RAMDP_80X14_GL_M2_E2.v
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RAMDP_80X15_GL_M2_E2.v
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RAMDP_80X18_GL_M1_E2.v
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RAMDP_80X9_GL_M2_E2.v
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RAMDP_8X130_GL_M1_E2.v
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RAMDP_8X258_GL_M1_E2.v
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RAMDP_8X66_GL_M1_E2.v
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RAMPDP_128X128_GL_M1_D2.v
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RAMPDP_128X18_GL_M2_D2.v
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RAMPDP_128X224_GL_M1_D2.v
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RAMPDP_128X256_GL_M1_D2.v
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RAMPDP_128X258_GL_M1_D2.v
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RAMPDP_128X288_GL_M1_D2.v
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RAMPDP_128X32_GL_M2_D2.v
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RAMPDP_128X60_GL_M1_D2.v
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RAMPDP_128X64_GL_M1_D2.v
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RAMPDP_160X144_GL_M2_D2.v
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RAMPDP_160X16_GL_M2_D2.v
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RAMPDP_160X65_GL_M2_D2.v
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RAMPDP_160X82_GL_M2_D2.v
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RAMPDP_160X93_GL_M2_D2.v
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RAMPDP_248X144_GL_M2_D2.v
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RAMPDP_248X82_GL_M2_D2.v
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RAMPDP_256X112_GL_M2_D2.v
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RAMPDP_256X113_GL_M2_D2.v
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RAMPDP_256X11_GL_M4_D2.v
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RAMPDP_256X128_GL_M2_D2.v
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RAMPDP_256X144_GL_M2_D2.v
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RAMPDP_256X14_GL_M4_D2.v
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RAMPDP_256X16_GL_M2_D2.v
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RAMPDP_256X64_GL_M2_D2.v
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RAMPDP_256X80_GL_M2_D2.v
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RAMPDP_32X128_GL_M1_D2.v
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RAMPDP_32X130_GL_M1_D2.v
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RAMPDP_32X192_GL_M1_D2.v
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RAMPDP_32X224_GL_M1_D2.v
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RAMPDP_32X256_GL_M1_D2.v
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RAMPDP_32X272_GL_M1_D2.v
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RAMPDP_32X288_GL_M1_D2.v
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RAMPDP_512X40_GL_M4_D2.v
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RAMPDP_512X56_GL_M4_D2.v
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RAMPDP_512X64_GL_M4_D2.v
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RAMPDP_512X72_GL_M4_D2.v
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RAMPDP_512X8_GL_M4_D2.v
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RAMPDP_60X168_GL_M1_D2.v
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RAMPDP_60X42_GL_M1_D2.v
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RAMPDP_60X84_GL_M1_D2.v
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RAMPDP_64X116_GL_M1_D2.v
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RAMPDP_64X128_GL_M1_D2.v
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RAMPDP_64X130_GL_M1_D2.v
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RAMPDP_64X160_GL_M1_D2.v
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RAMPDP_64X224_GL_M1_D2.v
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RAMPDP_64X226_GL_M1_D2.v
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RAMPDP_64X256_GL_M1_D2.v
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RAMPDP_64X288_GL_M1_D2.v
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RAMPDP_64X64_GL_M1_D2.v
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RAMPDP_64X66_GL_M1_D2.v
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RAMPDP_80X16_GL_M2_D2.v
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RAMPDP_80X17_GL_M2_D2.v
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RAMPDP_80X226_GL_M1_D2.v
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RAMPDP_80X238_GL_M1_D2.v
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RAMPDP_80X256_GL_M1_D2.v
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RAMPDP_80X288_GL_M1_D2.v
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RAMPDP_80X36_GL_M1_D2.v
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RAMPDP_80X66_GL_M1_D2.v
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RAMPDP_80X72_GL_M1_D2.v
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SDFCNQD1.v
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SDFQD1.v
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SDFSNQD1.v
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ScanShareSel_JTAG_reg_ext_cg.v
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cal1d_fp16_pool_sum.v
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fakeram130_256x64_dp.v
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fakeram45_256x64_dp.v
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fakeram7_256x64_dp.v
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fp16_4add.v
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fp_format_cvt.v
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fp_sum_block.v
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int_sum_block.v
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int_sum_block_tp1.v
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nv_ram_rws_128x128.v
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nv_ram_rws_128x128_logic.v
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nv_ram_rws_128x18.v
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nv_ram_rws_128x18_logic.v
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nv_ram_rws_128x256.v
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nv_ram_rws_128x256_logic.v
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nv_ram_rws_128x32.v
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nv_ram_rws_128x32_logic.v
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nv_ram_rws_128x512.v
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nv_ram_rws_128x512_logic.v
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nv_ram_rws_128x60.v
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nv_ram_rws_128x60_logic.v
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nv_ram_rws_128x64.v
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nv_ram_rws_128x64_logic.v
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nv_ram_rws_16x128.v
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nv_ram_rws_16x128_logic.v
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nv_ram_rws_16x256.v
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nv_ram_rws_16x256_logic.v
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nv_ram_rws_16x272.v
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nv_ram_rws_16x272_logic.v
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nv_ram_rws_16x64.v
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nv_ram_rws_16x64_logic.v
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nv_ram_rws_256x128.v
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nv_ram_rws_256x128_logic.v
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nv_ram_rws_256x256.v
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nv_ram_rws_256x256_logic.v
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nv_ram_rws_256x3.v
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nv_ram_rws_256x3_logic.v
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nv_ram_rws_256x512.v
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nv_ram_rws_256x512_logic.v
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nv_ram_rws_256x64.v
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nv_ram_rws_256x64.v.orig
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nv_ram_rws_256x64_logic.v
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nv_ram_rws_256x7.v
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nv_ram_rws_256x7_logic.v
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nv_ram_rws_32x128.v
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nv_ram_rws_32x128_logic.v
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nv_ram_rws_32x16.v
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nv_ram_rws_32x16_logic.v
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nv_ram_rws_32x256.v
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nv_ram_rws_32x256_logic.v
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nv_ram_rws_32x272.v
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nv_ram_rws_32x272_logic.v
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nv_ram_rws_32x32.v
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nv_ram_rws_32x32_logic.v
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nv_ram_rws_32x512.v
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nv_ram_rws_32x512_logic.v
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nv_ram_rws_32x544.v
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nv_ram_rws_32x544_logic.v
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nv_ram_rws_32x64.v
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nv_ram_rws_32x64_logic.v
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nv_ram_rws_32x768.v
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nv_ram_rws_32x768_logic.v
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nv_ram_rws_512x128.v
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nv_ram_rws_512x128_logic.v
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nv_ram_rws_512x256.v
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nv_ram_rws_512x256_logic.v
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nv_ram_rws_512x512.v
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nv_ram_rws_512x512_logic.v
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nv_ram_rws_512x64.v
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nv_ram_rws_512x64_logic.v
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nv_ram_rws_64x10.v
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nv_ram_rws_64x1024.v
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nv_ram_rws_64x1024_logic.v
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nv_ram_rws_64x1088.v
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nv_ram_rws_64x1088_logic.v
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nv_ram_rws_64x10_logic.v
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nv_ram_rws_64x116.v
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nv_ram_rws_64x116_logic.v
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nv_ram_rws_64x128.v
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nv_ram_rws_64x128_logic.v
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nv_ram_rws_64x18.v
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nv_ram_rws_64x18_logic.v
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nv_ram_rws_64x256.v
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nv_ram_rws_64x256_logic.v
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nv_ram_rws_64x32.v
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nv_ram_rws_64x32_logic.v
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nv_ram_rws_64x512.v
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nv_ram_rws_64x512_logic.v
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nv_ram_rws_64x64.v
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nv_ram_rws_64x64_logic.v
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nv_ram_rwsp_128x11.v
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nv_ram_rwsp_128x11_logic.v
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nv_ram_rwsp_128x257.v
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nv_ram_rwsp_128x257_logic.v
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nv_ram_rwsp_128x6.v
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nv_ram_rwsp_128x6_logic.v
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nv_ram_rwsp_160x16.v
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nv_ram_rwsp_160x16_logic.v
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nv_ram_rwsp_160x514.v
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nv_ram_rwsp_160x514_logic.v
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nv_ram_rwsp_160x65.v
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nv_ram_rwsp_160x65_logic.v
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nv_ram_rwsp_16x14.v
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nv_ram_rwsp_16x14_logic.v
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nv_ram_rwsp_16x16.v
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nv_ram_rwsp_16x16_logic.v
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nv_ram_rwsp_16x256.v
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nv_ram_rwsp_16x256_logic.v
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nv_ram_rwsp_16x65.v
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nv_ram_rwsp_16x65_logic.v
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nv_ram_rwsp_20x289.v
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nv_ram_rwsp_20x289_logic.v
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nv_ram_rwsp_245x514.v
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nv_ram_rwsp_245x514_logic.v
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nv_ram_rwsp_256x11.v
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nv_ram_rwsp_256x11_logic.v
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nv_ram_rwsp_256x14.v
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nv_ram_rwsp_256x14_logic.v
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nv_ram_rwsp_256x16.v
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nv_ram_rwsp_256x16_logic.v
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nv_ram_rwsp_256x257.v
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nv_ram_rwsp_256x257_logic.v
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nv_ram_rwsp_32x129.v
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nv_ram_rwsp_32x129_logic.v
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nv_ram_rwsp_32x256.v
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nv_ram_rwsp_32x256_logic.v
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nv_ram_rwsp_32x32.v
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nv_ram_rwsp_32x32_logic.v
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nv_ram_rwsp_4x128.v
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nv_ram_rwsp_4x128_logic.v
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nv_ram_rwsp_4x64.v
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nv_ram_rwsp_4x64_logic.v
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nv_ram_rwsp_61x514.v
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nv_ram_rwsp_61x514_logic.v
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nv_ram_rwsp_61x64.v
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nv_ram_rwsp_61x64_logic.v
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nv_ram_rwsp_61x65.v
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nv_ram_rwsp_61x65_logic.v
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nv_ram_rwsp_64x129.v
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nv_ram_rwsp_64x129_logic.v
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nv_ram_rwsp_64x14.v
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nv_ram_rwsp_64x14_logic.v
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nv_ram_rwsp_64x16.v
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nv_ram_rwsp_64x16_logic.v
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nv_ram_rwsp_80x14.v
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nv_ram_rwsp_80x14_logic.v
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nv_ram_rwsp_80x16.v
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nv_ram_rwsp_80x16_logic.v
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nv_ram_rwsp_80x256.v
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nv_ram_rwsp_80x256_logic.v
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nv_ram_rwsp_80x514.v
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nv_ram_rwsp_80x514_logic.v
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nv_ram_rwsp_80x65.v
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nv_ram_rwsp_80x65_logic.v
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nv_ram_rwsp_8x129.v
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nv_ram_rwsp_8x129_logic.v
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nv_ram_rwsp_8x257.v
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nv_ram_rwsp_8x257_logic.v
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nv_ram_rwsp_8x65.v
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nv_ram_rwsp_8x65_logic.v
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nv_ram_rwst_256x8.v
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nv_ram_rwst_256x8_logic.v
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nv_ram_rwsthp_19x32.v
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nv_ram_rwsthp_19x4.v
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nv_ram_rwsthp_19x80.v
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nv_ram_rwsthp_19x80_logic.v
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nv_ram_rwsthp_20x16.v
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nv_ram_rwsthp_20x16_logic.v
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nv_ram_rwsthp_20x32.v
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nv_ram_rwsthp_20x32_logic.v
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nv_ram_rwsthp_20x4.v
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nv_ram_rwsthp_20x4_logic.v
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nv_ram_rwsthp_20x8.v
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nv_ram_rwsthp_20x8_logic.v
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nv_ram_rwsthp_60x168.v
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nv_ram_rwsthp_60x168_logic.v
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nv_ram_rwsthp_60x21.v
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nv_ram_rwsthp_60x21_logic.v
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nv_ram_rwsthp_60x42.v
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nv_ram_rwsthp_60x42_logic.v
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nv_ram_rwsthp_60x84.v
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nv_ram_rwsthp_60x84_logic.v
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nv_ram_rwsthp_80x15.v
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nv_ram_rwsthp_80x15_logic.v
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nv_ram_rwsthp_80x17.v
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nv_ram_rwsthp_80x17_logic.v
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nv_ram_rwsthp_80x18.v
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nv_ram_rwsthp_80x18_logic.v
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nv_ram_rwsthp_80x36.v
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nv_ram_rwsthp_80x36_logic.v
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nv_ram_rwsthp_80x72.v
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nv_ram_rwsthp_80x72_logic.v
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nv_ram_rwsthp_80x9.v
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nv_ram_rwsthp_80x9_logic.v
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oneHotClk_async_read_clock.v
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oneHotClk_async_write_clock.v
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p_SDFCNQD1PO4.v
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p_SSYNC2DO_C_PP.v
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p_SSYNC3DO.v
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p_SSYNC3DO_C_PPP.v
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p_SSYNC3DO_S_PPP.v
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p_STRICTSYNC3DOTM_C_PPP.v
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rf_2p_hsc_256x64_nogating.v
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simulate_x_tick.vh
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sync2d_c_pp.v
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sync3d.v
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sync3d_c_ppp.v
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sync3d_s_ppp.v
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sync_reset.v
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synth_v2.tar.gz
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