library(fakeram130_64x64) { technology (cmos); delay_model : table_lookup; revision : 1.0; date : "2022-07-01 02:45:36Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; current_unit : "1uA"; leakage_power_unit : "1uW"; nom_process : 1; nom_temperature : 25.000; nom_voltage : 1.8; capacitive_load_unit (1,pf); pulling_resistance_unit : "1kohm"; operating_conditions(tt_1.0_25.0) { process : 1; temperature : 25.000; voltage : 1.8; tree_type : balanced_tree; } /* default attributes */ default_cell_leakage_power : 0; default_fanout_load : 1; default_inout_pin_cap : 0.0; default_input_pin_cap : 0.0; default_output_pin_cap : 0.0; default_input_pin_cap : 0.0; default_max_transition : 1.110; default_operating_conditions : tt_1.0_25.0; default_leakage_power_density : 0.0; /* additional header data */ slew_derate_from_library : 1.000; slew_lower_threshold_pct_fall : 20.000; slew_upper_threshold_pct_fall : 80.000; slew_lower_threshold_pct_rise : 20.000; slew_upper_threshold_pct_rise : 80.000; input_threshold_pct_fall : 50.000; input_threshold_pct_rise : 50.000; output_threshold_pct_fall : 50.000; output_threshold_pct_rise : 50.000; lu_table_template(fakeram130_64x64_mem_out_delay_template) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } lu_table_template(fakeram130_64x64_mem_out_slew_template) { variable_1 : total_output_net_capacitance; index_1 ("1000, 1001"); } lu_table_template(fakeram130_64x64_constraint_template) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } power_lut_template(fakeram130_64x64_energy_template_clkslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } power_lut_template(fakeram130_64x64_energy_template_sigslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } library_features(report_delay_calculation); type (fakeram130_64x64_DATA) { base_type : array ; data_type : bit ; bit_width : 64; bit_from : 63; bit_to : 0 ; downto : true ; } type (fakeram130_64x64_ADDRESS) { base_type : array ; data_type : bit ; bit_width : 6; bit_from : 5; bit_to : 0 ; downto : true ; } cell(fakeram130_64x64) { area : 44181.749; interface_timing : true; memory() { type : ram; address_width : 6; word_width : 64; } pin(clk) { direction : input; capacitance : 0.025; clock : true; min_period : 0.394 ; internal_power(){ rise_power(fakeram130_64x64_energy_template_clkslew) { index_1 ("0.044, 1.110"); values ("15.950, 15.950") } fall_power(fakeram130_64x64_energy_template_clkslew) { index_1 ("0.044, 1.110"); values ("15.950, 15.950") } } } bus(rd_out) { bus_type : fakeram130_64x64_DATA; direction : output; max_capacitance : 0.500; memory_read() { address : addr_in; } timing() { related_pin : "clk" ; timing_type : rising_edge; timing_sense : non_unate; cell_rise(fakeram130_64x64_mem_out_delay_template) { index_1 ("0.044, 1.110"); index_2 ("0.005, 0.500"); values ( \ "0.567, 0.567", \ "0.567, 0.567" \ ) } cell_fall(fakeram130_64x64_mem_out_delay_template) { index_1 ("0.044, 1.110"); index_2 ("0.005, 0.500"); values ( \ "0.567, 0.567", \ "0.567, 0.567" \ ) } rise_transition(fakeram130_64x64_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.044, 1.110") } fall_transition(fakeram130_64x64_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.044, 1.110") } } } pin(we_in){ direction : input; capacitance : 0.005; timing() { related_pin : clk; timing_type : setup_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } timing() { related_pin : clk; timing_type : hold_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } internal_power(){ rise_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } fall_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } } } pin(ce_in){ direction : input; capacitance : 0.005; timing() { related_pin : clk; timing_type : setup_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } timing() { related_pin : clk; timing_type : hold_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } internal_power(){ rise_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } fall_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } } } bus(addr_in) { bus_type : fakeram130_64x64_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : clk; timing_type : setup_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } timing() { related_pin : clk; timing_type : hold_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } internal_power(){ rise_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } fall_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } } } bus(wd_in) { bus_type : fakeram130_64x64_DATA; memory_write() { address : addr_in; clocked_on : "clk"; } direction : input; capacitance : 0.005; timing() { related_pin : clk; timing_type : setup_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } timing() { related_pin : clk; timing_type : hold_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } internal_power(){ when : "(! (we_in) )"; rise_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } fall_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } } internal_power(){ when : "(we_in)"; rise_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } fall_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } } } bus(w_mask_in) { bus_type : fakeram130_64x64_DATA; memory_write() { address : addr_in; clocked_on : "clk"; } direction : input; capacitance : 0.005; timing() { related_pin : clk; timing_type : setup_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } timing() { related_pin : clk; timing_type : hold_rising ; rise_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram130_64x64_constraint_template) { index_1 ("0.044, 1.110"); index_2 ("0.044, 1.110"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } } internal_power(){ when : "(! (we_in) )"; rise_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } fall_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } } internal_power(){ when : "(we_in)"; rise_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } fall_power(fakeram130_64x64_energy_template_sigslew) { index_1 ("0.044, 1.110"); values ("0.160, 0.160") } } } cell_leakage_power : 79.056; } }