// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: nv_ram_rws_256x64.v
module nv_ram_rws_256x64 (
  clk,	//CLKA, CLKB
  ra,   //AA
  re,   //CENA
  dout, //Q
  wa,   //AB
  we,   //CENB
  di,   //DB
  pwrbus_ram_pd
);
parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
// port list
input clk;
input [7:0] ra;
input re;
output [63:0] dout;
input [7:0] wa;
input we;
input [63:0] di;
input [31:0] pwrbus_ram_pd;

//reg and wire list
//Adding in Compiler module
wire stov;	// Self time override: Turn off by default, active high
wire emasa;	// Extra Margin Adjustment read port keeper enable: Default for all voltages
wire tena ;	// Test mode enable A: Turn off by default, active low
wire tenb ;	// Test mode enable B: Turn off by default, active low
wire tcena;	// Test mode chip enable A: Turn off by default, active low
wire tcenb ;	// Test mode chip enable B: Turn off by default, active low
wire sea ;		// Scan enable A: X by default
wire seb ;		// Scan enable B: X by default
wire dftrambyp ;	// Test control input - 0 for mission mode
wire ret1n ;	// Retention mode 1 enable, active low

wire [2:0] emaa;	// Extra margin adjustment A: Default for 0.8V
wire [2:0] emab;	// Extra margin adjustment B: Default for 0.8V
wire [1:0] sia;		// Scan input A
wire [1:0] sib;		// Scan input B
wire [7:0] taa;		// Test address inputs A 
wire [7:0] tab;		// Test address inputs B
wire [63:0] tdb; 	// Test data input

assign stov = 1'b0;	// Retention mode 1 enable, active low
assign emasa = 1'b0;	// Extra Margin Adjustment read port keeper enable: Default for all voltages
assign tena = 1'b1;	// Test mode enable A: Turn off by default, active low
assign tenb = 1'b1;	// Test mode enable B: Turn off by default, active low
assign tcena = 1'b1;	// Test mode chip enable A: Turn off by default, active low
assign tcenb = 1'b1;	// Test mode chip enable B: Turn off by default, active low
assign sea = 1'b1;		// Scan enable A: X by default
assign seb = 1'b1;		// Scan enable B: X by default
assign dftrambyp = 1'b0;	// Test control input - 0 for mission mode
assign ret1n = 1'b1;	// Retention mode 1 enable, active low

assign emaa = 3'b010;	// Extra margin adjustment A: Default for 0.8V
assign emab = 3'b010;	// Extra margin adjustment B: Default for 0.8V
assign sia=2'b0;		// Scan input A
assign sib=2'b0;		// Scan input B
assign taa=8'b0;		// Test address inputs A 
assign tab=8'b0;		// Test address inputs B
assign tdb=64'b0; 	// Test data input

rf_2p_hsc_256x64 rmod (.CENYA(), .AYA(), .CENYB(), .AYB(), .QA(dout), .SOA(), .SOB(), .CLKA(clk), .CENA(re), .AA(ra), .CLKB(clk),
    .CENB(we), .AB(wa), .DB(di), .STOV(stov), .EMAA(emaa), .EMASA(emasa), .EMAB(emab), .TENA(tena), .TCENA(tenb), .TAA(taa), .TENB(tenb), .TCENB(tcenb), .TAB(tab), .TDB(tdb), .SIA(sia), .SEA(sea), .DFTRAMBYP(dftrambyp), .SIB(sib), .SEB(seb), .RET1N(ret1n));

///Commented out behavioral module
//reg [7:0] ra_d;
//wire [63:0] dout;
//reg [63:0] M [255:0];
//always @( posedge clk ) begin
//    if (we)
//       M[wa] <= di;
//end
//always @( posedge clk ) begin
//    if (re)
//       ra_d <= ra;
//end
//assign dout = M[ra_d];
endmodule