//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//| !!!!!!!!!!!! !!!!!!!!!!!!
//| !!!!!!!!!!!! DO NOT EDIT - GENERATED BY VIVA - DO NOT EDIT !!!!!!!!!!!!
//| !!!!!!!!!!!! !!!!!!!!!!!!
//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//| generated by viva: NV_NVDLA_SDP_NRDMA_lat_fifo_lib.vcp --> NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v
//| /home/nvtools/engr/2017/05/16_10_02_50/nvtools/viva/viva -e 'vlib v sv svi svh vt gv bvrl vp defs NULL' -y '. /home/nvtools/engr/2017/05/16_10_02_50/nvtools/rtl/vlib ../../../../../../../../vlib /home/nvtools/engr/2017/03/07_07_35_45/nvtools/assertions /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c0 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c1 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c2 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c3 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c4 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c5 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c6 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c7 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c8 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c9 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c10 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c11 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c12 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c13 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c14 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c15 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c16 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c17 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c18 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c19 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c20 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c21 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c22 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c23 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c24 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c25 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c26 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c27 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c28 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c29 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c30 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c31 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c32 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c33 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c34 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/rams /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/misc /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/analog/common /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/analog/ism /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/analog/pll /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/common /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/mem /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/mipi /home/libs/tlit5_vlibcells/11202192_07042017/librarycells/pads/uphy /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/sdmem /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/usb /home/nvtools/engr/2017/05/25_05_01_38/nvtools/rtl/vlib/sync /home/nvtools/engr/2017/05/25_05_01_38/nvtools/rtl/vlib/sync/nvstd ../../../../include/private/collector/headers/tlit5 ../../../vlibs/tlit5 ../../../include /home/tools/synopsys/syn_2011.09/dw/sim_ver /home/ip/shared/clock/clkgate/1.0/36067466/verilog ../../../vlibs/tlit5/rams/model ./rams/model' -i '. ../../../../include/private/collector/headers/tlit5 /home/nvtools/engr/2017/05/16_10_02_50/nvtools/rtl/include ../../../../../../../inf/sim_helpers/1.0/include/public/rtl /home/nvtools/engr/2017/03/07_07_35_45/nvtools/assertions ../../../../../../../../vlib ../../../vlibs/tlit5 ../../../include /home/tools/synopsys/syn_2011.09/dw/sim_ver /home/ip/shared/inf/ness/2.0/38823533/include/verilog /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/mobile /home/ip/shared/fpga/shared_proto/1.0/38757645/vmod/include /home/ip/shared/fpga/shared_proto/1.0/38757645/vmod/include ../../../vlibs/tlit5/rams/model ./rams/model' -p ' /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/shared /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/mobile /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/archive ../../../plugins' -pf /home/nvtools/engr/2017/06/26_10_09_38/nvtools/viva_plugins/mobile/unit_actmon.pl -d NV_BEHAVIORAL -d NVTOOLS_SYNC2D_GENERIC_CELL -d BEHAVIORAL_AUTOPD_DEFAULT -d JTAGREG_CONFIG=/error_get_source_dir_not_found_might_mean_missing_input_in_t_make_config_but_could_also_indicate_garbage_input_for/__TOP-ip/socd/ip_chip_tools/1.0/defs/public/jtagreg/golden/tlit5/jtagreg.yml NV_NVDLA_SDP_NRDMA_lat_fifo_lib.vcp -o NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v
//nv_large & nv_medium_1024_full
//nv_medium_512
//nv_small & nv_small_256 & nv_small_256_full
//xavier
//#define NVDLA_VMOD_SDP_NRDMA_LATENCY_FIFO_DEPTH4 160
//#define NVDLA_DMA_RD_RSP4 514
//| &Shell ${FIFOGEN} -stdout -m NV_NVDLA_SDP_NRDMA_lat_fifo_::eval(256 )x::eval(257 )
//| -clk_name ::eval($VIVA_CLOCK)
//| -reset_name ::eval($VIVA_RESET)
//| -wr_pipebus lat_wr
//| -rd_pipebus lat_rd
//| -rd_reg
//| -d ::eval(256 )
//| -w ::eval(257 )
//| -ram ra2;
//
// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN
//
// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen
// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_SDP_NRDMA_lat_fifo_256x257 -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_wr -rd_pipebus lat_rd -rd_reg -d 256 -w 257 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)]
// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1
//
// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment
// leda B_1405 OFF -- 2 asynchronous resets in this unit detected
`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1
`include "simulate_x_tick.vh"
module NV_NVDLA_SDP_NRDMA_lat_fifo_256x257 (
nvdla_core_clk
, nvdla_core_rstn
, lat_wr_prdy
, lat_wr_pvld
`ifdef FV_RAND_WR_PAUSE
, lat_wr_pause
`endif
, lat_wr_pd
, lat_rd_prdy
, lat_rd_pvld
, lat_rd_pd
, pwrbus_ram_pd
);
// spyglass disable_block W401 -- clock is not input to module
input nvdla_core_clk;
input nvdla_core_rstn;
output lat_wr_prdy;
input lat_wr_pvld;
`ifdef FV_RAND_WR_PAUSE
input lat_wr_pause;
`endif
input [256:0] lat_wr_pd;
input lat_rd_prdy;
output lat_rd_pvld;
output [256:0] lat_rd_pd;
input [31:0] pwrbus_ram_pd;
// Master Clock Gating (SLCG)
//
// We gate the clock(s) when idle or stalled.
// This allows us to turn off numerous miscellaneous flops
// that don't get gated during synthesis for one reason or another.
//
// We gate write side and read side separately.
// If the fifo is synchronous, we also gate the ram separately, but if
// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified,
// then we use one clk gate for write, ram, and read.
//
wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module
wire nvdla_core_clk_mgated; // used only in synchronous fifos
NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) );
//
// WRITE SIDE
//
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
wire wr_pause_rand; // random stalling
`endif
`endif
// synopsys translate_on
wire wr_reserving;
reg lat_wr_busy_int; // copy for internal use
assign lat_wr_prdy = !lat_wr_busy_int;
assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space?
reg wr_popping; // fwd: write side sees pop?
reg [8:0] lat_wr_count; // write-side count
wire [8:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484
wire [8:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484
wire [8:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_256 = ( wr_count_next_no_wr_popping == 9'd256 );
wire wr_count_next_is_256 = wr_popping ? 1'b0 :
wr_count_next_no_wr_popping_is_256;
wire [8:0] wr_limit_muxed; // muxed with simulation/emulation overrides
wire [8:0] wr_limit_reg = wr_limit_muxed;
`ifdef FV_RAND_WR_PAUSE
// VCS coverage off
wire lat_wr_busy_next = wr_count_next_is_256 || // busy next cycle?
(wr_limit_reg != 9'd0 && // check lat_wr_limit if != 0
wr_count_next >= wr_limit_reg) || lat_wr_pause;
// VCS coverage on
`else
// VCS coverage off
wire lat_wr_busy_next = wr_count_next_is_256 || // busy next cycle?
(wr_limit_reg != 9'd0 && // check lat_wr_limit if != 0
wr_count_next >= wr_limit_reg)
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
|| wr_pause_rand
`endif
`endif
// synopsys translate_on
;
// VCS coverage on
`endif
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_wr_busy_int <= 1'b0;
lat_wr_count <= 9'd0;
end else begin
lat_wr_busy_int <= lat_wr_busy_next;
if ( wr_reserving ^ wr_popping ) begin
lat_wr_count <= wr_count_next;
end
//synopsys translate_off
else if ( !(wr_reserving ^ wr_popping) ) begin
end else begin
lat_wr_count <= {9{`x_or_0}};
end
//synopsys translate_on
end
end
wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld
//
// RAM
//
reg [7:0] lat_wr_adr; // current write address
wire [7:0] lat_rd_adr_p; // read address to use for ram
wire [256:0] lat_rd_pd_p; // read data directly out of ram
wire rd_enable;
wire ore;
wire [31 : 0] pwrbus_ram_pd;
// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen.
// Fifogen handles this by ignoring the data on the ram data out for that cycle.
nv_ram_rwsp_256x257 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram (
.clk ( nvdla_core_clk )
, .pwrbus_ram_pd ( pwrbus_ram_pd )
, .wa ( lat_wr_adr )
, .we ( wr_pushing )
, .di ( lat_wr_pd )
, .ra ( lat_rd_adr_p )
, .re ( rd_enable )
, .dout ( lat_rd_pd_p )
, .ore ( ore )
);
// next lat_wr_adr if wr_pushing=1
wire [7:0] wr_adr_next = lat_wr_adr + 1'd1; // spyglass disable W484
// spyglass disable_block W484
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_wr_adr <= 8'd0;
end else begin
if ( wr_pushing ) begin
lat_wr_adr <= wr_adr_next;
end
//synopsys translate_off
else if ( !(wr_pushing) ) begin
end else begin
lat_wr_adr <= {8{`x_or_0}};
end
//synopsys translate_on
end
end
// spyglass enable_block W484
wire rd_popping; // read side doing pop this cycle?
reg [7:0] lat_rd_adr; // current read address
// next read address
wire [7:0] rd_adr_next = lat_rd_adr + 1'd1; // spyglass disable W484
assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram
// spyglass disable_block W484
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_adr <= 8'd0;
end else begin
if ( rd_popping ) begin
lat_rd_adr <= rd_adr_next;
end
//synopsys translate_off
else if ( !rd_popping ) begin
end else begin
lat_rd_adr <= {8{`x_or_0}};
end
//synopsys translate_on
end
end
// spyglass enable_block W484
//
// SYNCHRONOUS BOUNDARY
//
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
wr_popping <= 1'b0;
end else begin
wr_popping <= rd_popping;
end
end
reg rd_pushing;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
rd_pushing <= 1'b0;
end else begin
rd_pushing <= wr_pushing; // let data go into ram first
end
end
//
// READ SIDE
//
reg lat_rd_pvld_p; // data out of fifo is valid
reg lat_rd_pvld_int; // internal copy of lat_rd_pvld
assign lat_rd_pvld = lat_rd_pvld_int;
assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy);
reg [8:0] lat_rd_count_p; // read-side fifo count
// spyglass disable_block W164a W484
wire [8:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p :
(lat_rd_count_p - 1'd1);
wire [8:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) :
lat_rd_count_p;
// spyglass enable_block W164a W484
wire [8:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
rd_count_p_next_no_rd_popping;
wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0;
wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0;
wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 :
rd_count_p_next_no_rd_popping_not_0;
assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_count_p <= 9'd0;
lat_rd_pvld_p <= 1'b0;
end else begin
if ( rd_pushing || rd_popping ) begin
lat_rd_count_p <= rd_count_p_next;
end
//synopsys translate_off
else if ( !(rd_pushing || rd_popping ) ) begin
end else begin
lat_rd_count_p <= {9{`x_or_0}};
end
//synopsys translate_on
if ( rd_pushing || rd_popping ) begin
lat_rd_pvld_p <= (rd_count_p_next_not_0);
end
//synopsys translate_off
else if ( !(rd_pushing || rd_popping ) ) begin
end else begin
lat_rd_pvld_p <= `x_or_0;
end
//synopsys translate_on
end
end
wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_pvld_int <= 1'b0;
end else begin
lat_rd_pvld_int <= rd_req_next;
end
end
assign lat_rd_pd = lat_rd_pd_p;
assign ore = rd_popping;
// Master Clock Gating (SLCG) Enables
//
// plusarg for disabling this stuff:
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif
// synopsys translate_on
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg wr_pause_rand_dly;
always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
wr_pause_rand_dly <= 1'b0;
end else begin
wr_pause_rand_dly <= wr_pause_rand;
end
end
`endif
`endif
// synopsys translate_on
assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing))
`ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
|| 1'b1
`endif
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
|| master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly)
`endif
`endif
// synopsys translate_on
;
// Simulation and Emulation Overrides of wr_limit(s)
//
`ifdef EMU
`ifdef EMU_FIFO_CFG
// Emulation Global Config Override
//
assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_wr_limit : 9'd0;
`else
// No Global Override for Emulation
//
assign wr_limit_muxed = 9'd0;
`endif // EMU_FIFO_CFG
`else // !EMU
`ifdef SYNTH_LEVEL1_COMPILE
// No Override for GCS Compiles
//
assign wr_limit_muxed = 9'd0;
`else
`ifdef SYNTHESIS
// No Override for RTL Synthesis
//
assign wr_limit_muxed = 9'd0;
`else
// RTL Simulation Plusarg Override
// VCS coverage off
reg wr_limit_override;
reg [8:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 9'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
$display("fifogen reinit initial block %m");
-> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
wr_limit_override = 0;
wr_limit_override_value = 0; // to keep viva happy with dangles
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_wr_limit" ) ) begin
wr_limit_override = 1;
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_wr_limit=%d", wr_limit_override_value);
end
end
// VCS coverage on
`endif
`endif
`endif
// Random Write-Side Stalling
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
// VCS coverage off
// leda W339 OFF -- Non synthesizable operator
// leda W372 OFF -- Undefined PLI task
// leda W373 OFF -- Undefined PLI function
// leda W599 OFF -- This construct is not supported by Synopsys
// leda W430 OFF -- Initial statement is not synthesizable
// leda W182 OFF -- Illegal statement for synthesis
// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants
// leda DCVER_274_NV OFF -- This system task is not supported by DC
integer stall_probability; // prob of stalling
integer stall_cycles_min; // min cycles to stall
integer stall_cycles_max; // max cycles to stall
integer stall_cycles_left; // stall cycles left
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
stall_probability = 0; // no stalling by default
stall_cycles_min = 1;
stall_cycles_max = 10;
`ifdef NO_PLI
`else
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_probability" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_probability=%d", stall_probability);
end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin
$value$plusargs( "default_fifo_stall_probability=%d", stall_probability);
end
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_cycles_min" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_cycles_min=%d", stall_cycles_min);
end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin
$value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min);
end
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_cycles_max" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_cycles_max=%d", stall_cycles_max);
end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin
$value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max);
end
`endif
if ( stall_cycles_min < 1 ) begin
stall_cycles_min = 1;
end
if ( stall_cycles_min > stall_cycles_max ) begin
stall_cycles_max = stall_cycles_min;
end
end
`ifdef NO_PLI
`else
// randomization globals
`ifdef SIMTOP_RANDOMIZE_STALLS
always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability;
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min;
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max;
end
`endif
`endif
always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
stall_cycles_left <= 0;
end else begin
`ifdef NO_PLI
stall_cycles_left <= 0;
`else
if ( lat_wr_pvld && !(!lat_wr_prdy)
&& stall_probability != 0 ) begin
if ( prand_inst0(1, 100) <= stall_probability ) begin
stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max);
end else if ( stall_cycles_left !== 0 ) begin
stall_cycles_left <= stall_cycles_left - 1;
end
end else if ( stall_cycles_left !== 0 ) begin
stall_cycles_left <= stall_cycles_left - 1;
end
`endif
end
end
assign wr_pause_rand = (stall_cycles_left !== 0) ;
// VCS coverage on
`endif
`endif
// synopsys translate_on
// VCS coverage on
// leda W339 ON
// leda W372 ON
// leda W373 ON
// leda W599 ON
// leda W430 ON
// leda W182 ON
// leda W639 ON
// leda DCVER_274_NV ON
//
// Histogram of fifo depth (from write side's perspective)
//
// NOTE: it will reference `SIMTOP.perfmon_enabled, so that
// has to at least be defined, though not initialized.
// tbgen testbenches have it already and various
// ways to turn it on and off.
//
`ifdef PERFMON_HISTOGRAM
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
.clk ( nvdla_core_clk )
, .max ( {23'd0, (wr_limit_reg == 9'd0) ? 9'd256 : wr_limit_reg} )
, .curr ( {23'd0, lat_wr_count} )
);
`endif
`endif
// synopsys translate_on
`endif
// spyglass disable_block W164a W164b W116 W484 W504
`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else
// synopsys translate_off
`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else
// synopsys translate_on
`endif
`ifdef ASSERT_ON
//synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
if ( assert_enabled === 1'b0 ) begin
$display("Asserts are disabled for %m");
end
end
`endif
`endif
//synopsys translate_on
`endif
`endif
// spyglass enable_block W164a W164b W116 W484 W504
//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH
// define is set. This is to aid fifogen team search for fifogen fifo
// instance and module names in a given design.
`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif
// spyglass enable_block W401 -- clock is not input to module
// synopsys dc_script_begin
// set_boundary_optimization find(design, "NV_NVDLA_SDP_NRDMA_lat_fifo_256x257") true
// synopsys dc_script_end
//| &Attachment -no_warn EndModulePrepend;
//| _attach_EndModulePrepend_1;
`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG
// Only verilog needs any local variables
reg [47:0] prand_local_seed0;
reg prand_initialized0;
reg prand_no_rollpli0;
`endif
`endif
`endif
function [31:0] prand_inst0;
//VCS coverage off
input [31:0] min;
input [31:0] max;
reg [32:0] diff;
begin
`ifdef SYNTH_LEVEL1_COMPILE
prand_inst0 = min;
`else
`ifdef SYNTHESIS
prand_inst0 = min;
`else
`ifdef PRAND_VERILOG
if (prand_initialized0 !== 1'b1) begin
prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI");
if (!prand_no_rollpli0)
prand_local_seed0 = {$prand_get_seed(0), 16'b0};
prand_initialized0 = 1'b1;
end
if (prand_no_rollpli0) begin
prand_inst0 = min;
end else begin
diff = max - min + 1;
prand_inst0 = min + prand_local_seed0[47:16] % diff;
// magic numbers taken from Java's random class (same as lrand48)
prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11;
end
`else
`ifdef PRAND_OFF
prand_inst0 = min;
`else
prand_inst0 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
end
//VCS coverage on
endfunction
//| _attach_EndModulePrepend_2;
`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG
// Only verilog needs any local variables
reg [47:0] prand_local_seed1;
reg prand_initialized1;
reg prand_no_rollpli1;
`endif
`endif
`endif
function [31:0] prand_inst1;
//VCS coverage off
input [31:0] min;
input [31:0] max;
reg [32:0] diff;
begin
`ifdef SYNTH_LEVEL1_COMPILE
prand_inst1 = min;
`else
`ifdef SYNTHESIS
prand_inst1 = min;
`else
`ifdef PRAND_VERILOG
if (prand_initialized1 !== 1'b1) begin
prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI");
if (!prand_no_rollpli1)
prand_local_seed1 = {$prand_get_seed(1), 16'b0};
prand_initialized1 = 1'b1;
end
if (prand_no_rollpli1) begin
prand_inst1 = min;
end else begin
diff = max - min + 1;
prand_inst1 = min + prand_local_seed1[47:16] % diff;
// magic numbers taken from Java's random class (same as lrand48)
prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11;
end
`else
`ifdef PRAND_OFF
prand_inst1 = min;
`else
prand_inst1 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
end
//VCS coverage on
endfunction
endmodule // NV_NVDLA_SDP_NRDMA_lat_fifo_256x257
//| &Shell ${FIFOGEN} -stdout -m NV_NVDLA_SDP_NRDMA_lat_fifo_::eval(64 )x::eval(129 )
//| -clk_name ::eval($VIVA_CLOCK)
//| -reset_name ::eval($VIVA_RESET)
//| -wr_pipebus lat_wr
//| -rd_pipebus lat_rd
//| -rd_reg
//| -d ::eval(64 )
//| -w ::eval(129 )
//| -ram ra2;
//
// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN
//
// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen
// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_SDP_NRDMA_lat_fifo_64x129 -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_wr -rd_pipebus lat_rd -rd_reg -d 64 -w 129 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)]
// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1
//
// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment
// leda B_1405 OFF -- 2 asynchronous resets in this unit detected
`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1
`include "simulate_x_tick.vh"
module NV_NVDLA_SDP_NRDMA_lat_fifo_64x129 (
nvdla_core_clk
, nvdla_core_rstn
, lat_wr_prdy
, lat_wr_pvld
`ifdef FV_RAND_WR_PAUSE
, lat_wr_pause
`endif
, lat_wr_pd
, lat_rd_prdy
, lat_rd_pvld
, lat_rd_pd
, pwrbus_ram_pd
);
// spyglass disable_block W401 -- clock is not input to module
input nvdla_core_clk;
input nvdla_core_rstn;
output lat_wr_prdy;
input lat_wr_pvld;
`ifdef FV_RAND_WR_PAUSE
input lat_wr_pause;
`endif
input [128:0] lat_wr_pd;
input lat_rd_prdy;
output lat_rd_pvld;
output [128:0] lat_rd_pd;
input [31:0] pwrbus_ram_pd;
// Master Clock Gating (SLCG)
//
// We gate the clock(s) when idle or stalled.
// This allows us to turn off numerous miscellaneous flops
// that don't get gated during synthesis for one reason or another.
//
// We gate write side and read side separately.
// If the fifo is synchronous, we also gate the ram separately, but if
// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified,
// then we use one clk gate for write, ram, and read.
//
wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module
wire nvdla_core_clk_mgated; // used only in synchronous fifos
NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) );
//
// WRITE SIDE
//
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
wire wr_pause_rand; // random stalling
`endif
`endif
// synopsys translate_on
wire wr_reserving;
reg lat_wr_busy_int; // copy for internal use
assign lat_wr_prdy = !lat_wr_busy_int;
assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space?
reg wr_popping; // fwd: write side sees pop?
reg [6:0] lat_wr_count; // write-side count
wire [6:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484
wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484
wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_64 = ( wr_count_next_no_wr_popping == 7'd64 );
wire wr_count_next_is_64 = wr_popping ? 1'b0 :
wr_count_next_no_wr_popping_is_64;
wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides
wire [6:0] wr_limit_reg = wr_limit_muxed;
`ifdef FV_RAND_WR_PAUSE
// VCS coverage off
wire lat_wr_busy_next = wr_count_next_is_64 || // busy next cycle?
(wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0
wr_count_next >= wr_limit_reg) || lat_wr_pause;
// VCS coverage on
`else
// VCS coverage off
wire lat_wr_busy_next = wr_count_next_is_64 || // busy next cycle?
(wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0
wr_count_next >= wr_limit_reg)
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
|| wr_pause_rand
`endif
`endif
// synopsys translate_on
;
// VCS coverage on
`endif
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_wr_busy_int <= 1'b0;
lat_wr_count <= 7'd0;
end else begin
lat_wr_busy_int <= lat_wr_busy_next;
if ( wr_reserving ^ wr_popping ) begin
lat_wr_count <= wr_count_next;
end
//synopsys translate_off
else if ( !(wr_reserving ^ wr_popping) ) begin
end else begin
lat_wr_count <= {7{`x_or_0}};
end
//synopsys translate_on
end
end
wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld
//
// RAM
//
reg [5:0] lat_wr_adr; // current write address
wire [5:0] lat_rd_adr_p; // read address to use for ram
wire [128:0] lat_rd_pd_p; // read data directly out of ram
wire rd_enable;
wire ore;
wire [31 : 0] pwrbus_ram_pd;
// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen.
// Fifogen handles this by ignoring the data on the ram data out for that cycle.
nv_ram_rwsp_64x129 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram (
.clk ( nvdla_core_clk )
, .pwrbus_ram_pd ( pwrbus_ram_pd )
, .wa ( lat_wr_adr )
, .we ( wr_pushing )
, .di ( lat_wr_pd )
, .ra ( lat_rd_adr_p )
, .re ( rd_enable )
, .dout ( lat_rd_pd_p )
, .ore ( ore )
);
// next lat_wr_adr if wr_pushing=1
wire [5:0] wr_adr_next = lat_wr_adr + 1'd1; // spyglass disable W484
// spyglass disable_block W484
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_wr_adr <= 6'd0;
end else begin
if ( wr_pushing ) begin
lat_wr_adr <= wr_adr_next;
end
//synopsys translate_off
else if ( !(wr_pushing) ) begin
end else begin
lat_wr_adr <= {6{`x_or_0}};
end
//synopsys translate_on
end
end
// spyglass enable_block W484
wire rd_popping; // read side doing pop this cycle?
reg [5:0] lat_rd_adr; // current read address
// next read address
wire [5:0] rd_adr_next = lat_rd_adr + 1'd1; // spyglass disable W484
assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram
// spyglass disable_block W484
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_adr <= 6'd0;
end else begin
if ( rd_popping ) begin
lat_rd_adr <= rd_adr_next;
end
//synopsys translate_off
else if ( !rd_popping ) begin
end else begin
lat_rd_adr <= {6{`x_or_0}};
end
//synopsys translate_on
end
end
// spyglass enable_block W484
//
// SYNCHRONOUS BOUNDARY
//
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
wr_popping <= 1'b0;
end else begin
wr_popping <= rd_popping;
end
end
reg rd_pushing;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
rd_pushing <= 1'b0;
end else begin
rd_pushing <= wr_pushing; // let data go into ram first
end
end
//
// READ SIDE
//
reg lat_rd_pvld_p; // data out of fifo is valid
reg lat_rd_pvld_int; // internal copy of lat_rd_pvld
assign lat_rd_pvld = lat_rd_pvld_int;
assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy);
reg [6:0] lat_rd_count_p; // read-side fifo count
// spyglass disable_block W164a W484
wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p :
(lat_rd_count_p - 1'd1);
wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) :
lat_rd_count_p;
// spyglass enable_block W164a W484
wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
rd_count_p_next_no_rd_popping;
wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0;
wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0;
wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 :
rd_count_p_next_no_rd_popping_not_0;
assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_count_p <= 7'd0;
lat_rd_pvld_p <= 1'b0;
end else begin
if ( rd_pushing || rd_popping ) begin
lat_rd_count_p <= rd_count_p_next;
end
//synopsys translate_off
else if ( !(rd_pushing || rd_popping ) ) begin
end else begin
lat_rd_count_p <= {7{`x_or_0}};
end
//synopsys translate_on
if ( rd_pushing || rd_popping ) begin
lat_rd_pvld_p <= (rd_count_p_next_not_0);
end
//synopsys translate_off
else if ( !(rd_pushing || rd_popping ) ) begin
end else begin
lat_rd_pvld_p <= `x_or_0;
end
//synopsys translate_on
end
end
wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_pvld_int <= 1'b0;
end else begin
lat_rd_pvld_int <= rd_req_next;
end
end
assign lat_rd_pd = lat_rd_pd_p;
assign ore = rd_popping;
// Master Clock Gating (SLCG) Enables
//
// plusarg for disabling this stuff:
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif
// synopsys translate_on
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg wr_pause_rand_dly;
always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
wr_pause_rand_dly <= 1'b0;
end else begin
wr_pause_rand_dly <= wr_pause_rand;
end
end
`endif
`endif
// synopsys translate_on
assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing))
`ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
|| 1'b1
`endif
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
|| master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly)
`endif
`endif
// synopsys translate_on
;
// Simulation and Emulation Overrides of wr_limit(s)
//
`ifdef EMU
`ifdef EMU_FIFO_CFG
// Emulation Global Config Override
//
assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_wr_limit : 7'd0;
`else
// No Global Override for Emulation
//
assign wr_limit_muxed = 7'd0;
`endif // EMU_FIFO_CFG
`else // !EMU
`ifdef SYNTH_LEVEL1_COMPILE
// No Override for GCS Compiles
//
assign wr_limit_muxed = 7'd0;
`else
`ifdef SYNTHESIS
// No Override for RTL Synthesis
//
assign wr_limit_muxed = 7'd0;
`else
// RTL Simulation Plusarg Override
// VCS coverage off
reg wr_limit_override;
reg [6:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
$display("fifogen reinit initial block %m");
-> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
wr_limit_override = 0;
wr_limit_override_value = 0; // to keep viva happy with dangles
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_wr_limit" ) ) begin
wr_limit_override = 1;
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_wr_limit=%d", wr_limit_override_value);
end
end
// VCS coverage on
`endif
`endif
`endif
// Random Write-Side Stalling
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
// VCS coverage off
// leda W339 OFF -- Non synthesizable operator
// leda W372 OFF -- Undefined PLI task
// leda W373 OFF -- Undefined PLI function
// leda W599 OFF -- This construct is not supported by Synopsys
// leda W430 OFF -- Initial statement is not synthesizable
// leda W182 OFF -- Illegal statement for synthesis
// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants
// leda DCVER_274_NV OFF -- This system task is not supported by DC
integer stall_probability; // prob of stalling
integer stall_cycles_min; // min cycles to stall
integer stall_cycles_max; // max cycles to stall
integer stall_cycles_left; // stall cycles left
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
stall_probability = 0; // no stalling by default
stall_cycles_min = 1;
stall_cycles_max = 10;
`ifdef NO_PLI
`else
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_probability" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_probability=%d", stall_probability);
end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin
$value$plusargs( "default_fifo_stall_probability=%d", stall_probability);
end
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_cycles_min" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_cycles_min=%d", stall_cycles_min);
end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin
$value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min);
end
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_cycles_max" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_cycles_max=%d", stall_cycles_max);
end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin
$value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max);
end
`endif
if ( stall_cycles_min < 1 ) begin
stall_cycles_min = 1;
end
if ( stall_cycles_min > stall_cycles_max ) begin
stall_cycles_max = stall_cycles_min;
end
end
`ifdef NO_PLI
`else
// randomization globals
`ifdef SIMTOP_RANDOMIZE_STALLS
always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability;
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min;
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max;
end
`endif
`endif
always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
stall_cycles_left <= 0;
end else begin
`ifdef NO_PLI
stall_cycles_left <= 0;
`else
if ( lat_wr_pvld && !(!lat_wr_prdy)
&& stall_probability != 0 ) begin
if ( prand_inst2(1, 100) <= stall_probability ) begin
stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max);
end else if ( stall_cycles_left !== 0 ) begin
stall_cycles_left <= stall_cycles_left - 1;
end
end else if ( stall_cycles_left !== 0 ) begin
stall_cycles_left <= stall_cycles_left - 1;
end
`endif
end
end
assign wr_pause_rand = (stall_cycles_left !== 0) ;
// VCS coverage on
`endif
`endif
// synopsys translate_on
// VCS coverage on
// leda W339 ON
// leda W372 ON
// leda W373 ON
// leda W599 ON
// leda W430 ON
// leda W182 ON
// leda W639 ON
// leda DCVER_274_NV ON
//
// Histogram of fifo depth (from write side's perspective)
//
// NOTE: it will reference `SIMTOP.perfmon_enabled, so that
// has to at least be defined, though not initialized.
// tbgen testbenches have it already and various
// ways to turn it on and off.
//
`ifdef PERFMON_HISTOGRAM
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
.clk ( nvdla_core_clk )
, .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd64 : wr_limit_reg} )
, .curr ( {25'd0, lat_wr_count} )
);
`endif
`endif
// synopsys translate_on
`endif
// spyglass disable_block W164a W164b W116 W484 W504
`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else
// synopsys translate_off
`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else
// synopsys translate_on
`endif
`ifdef ASSERT_ON
//synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
if ( assert_enabled === 1'b0 ) begin
$display("Asserts are disabled for %m");
end
end
`endif
`endif
//synopsys translate_on
`endif
`endif
// spyglass enable_block W164a W164b W116 W484 W504
//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH
// define is set. This is to aid fifogen team search for fifogen fifo
// instance and module names in a given design.
`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif
// spyglass enable_block W401 -- clock is not input to module
// synopsys dc_script_begin
// set_boundary_optimization find(design, "NV_NVDLA_SDP_NRDMA_lat_fifo_64x129") true
// synopsys dc_script_end
//| &Attachment -no_warn EndModulePrepend;
//| _attach_EndModulePrepend_3;
`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG
// Only verilog needs any local variables
reg [47:0] prand_local_seed2;
reg prand_initialized2;
reg prand_no_rollpli2;
`endif
`endif
`endif
function [31:0] prand_inst2;
//VCS coverage off
input [31:0] min;
input [31:0] max;
reg [32:0] diff;
begin
`ifdef SYNTH_LEVEL1_COMPILE
prand_inst2 = min;
`else
`ifdef SYNTHESIS
prand_inst2 = min;
`else
`ifdef PRAND_VERILOG
if (prand_initialized2 !== 1'b1) begin
prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI");
if (!prand_no_rollpli2)
prand_local_seed2 = {$prand_get_seed(2), 16'b0};
prand_initialized2 = 1'b1;
end
if (prand_no_rollpli2) begin
prand_inst2 = min;
end else begin
diff = max - min + 1;
prand_inst2 = min + prand_local_seed2[47:16] % diff;
// magic numbers taken from Java's random class (same as lrand48)
prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11;
end
`else
`ifdef PRAND_OFF
prand_inst2 = min;
`else
prand_inst2 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
end
//VCS coverage on
endfunction
//| _attach_EndModulePrepend_4;
`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG
// Only verilog needs any local variables
reg [47:0] prand_local_seed3;
reg prand_initialized3;
reg prand_no_rollpli3;
`endif
`endif
`endif
function [31:0] prand_inst3;
//VCS coverage off
input [31:0] min;
input [31:0] max;
reg [32:0] diff;
begin
`ifdef SYNTH_LEVEL1_COMPILE
prand_inst3 = min;
`else
`ifdef SYNTHESIS
prand_inst3 = min;
`else
`ifdef PRAND_VERILOG
if (prand_initialized3 !== 1'b1) begin
prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI");
if (!prand_no_rollpli3)
prand_local_seed3 = {$prand_get_seed(3), 16'b0};
prand_initialized3 = 1'b1;
end
if (prand_no_rollpli3) begin
prand_inst3 = min;
end else begin
diff = max - min + 1;
prand_inst3 = min + prand_local_seed3[47:16] % diff;
// magic numbers taken from Java's random class (same as lrand48)
prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11;
end
`else
`ifdef PRAND_OFF
prand_inst3 = min;
`else
prand_inst3 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
end
//VCS coverage on
endfunction
endmodule // NV_NVDLA_SDP_NRDMA_lat_fifo_64x129
//| &Shell ${FIFOGEN} -stdout -m NV_NVDLA_SDP_NRDMA_lat_fifo_::eval(16 )x::eval(65 )
//| -clk_name ::eval($VIVA_CLOCK)
//| -reset_name ::eval($VIVA_RESET)
//| -wr_pipebus lat_wr
//| -rd_pipebus lat_rd
//| -rd_reg
//| -d ::eval(16 )
//| -w ::eval(65 )
//| -ram ra2;
//
// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN
//
// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen
// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_SDP_NRDMA_lat_fifo_16x65 -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_wr -rd_pipebus lat_rd -rd_reg -d 16 -w 65 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)]
// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1
//
// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment
// leda B_1405 OFF -- 2 asynchronous resets in this unit detected
`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1
`include "simulate_x_tick.vh"
module NV_NVDLA_SDP_NRDMA_lat_fifo_16x65 (
nvdla_core_clk
, nvdla_core_rstn
, lat_wr_prdy
, lat_wr_pvld
`ifdef FV_RAND_WR_PAUSE
, lat_wr_pause
`endif
, lat_wr_pd
, lat_rd_prdy
, lat_rd_pvld
, lat_rd_pd
, pwrbus_ram_pd
);
// spyglass disable_block W401 -- clock is not input to module
input nvdla_core_clk;
input nvdla_core_rstn;
output lat_wr_prdy;
input lat_wr_pvld;
`ifdef FV_RAND_WR_PAUSE
input lat_wr_pause;
`endif
input [64:0] lat_wr_pd;
input lat_rd_prdy;
output lat_rd_pvld;
output [64:0] lat_rd_pd;
input [31:0] pwrbus_ram_pd;
// Master Clock Gating (SLCG)
//
// We gate the clock(s) when idle or stalled.
// This allows us to turn off numerous miscellaneous flops
// that don't get gated during synthesis for one reason or another.
//
// We gate write side and read side separately.
// If the fifo is synchronous, we also gate the ram separately, but if
// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified,
// then we use one clk gate for write, ram, and read.
//
wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module
wire nvdla_core_clk_mgated; // used only in synchronous fifos
NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) );
//
// WRITE SIDE
//
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
wire wr_pause_rand; // random stalling
`endif
`endif
// synopsys translate_on
wire wr_reserving;
reg lat_wr_busy_int; // copy for internal use
assign lat_wr_prdy = !lat_wr_busy_int;
assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space?
reg wr_popping; // fwd: write side sees pop?
reg [4:0] lat_wr_count; // write-side count
wire [4:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484
wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484
wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_16 = ( wr_count_next_no_wr_popping == 5'd16 );
wire wr_count_next_is_16 = wr_popping ? 1'b0 :
wr_count_next_no_wr_popping_is_16;
wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides
wire [4:0] wr_limit_reg = wr_limit_muxed;
`ifdef FV_RAND_WR_PAUSE
// VCS coverage off
wire lat_wr_busy_next = wr_count_next_is_16 || // busy next cycle?
(wr_limit_reg != 5'd0 && // check lat_wr_limit if != 0
wr_count_next >= wr_limit_reg) || lat_wr_pause;
// VCS coverage on
`else
// VCS coverage off
wire lat_wr_busy_next = wr_count_next_is_16 || // busy next cycle?
(wr_limit_reg != 5'd0 && // check lat_wr_limit if != 0
wr_count_next >= wr_limit_reg)
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
|| wr_pause_rand
`endif
`endif
// synopsys translate_on
;
// VCS coverage on
`endif
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_wr_busy_int <= 1'b0;
lat_wr_count <= 5'd0;
end else begin
lat_wr_busy_int <= lat_wr_busy_next;
if ( wr_reserving ^ wr_popping ) begin
lat_wr_count <= wr_count_next;
end
//synopsys translate_off
else if ( !(wr_reserving ^ wr_popping) ) begin
end else begin
lat_wr_count <= {5{`x_or_0}};
end
//synopsys translate_on
end
end
wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld
//
// RAM
//
reg [3:0] lat_wr_adr; // current write address
wire [3:0] lat_rd_adr_p; // read address to use for ram
wire [64:0] lat_rd_pd_p; // read data directly out of ram
wire rd_enable;
wire ore;
wire [31 : 0] pwrbus_ram_pd;
// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen.
// Fifogen handles this by ignoring the data on the ram data out for that cycle.
nv_ram_rwsp_16x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram (
.clk ( nvdla_core_clk )
, .pwrbus_ram_pd ( pwrbus_ram_pd )
, .wa ( lat_wr_adr )
, .we ( wr_pushing )
, .di ( lat_wr_pd )
, .ra ( lat_rd_adr_p )
, .re ( rd_enable )
, .dout ( lat_rd_pd_p )
, .ore ( ore )
);
// next lat_wr_adr if wr_pushing=1
wire [3:0] wr_adr_next = lat_wr_adr + 1'd1; // spyglass disable W484
// spyglass disable_block W484
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_wr_adr <= 4'd0;
end else begin
if ( wr_pushing ) begin
lat_wr_adr <= wr_adr_next;
end
//synopsys translate_off
else if ( !(wr_pushing) ) begin
end else begin
lat_wr_adr <= {4{`x_or_0}};
end
//synopsys translate_on
end
end
// spyglass enable_block W484
wire rd_popping; // read side doing pop this cycle?
reg [3:0] lat_rd_adr; // current read address
// next read address
wire [3:0] rd_adr_next = lat_rd_adr + 1'd1; // spyglass disable W484
assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram
// spyglass disable_block W484
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_adr <= 4'd0;
end else begin
if ( rd_popping ) begin
lat_rd_adr <= rd_adr_next;
end
//synopsys translate_off
else if ( !rd_popping ) begin
end else begin
lat_rd_adr <= {4{`x_or_0}};
end
//synopsys translate_on
end
end
// spyglass enable_block W484
//
// SYNCHRONOUS BOUNDARY
//
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
wr_popping <= 1'b0;
end else begin
wr_popping <= rd_popping;
end
end
reg rd_pushing;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
rd_pushing <= 1'b0;
end else begin
rd_pushing <= wr_pushing; // let data go into ram first
end
end
//
// READ SIDE
//
reg lat_rd_pvld_p; // data out of fifo is valid
reg lat_rd_pvld_int; // internal copy of lat_rd_pvld
assign lat_rd_pvld = lat_rd_pvld_int;
assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy);
reg [4:0] lat_rd_count_p; // read-side fifo count
// spyglass disable_block W164a W484
wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p :
(lat_rd_count_p - 1'd1);
wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) :
lat_rd_count_p;
// spyglass enable_block W164a W484
wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
rd_count_p_next_no_rd_popping;
wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0;
wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0;
wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 :
rd_count_p_next_no_rd_popping_not_0;
assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_count_p <= 5'd0;
lat_rd_pvld_p <= 1'b0;
end else begin
if ( rd_pushing || rd_popping ) begin
lat_rd_count_p <= rd_count_p_next;
end
//synopsys translate_off
else if ( !(rd_pushing || rd_popping ) ) begin
end else begin
lat_rd_count_p <= {5{`x_or_0}};
end
//synopsys translate_on
if ( rd_pushing || rd_popping ) begin
lat_rd_pvld_p <= (rd_count_p_next_not_0);
end
//synopsys translate_off
else if ( !(rd_pushing || rd_popping ) ) begin
end else begin
lat_rd_pvld_p <= `x_or_0;
end
//synopsys translate_on
end
end
wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
lat_rd_pvld_int <= 1'b0;
end else begin
lat_rd_pvld_int <= rd_req_next;
end
end
assign lat_rd_pd = lat_rd_pd_p;
assign ore = rd_popping;
// Master Clock Gating (SLCG) Enables
//
// plusarg for disabling this stuff:
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif
// synopsys translate_on
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg wr_pause_rand_dly;
always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
wr_pause_rand_dly <= 1'b0;
end else begin
wr_pause_rand_dly <= wr_pause_rand;
end
end
`endif
`endif
// synopsys translate_on
assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing))
`ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
|| 1'b1
`endif
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
|| master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly)
`endif
`endif
// synopsys translate_on
;
// Simulation and Emulation Overrides of wr_limit(s)
//
`ifdef EMU
`ifdef EMU_FIFO_CFG
// Emulation Global Config Override
//
assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_wr_limit : 5'd0;
`else
// No Global Override for Emulation
//
assign wr_limit_muxed = 5'd0;
`endif // EMU_FIFO_CFG
`else // !EMU
`ifdef SYNTH_LEVEL1_COMPILE
// No Override for GCS Compiles
//
assign wr_limit_muxed = 5'd0;
`else
`ifdef SYNTHESIS
// No Override for RTL Synthesis
//
assign wr_limit_muxed = 5'd0;
`else
// RTL Simulation Plusarg Override
// VCS coverage off
reg wr_limit_override;
reg [4:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
$display("fifogen reinit initial block %m");
-> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
wr_limit_override = 0;
wr_limit_override_value = 0; // to keep viva happy with dangles
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_wr_limit" ) ) begin
wr_limit_override = 1;
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_wr_limit=%d", wr_limit_override_value);
end
end
// VCS coverage on
`endif
`endif
`endif
// Random Write-Side Stalling
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
// VCS coverage off
// leda W339 OFF -- Non synthesizable operator
// leda W372 OFF -- Undefined PLI task
// leda W373 OFF -- Undefined PLI function
// leda W599 OFF -- This construct is not supported by Synopsys
// leda W430 OFF -- Initial statement is not synthesizable
// leda W182 OFF -- Illegal statement for synthesis
// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants
// leda DCVER_274_NV OFF -- This system task is not supported by DC
integer stall_probability; // prob of stalling
integer stall_cycles_min; // min cycles to stall
integer stall_cycles_max; // max cycles to stall
integer stall_cycles_left; // stall cycles left
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
stall_probability = 0; // no stalling by default
stall_cycles_min = 1;
stall_cycles_max = 10;
`ifdef NO_PLI
`else
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_probability" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_probability=%d", stall_probability);
end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin
$value$plusargs( "default_fifo_stall_probability=%d", stall_probability);
end
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_cycles_min" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_cycles_min=%d", stall_cycles_min);
end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin
$value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min);
end
if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_cycles_max" ) ) begin
$value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_cycles_max=%d", stall_cycles_max);
end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin
$value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max);
end
`endif
if ( stall_cycles_min < 1 ) begin
stall_cycles_min = 1;
end
if ( stall_cycles_min > stall_cycles_max ) begin
stall_cycles_max = stall_cycles_min;
end
end
`ifdef NO_PLI
`else
// randomization globals
`ifdef SIMTOP_RANDOMIZE_STALLS
always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability;
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min;
if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max;
end
`endif
`endif
always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
stall_cycles_left <= 0;
end else begin
`ifdef NO_PLI
stall_cycles_left <= 0;
`else
if ( lat_wr_pvld && !(!lat_wr_prdy)
&& stall_probability != 0 ) begin
if ( prand_inst4(1, 100) <= stall_probability ) begin
stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max);
end else if ( stall_cycles_left !== 0 ) begin
stall_cycles_left <= stall_cycles_left - 1;
end
end else if ( stall_cycles_left !== 0 ) begin
stall_cycles_left <= stall_cycles_left - 1;
end
`endif
end
end
assign wr_pause_rand = (stall_cycles_left !== 0) ;
// VCS coverage on
`endif
`endif
// synopsys translate_on
// VCS coverage on
// leda W339 ON
// leda W372 ON
// leda W373 ON
// leda W599 ON
// leda W430 ON
// leda W182 ON
// leda W639 ON
// leda DCVER_274_NV ON
//
// Histogram of fifo depth (from write side's perspective)
//
// NOTE: it will reference `SIMTOP.perfmon_enabled, so that
// has to at least be defined, though not initialized.
// tbgen testbenches have it already and various
// ways to turn it on and off.
//
`ifdef PERFMON_HISTOGRAM
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
.clk ( nvdla_core_clk )
, .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd16 : wr_limit_reg} )
, .curr ( {27'd0, lat_wr_count} )
);
`endif
`endif
// synopsys translate_on
`endif
// spyglass disable_block W164a W164b W116 W484 W504
`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else
// synopsys translate_off
`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else
// synopsys translate_on
`endif
`ifdef ASSERT_ON
//synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
if ( assert_enabled === 1'b0 ) begin
$display("Asserts are disabled for %m");
end
end
`endif
`endif
//synopsys translate_on
`endif
`endif
// spyglass enable_block W164a W164b W116 W484 W504
//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH
// define is set. This is to aid fifogen team search for fifogen fifo
// instance and module names in a given design.
`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif
// spyglass enable_block W401 -- clock is not input to module
// synopsys dc_script_begin
// set_boundary_optimization find(design, "NV_NVDLA_SDP_NRDMA_lat_fifo_16x65") true
// synopsys dc_script_end
//| &Attachment -no_warn EndModulePrepend;
//| _attach_EndModulePrepend_5;
`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG
// Only verilog needs any local variables
reg [47:0] prand_local_seed4;
reg prand_initialized4;
reg prand_no_rollpli4;
`endif
`endif
`endif
function [31:0] prand_inst4;
//VCS coverage off
input [31:0] min;
input [31:0] max;
reg [32:0] diff;
begin
`ifdef SYNTH_LEVEL1_COMPILE
prand_inst4 = min;
`else
`ifdef SYNTHESIS
prand_inst4 = min;
`else
`ifdef PRAND_VERILOG
if (prand_initialized4 !== 1'b1) begin
prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI");
if (!prand_no_rollpli4)
prand_local_seed4 = {$prand_get_seed(4), 16'b0};
prand_initialized4 = 1'b1;
end
if (prand_no_rollpli4) begin
prand_inst4 = min;
end else begin
diff = max - min + 1;
prand_inst4 = min + prand_local_seed4[47:16] % diff;
// magic numbers taken from Java's random class (same as lrand48)
prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11;
end
`else
`ifdef PRAND_OFF
prand_inst4 = min;
`else
prand_inst4 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
end
//VCS coverage on
endfunction
//| _attach_EndModulePrepend_6;
`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG
// Only verilog needs any local variables
reg [47:0] prand_local_seed5;
reg prand_initialized5;
reg prand_no_rollpli5;
`endif
`endif
`endif
function [31:0] prand_inst5;
//VCS coverage off
input [31:0] min;
input [31:0] max;
reg [32:0] diff;
begin
`ifdef SYNTH_LEVEL1_COMPILE
prand_inst5 = min;
`else
`ifdef SYNTHESIS
prand_inst5 = min;
`else
`ifdef PRAND_VERILOG
if (prand_initialized5 !== 1'b1) begin
prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI");
if (!prand_no_rollpli5)
prand_local_seed5 = {$prand_get_seed(5), 16'b0};
prand_initialized5 = 1'b1;
end
if (prand_no_rollpli5) begin
prand_inst5 = min;
end else begin
diff = max - min + 1;
prand_inst5 = min + prand_local_seed5[47:16] % diff;
// magic numbers taken from Java's random class (same as lrand48)
prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11;
end
`else
`ifdef PRAND_OFF
prand_inst5 = min;
`else
prand_inst5 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
end
//VCS coverage on
endfunction
endmodule // NV_NVDLA_SDP_NRDMA_lat_fifo_16x65
/*
&Shell ${FIFOGEN} -stdout -m NV_NVDLA_SDP_NRDMA_lat_fifo_::eval(NVDLA_VMOD_SDP_NRDMA_LATENCY_FIFO_DEPTH3)x::eval(NVDLA_DMA_RD_RSP3)
-clk_name ::eval($VIVA_CLOCK)
-reset_name ::eval($VIVA_RESET)
-wr_pipebus lat_wr
-rd_pipebus lat_rd
-rd_reg
-d ::eval(NVDLA_VMOD_SDP_NRDMA_LATENCY_FIFO_DEPTH3)
-w ::eval(NVDLA_DMA_RD_RSP3)
-ram ra2;
&Shell ${FIFOGEN} -stdout -m NV_NVDLA_SDP_NRDMA_lat_fifo_::eval(NVDLA_VMOD_SDP_NRDMA_LATENCY_FIFO_DEPTH4)x::eval(NVDLA_DMA_RD_RSP4)
-clk_name ::eval($VIVA_CLOCK)
-reset_name ::eval($VIVA_RESET)
-wr_pipebus lat_wr
-rd_pipebus lat_rd
-rd_reg
-d ::eval(NVDLA_VMOD_SDP_NRDMA_LATENCY_FIFO_DEPTH4)
-w ::eval(NVDLA_DMA_RD_RSP4)
-ram ra2;
*/