//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//| !!!!!!!!!!!! !!!!!!!!!!!!
//| !!!!!!!!!!!! DO NOT EDIT - GENERATED BY VIVA - DO NOT EDIT !!!!!!!!!!!!
//| !!!!!!!!!!!! !!!!!!!!!!!!
//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//| generated by viva: NV_NVDLA_CDP_RDMA_cqs.vcp --> NV_NVDLA_CDP_RDMA_cqs.v
//| /home/nvtools/engr/2017/05/16_10_02_50/nvtools/viva/viva -e 'vlib v sv svi svh vt gv bvrl vp defs NULL' -y '. /home/nvtools/engr/2017/05/16_10_02_50/nvtools/rtl/vlib ../../../../../../../../vlib /home/nvtools/engr/2017/03/07_07_35_45/nvtools/assertions /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c0 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c1 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c2 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c3 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c4 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c5 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c6 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c7 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c8 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c9 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c10 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c11 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c12 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c13 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c14 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c15 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c16 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c17 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c18 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c19 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c20 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c21 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c22 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c23 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c24 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c25 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c26 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c27 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c28 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c29 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c30 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c31 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c32 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c33 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/stdcell/c34 /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/rams /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/misc /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/analog/common /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/analog/ism /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/analog/pll /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/common /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/mem /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/mipi /home/libs/tlit5_vlibcells/11202192_07042017/librarycells/pads/uphy /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/sdmem /home/libs/tlit5_vlibcells/11221199_07072017/librarycells/pads/usb /home/nvtools/engr/2017/05/25_05_01_38/nvtools/rtl/vlib/sync /home/nvtools/engr/2017/05/25_05_01_38/nvtools/rtl/vlib/sync/nvstd ../../../../include/private/collector/headers/tlit5 ../../../vlibs/tlit5 ../../../include /home/ip/shared/clock/clkgate/1.0/36067466/verilog ../../../vlibs/tlit5/rams/model ./rams/model' -i '. ../../../../include/private/collector/headers/tlit5 /home/nvtools/engr/2017/05/16_10_02_50/nvtools/rtl/include ../../../../../../../inf/sim_helpers/1.0/include/public/rtl /home/nvtools/engr/2017/03/07_07_35_45/nvtools/assertions ../../../../../../../../vlib ../../../vlibs/tlit5 ../../../include /home/ip/shared/inf/ness/2.0/38823533/include/verilog /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/mobile /home/ip/shared/fpga/shared_proto/1.0/38757645/vmod/include /home/ip/shared/fpga/shared_proto/1.0/38757645/vmod/include ../../../vlibs/tlit5/rams/model ./rams/model' -p ' /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/shared /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/mobile /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/archive ../../../plugins' -pf /home/nvtools/engr/2017/06/26_10_09_38/nvtools/viva_plugins/mobile/unit_actmon.pl -d NV_BEHAVIORAL -d NVTOOLS_SYNC2D_GENERIC_CELL -d BEHAVIORAL_AUTOPD_DEFAULT -d JTAGREG_CONFIG=/error_get_source_dir_not_found_might_mean_missing_input_in_t_make_config_but_could_also_indicate_garbage_input_for/__TOP-ip/socd/ip_chip_tools/1.0/defs/public/jtagreg/golden/tlit5/jtagreg.yml NV_NVDLA_CDP_RDMA_cqs.vcp -o NV_NVDLA_CDP_RDMA_cqs.v
//| &Shell ${FIFOGEN} -stdout -m NV_NVDLA_CDP_RDMA_cq
//| -clk_name ::eval($VIVA_CLOCK)
//| -reset_name ::eval($VIVA_RESET)
//| -wr_pipebus cq_wr
//| -rd_pipebus cq_rd
//| -rd_reg
//| -d 256
//| -w 7
//| -rand_none
//| -ram ff;
//
// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN
//
// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen
// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_RDMA_cq -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus cq_wr -rd_pipebus cq_rd -rd_reg -d 256 -w 7 -rand_none -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)]
// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1
//
// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment
// leda B_1405 OFF -- 2 asynchronous resets in this unit detected
`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1
`include "simulate_x_tick.vh"
module NV_NVDLA_CDP_RDMA_cq (
nvdla_core_clk
, nvdla_core_rstn
, cq_wr_prdy
, cq_wr_pvld
, cq_wr_pd
, cq_rd_prdy
, cq_rd_pvld
, cq_rd_pd
, pwrbus_ram_pd
);
// spyglass disable_block W401 -- clock is not input to module
input nvdla_core_clk;
input nvdla_core_rstn;
output cq_wr_prdy;
input cq_wr_pvld;
input [6:0] cq_wr_pd;
input cq_rd_prdy;
output cq_rd_pvld;
output [6:0] cq_rd_pd;
input [31:0] pwrbus_ram_pd;
// Master Clock Gating (SLCG)
//
// We gate the clock(s) when idle or stalled.
// This allows us to turn off numerous miscellaneous flops
// that don't get gated during synthesis for one reason or another.
//
// We gate write side and read side separately.
// If the fifo is synchronous, we also gate the ram separately, but if
// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified,
// then we use one clk gate for write, ram, and read.
//
wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module
wire nvdla_core_clk_mgated; // used only in synchronous fifos
NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) );
//
// WRITE SIDE
//
wire wr_reserving;
reg cq_wr_busy_int; // copy for internal use
assign cq_wr_prdy = !cq_wr_busy_int;
assign wr_reserving = cq_wr_pvld && !cq_wr_busy_int; // reserving write space?
reg wr_popping; // fwd: write side sees pop?
reg [8:0] cq_wr_count; // write-side count
wire [8:0] wr_count_next_wr_popping = wr_reserving ? cq_wr_count : (cq_wr_count - 1'd1); // spyglass disable W164a W484
wire [8:0] wr_count_next_no_wr_popping = wr_reserving ? (cq_wr_count + 1'd1) : cq_wr_count; // spyglass disable W164a W484
wire [8:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_256 = ( wr_count_next_no_wr_popping == 9'd256 );
wire wr_count_next_is_256 = wr_popping ? 1'b0 :
wr_count_next_no_wr_popping_is_256;
wire [8:0] wr_limit_muxed; // muxed with simulation/emulation overrides
wire [8:0] wr_limit_reg = wr_limit_muxed;
// VCS coverage off
wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle?
(wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0
wr_count_next >= wr_limit_reg) ;
// VCS coverage on
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
cq_wr_busy_int <= 1'b0;
cq_wr_count <= 9'd0;
end else begin
cq_wr_busy_int <= cq_wr_busy_next;
if ( wr_reserving ^ wr_popping ) begin
cq_wr_count <= wr_count_next;
end
//synopsys translate_off
else if ( !(wr_reserving ^ wr_popping) ) begin
end else begin
cq_wr_count <= {9{`x_or_0}};
end
//synopsys translate_on
end
end
wire wr_pushing = wr_reserving; // data pushed same cycle as cq_wr_pvld
//
// RAM
//
reg [7:0] cq_wr_adr; // current write address
// spyglass disable_block W484
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
cq_wr_adr <= 8'd0;
end else begin
if ( wr_pushing ) begin
cq_wr_adr <= cq_wr_adr + 1'd1;
end
end
end
// spyglass enable_block W484
reg [7:0] cq_rd_adr; // read address this cycle
wire ram_we = wr_pushing; // note: write occurs next cycle
wire [6:0] cq_rd_pd_p; // read data out of ram
wire [31 : 0] pwrbus_ram_pd;
// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen.
// Fifogen handles this by ignoring the data on the ram data out for that cycle.
NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7 ram (
.clk( nvdla_core_clk_mgated )
, .pwrbus_ram_pd ( pwrbus_ram_pd )
, .di ( cq_wr_pd )
, .we ( ram_we )
, .wa ( cq_wr_adr )
, .ra ( cq_rd_adr )
, .dout ( cq_rd_pd_p )
);
wire rd_popping; // read side doing pop this cycle?
wire [7:0] rd_adr_next_popping = cq_rd_adr + 1'd1; // spyglass disable W484
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
cq_rd_adr <= 8'd0;
end else begin
if ( rd_popping ) begin
cq_rd_adr <= rd_adr_next_popping;
end
//synopsys translate_off
else if ( !rd_popping ) begin
end else begin
cq_rd_adr <= {8{`x_or_0}};
end
//synopsys translate_on
end
end
//
// SYNCHRONOUS BOUNDARY
//
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
wr_popping <= 1'b0;
end else begin
wr_popping <= rd_popping;
end
end
wire rd_pushing = wr_pushing; // let it be seen immediately
//
// READ SIDE
//
reg cq_rd_pvld_p; // data out of fifo is valid
reg cq_rd_pvld_int; // internal copy of cq_rd_pvld
assign cq_rd_pvld = cq_rd_pvld_int;
assign rd_popping = cq_rd_pvld_p && !(cq_rd_pvld_int && !cq_rd_prdy);
reg [8:0] cq_rd_count_p; // read-side fifo count
// spyglass disable_block W164a W484
wire [8:0] rd_count_p_next_rd_popping = rd_pushing ? cq_rd_count_p :
(cq_rd_count_p - 1'd1);
wire [8:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq_rd_count_p + 1'd1) :
cq_rd_count_p;
// spyglass enable_block W164a W484
wire [8:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
rd_count_p_next_no_rd_popping;
wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0;
wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0;
wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 :
rd_count_p_next_no_rd_popping_not_0;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
cq_rd_count_p <= 9'd0;
cq_rd_pvld_p <= 1'b0;
end else begin
if ( rd_pushing || rd_popping ) begin
cq_rd_count_p <= rd_count_p_next;
end
//synopsys translate_off
else if ( !(rd_pushing || rd_popping ) ) begin
end else begin
cq_rd_count_p <= {9{`x_or_0}};
end
//synopsys translate_on
if ( rd_pushing || rd_popping ) begin
cq_rd_pvld_p <= (rd_count_p_next_not_0);
end
//synopsys translate_off
else if ( !(rd_pushing || rd_popping ) ) begin
end else begin
cq_rd_pvld_p <= `x_or_0;
end
//synopsys translate_on
end
end
reg [6:0] cq_rd_pd; // output data register
wire rd_req_next = (cq_rd_pvld_p || (cq_rd_pvld_int && !cq_rd_prdy)) ;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
if ( !nvdla_core_rstn ) begin
cq_rd_pvld_int <= 1'b0;
end else begin
cq_rd_pvld_int <= rd_req_next;
end
end
always @( posedge nvdla_core_clk_mgated ) begin
if ( (rd_popping) ) begin
cq_rd_pd <= cq_rd_pd_p;
end
//synopsys translate_off
else if ( !((rd_popping)) ) begin
end else begin
cq_rd_pd <= {7{`x_or_0}};
end
//synopsys translate_on
end
// Master Clock Gating (SLCG) Enables
//
// plusarg for disabling this stuff:
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif
// synopsys translate_on
assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (cq_wr_pvld && !cq_wr_busy_int) || (cq_wr_busy_int != cq_wr_busy_next)) || (rd_pushing || rd_popping || (cq_rd_pvld_int && cq_rd_prdy)) || (wr_pushing))
`ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
|| 1'b1
`endif
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
|| master_clk_gating_disabled
`endif
`endif
// synopsys translate_on
;
// Simulation and Emulation Overrides of wr_limit(s)
//
`ifdef EMU
`ifdef EMU_FIFO_CFG
// Emulation Global Config Override
//
assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_cq_wr_limit : 9'd0;
`else
// No Global Override for Emulation
//
assign wr_limit_muxed = 9'd0;
`endif // EMU_FIFO_CFG
`else // !EMU
`ifdef SYNTH_LEVEL1_COMPILE
// No Override for GCS Compiles
//
assign wr_limit_muxed = 9'd0;
`else
`ifdef SYNTHESIS
// No Override for RTL Synthesis
//
assign wr_limit_muxed = 9'd0;
`else
// RTL Simulation Plusarg Override
// VCS coverage off
reg wr_limit_override;
reg [8:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 9'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
$display("fifogen reinit initial block %m");
-> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
wr_limit_override = 0;
wr_limit_override_value = 0; // to keep viva happy with dangles
if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_cq_wr_limit" ) ) begin
wr_limit_override = 1;
$value$plusargs( "NV_NVDLA_CDP_RDMA_cq_wr_limit=%d", wr_limit_override_value);
end
end
// VCS coverage on
`endif
`endif
`endif
//
// Histogram of fifo depth (from write side's perspective)
//
// NOTE: it will reference `SIMTOP.perfmon_enabled, so that
// has to at least be defined, though not initialized.
// tbgen testbenches have it already and various
// ways to turn it on and off.
//
`ifdef PERFMON_HISTOGRAM
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
.clk ( nvdla_core_clk )
, .max ( {23'd0, (wr_limit_reg == 9'd0) ? 9'd256 : wr_limit_reg} )
, .curr ( {23'd0, cq_wr_count} )
);
`endif
`endif
// synopsys translate_on
`endif
// spyglass disable_block W164a W164b W116 W484 W504
`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else
// synopsys translate_off
`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else
// synopsys translate_on
`endif
`ifdef ASSERT_ON
//synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
if ( assert_enabled === 1'b0 ) begin
$display("Asserts are disabled for %m");
end
end
`endif
`endif
//synopsys translate_on
`endif
`endif
// spyglass enable_block W164a W164b W116 W484 W504
//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH
// define is set. This is to aid fifogen team search for fifogen fifo
// instance and module names in a given design.
`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif
// spyglass enable_block W401 -- clock is not input to module
// synopsys dc_script_begin
// set_boundary_optimization find(design, "NV_NVDLA_CDP_RDMA_cq") true
// synopsys dc_script_end
//| &Attachment -no_warn EndModulePrepend;
endmodule // NV_NVDLA_CDP_RDMA_cq
//
// Flop-Based RAM
//
module NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7 (
clk
, pwrbus_ram_pd
, di
, we
, wa
, ra
, dout
);
input clk; // write clock
input [31 : 0] pwrbus_ram_pd;
input [6:0] di;
input we;
input [7:0] wa;
input [7:0] ra;
output [6:0] dout;
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31]));
`ifdef EMU
// we use an emulation ram here to save flops on the emulation board
// so that the monstrous chip can fit :-)
//
reg [7:0] Wa0_vmw;
reg we0_vmw;
reg [6:0] Di0_vmw;
always @( posedge clk ) begin
Wa0_vmw <= wa;
we0_vmw <= we;
Di0_vmw <= di;
end
vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7 emu_ram (
.Wa0( Wa0_vmw )
, .we0( we0_vmw )
, .Di0( Di0_vmw )
, .Ra0( ra )
, .Do0( dout )
);
`else
reg [6:0] ram_ff0;
reg [6:0] ram_ff1;
reg [6:0] ram_ff2;
reg [6:0] ram_ff3;
reg [6:0] ram_ff4;
reg [6:0] ram_ff5;
reg [6:0] ram_ff6;
reg [6:0] ram_ff7;
reg [6:0] ram_ff8;
reg [6:0] ram_ff9;
reg [6:0] ram_ff10;
reg [6:0] ram_ff11;
reg [6:0] ram_ff12;
reg [6:0] ram_ff13;
reg [6:0] ram_ff14;
reg [6:0] ram_ff15;
reg [6:0] ram_ff16;
reg [6:0] ram_ff17;
reg [6:0] ram_ff18;
reg [6:0] ram_ff19;
reg [6:0] ram_ff20;
reg [6:0] ram_ff21;
reg [6:0] ram_ff22;
reg [6:0] ram_ff23;
reg [6:0] ram_ff24;
reg [6:0] ram_ff25;
reg [6:0] ram_ff26;
reg [6:0] ram_ff27;
reg [6:0] ram_ff28;
reg [6:0] ram_ff29;
reg [6:0] ram_ff30;
reg [6:0] ram_ff31;
reg [6:0] ram_ff32;
reg [6:0] ram_ff33;
reg [6:0] ram_ff34;
reg [6:0] ram_ff35;
reg [6:0] ram_ff36;
reg [6:0] ram_ff37;
reg [6:0] ram_ff38;
reg [6:0] ram_ff39;
reg [6:0] ram_ff40;
reg [6:0] ram_ff41;
reg [6:0] ram_ff42;
reg [6:0] ram_ff43;
reg [6:0] ram_ff44;
reg [6:0] ram_ff45;
reg [6:0] ram_ff46;
reg [6:0] ram_ff47;
reg [6:0] ram_ff48;
reg [6:0] ram_ff49;
reg [6:0] ram_ff50;
reg [6:0] ram_ff51;
reg [6:0] ram_ff52;
reg [6:0] ram_ff53;
reg [6:0] ram_ff54;
reg [6:0] ram_ff55;
reg [6:0] ram_ff56;
reg [6:0] ram_ff57;
reg [6:0] ram_ff58;
reg [6:0] ram_ff59;
reg [6:0] ram_ff60;
reg [6:0] ram_ff61;
reg [6:0] ram_ff62;
reg [6:0] ram_ff63;
reg [6:0] ram_ff64;
reg [6:0] ram_ff65;
reg [6:0] ram_ff66;
reg [6:0] ram_ff67;
reg [6:0] ram_ff68;
reg [6:0] ram_ff69;
reg [6:0] ram_ff70;
reg [6:0] ram_ff71;
reg [6:0] ram_ff72;
reg [6:0] ram_ff73;
reg [6:0] ram_ff74;
reg [6:0] ram_ff75;
reg [6:0] ram_ff76;
reg [6:0] ram_ff77;
reg [6:0] ram_ff78;
reg [6:0] ram_ff79;
reg [6:0] ram_ff80;
reg [6:0] ram_ff81;
reg [6:0] ram_ff82;
reg [6:0] ram_ff83;
reg [6:0] ram_ff84;
reg [6:0] ram_ff85;
reg [6:0] ram_ff86;
reg [6:0] ram_ff87;
reg [6:0] ram_ff88;
reg [6:0] ram_ff89;
reg [6:0] ram_ff90;
reg [6:0] ram_ff91;
reg [6:0] ram_ff92;
reg [6:0] ram_ff93;
reg [6:0] ram_ff94;
reg [6:0] ram_ff95;
reg [6:0] ram_ff96;
reg [6:0] ram_ff97;
reg [6:0] ram_ff98;
reg [6:0] ram_ff99;
reg [6:0] ram_ff100;
reg [6:0] ram_ff101;
reg [6:0] ram_ff102;
reg [6:0] ram_ff103;
reg [6:0] ram_ff104;
reg [6:0] ram_ff105;
reg [6:0] ram_ff106;
reg [6:0] ram_ff107;
reg [6:0] ram_ff108;
reg [6:0] ram_ff109;
reg [6:0] ram_ff110;
reg [6:0] ram_ff111;
reg [6:0] ram_ff112;
reg [6:0] ram_ff113;
reg [6:0] ram_ff114;
reg [6:0] ram_ff115;
reg [6:0] ram_ff116;
reg [6:0] ram_ff117;
reg [6:0] ram_ff118;
reg [6:0] ram_ff119;
reg [6:0] ram_ff120;
reg [6:0] ram_ff121;
reg [6:0] ram_ff122;
reg [6:0] ram_ff123;
reg [6:0] ram_ff124;
reg [6:0] ram_ff125;
reg [6:0] ram_ff126;
reg [6:0] ram_ff127;
reg [6:0] ram_ff128;
reg [6:0] ram_ff129;
reg [6:0] ram_ff130;
reg [6:0] ram_ff131;
reg [6:0] ram_ff132;
reg [6:0] ram_ff133;
reg [6:0] ram_ff134;
reg [6:0] ram_ff135;
reg [6:0] ram_ff136;
reg [6:0] ram_ff137;
reg [6:0] ram_ff138;
reg [6:0] ram_ff139;
reg [6:0] ram_ff140;
reg [6:0] ram_ff141;
reg [6:0] ram_ff142;
reg [6:0] ram_ff143;
reg [6:0] ram_ff144;
reg [6:0] ram_ff145;
reg [6:0] ram_ff146;
reg [6:0] ram_ff147;
reg [6:0] ram_ff148;
reg [6:0] ram_ff149;
reg [6:0] ram_ff150;
reg [6:0] ram_ff151;
reg [6:0] ram_ff152;
reg [6:0] ram_ff153;
reg [6:0] ram_ff154;
reg [6:0] ram_ff155;
reg [6:0] ram_ff156;
reg [6:0] ram_ff157;
reg [6:0] ram_ff158;
reg [6:0] ram_ff159;
reg [6:0] ram_ff160;
reg [6:0] ram_ff161;
reg [6:0] ram_ff162;
reg [6:0] ram_ff163;
reg [6:0] ram_ff164;
reg [6:0] ram_ff165;
reg [6:0] ram_ff166;
reg [6:0] ram_ff167;
reg [6:0] ram_ff168;
reg [6:0] ram_ff169;
reg [6:0] ram_ff170;
reg [6:0] ram_ff171;
reg [6:0] ram_ff172;
reg [6:0] ram_ff173;
reg [6:0] ram_ff174;
reg [6:0] ram_ff175;
reg [6:0] ram_ff176;
reg [6:0] ram_ff177;
reg [6:0] ram_ff178;
reg [6:0] ram_ff179;
reg [6:0] ram_ff180;
reg [6:0] ram_ff181;
reg [6:0] ram_ff182;
reg [6:0] ram_ff183;
reg [6:0] ram_ff184;
reg [6:0] ram_ff185;
reg [6:0] ram_ff186;
reg [6:0] ram_ff187;
reg [6:0] ram_ff188;
reg [6:0] ram_ff189;
reg [6:0] ram_ff190;
reg [6:0] ram_ff191;
reg [6:0] ram_ff192;
reg [6:0] ram_ff193;
reg [6:0] ram_ff194;
reg [6:0] ram_ff195;
reg [6:0] ram_ff196;
reg [6:0] ram_ff197;
reg [6:0] ram_ff198;
reg [6:0] ram_ff199;
reg [6:0] ram_ff200;
reg [6:0] ram_ff201;
reg [6:0] ram_ff202;
reg [6:0] ram_ff203;
reg [6:0] ram_ff204;
reg [6:0] ram_ff205;
reg [6:0] ram_ff206;
reg [6:0] ram_ff207;
reg [6:0] ram_ff208;
reg [6:0] ram_ff209;
reg [6:0] ram_ff210;
reg [6:0] ram_ff211;
reg [6:0] ram_ff212;
reg [6:0] ram_ff213;
reg [6:0] ram_ff214;
reg [6:0] ram_ff215;
reg [6:0] ram_ff216;
reg [6:0] ram_ff217;
reg [6:0] ram_ff218;
reg [6:0] ram_ff219;
reg [6:0] ram_ff220;
reg [6:0] ram_ff221;
reg [6:0] ram_ff222;
reg [6:0] ram_ff223;
reg [6:0] ram_ff224;
reg [6:0] ram_ff225;
reg [6:0] ram_ff226;
reg [6:0] ram_ff227;
reg [6:0] ram_ff228;
reg [6:0] ram_ff229;
reg [6:0] ram_ff230;
reg [6:0] ram_ff231;
reg [6:0] ram_ff232;
reg [6:0] ram_ff233;
reg [6:0] ram_ff234;
reg [6:0] ram_ff235;
reg [6:0] ram_ff236;
reg [6:0] ram_ff237;
reg [6:0] ram_ff238;
reg [6:0] ram_ff239;
reg [6:0] ram_ff240;
reg [6:0] ram_ff241;
reg [6:0] ram_ff242;
reg [6:0] ram_ff243;
reg [6:0] ram_ff244;
reg [6:0] ram_ff245;
reg [6:0] ram_ff246;
reg [6:0] ram_ff247;
reg [6:0] ram_ff248;
reg [6:0] ram_ff249;
reg [6:0] ram_ff250;
reg [6:0] ram_ff251;
reg [6:0] ram_ff252;
reg [6:0] ram_ff253;
reg [6:0] ram_ff254;
reg [6:0] ram_ff255;
always @( posedge clk ) begin
if ( we && wa == 8'd0 ) begin
ram_ff0 <= di;
end
if ( we && wa == 8'd1 ) begin
ram_ff1 <= di;
end
if ( we && wa == 8'd2 ) begin
ram_ff2 <= di;
end
if ( we && wa == 8'd3 ) begin
ram_ff3 <= di;
end
if ( we && wa == 8'd4 ) begin
ram_ff4 <= di;
end
if ( we && wa == 8'd5 ) begin
ram_ff5 <= di;
end
if ( we && wa == 8'd6 ) begin
ram_ff6 <= di;
end
if ( we && wa == 8'd7 ) begin
ram_ff7 <= di;
end
if ( we && wa == 8'd8 ) begin
ram_ff8 <= di;
end
if ( we && wa == 8'd9 ) begin
ram_ff9 <= di;
end
if ( we && wa == 8'd10 ) begin
ram_ff10 <= di;
end
if ( we && wa == 8'd11 ) begin
ram_ff11 <= di;
end
if ( we && wa == 8'd12 ) begin
ram_ff12 <= di;
end
if ( we && wa == 8'd13 ) begin
ram_ff13 <= di;
end
if ( we && wa == 8'd14 ) begin
ram_ff14 <= di;
end
if ( we && wa == 8'd15 ) begin
ram_ff15 <= di;
end
if ( we && wa == 8'd16 ) begin
ram_ff16 <= di;
end
if ( we && wa == 8'd17 ) begin
ram_ff17 <= di;
end
if ( we && wa == 8'd18 ) begin
ram_ff18 <= di;
end
if ( we && wa == 8'd19 ) begin
ram_ff19 <= di;
end
if ( we && wa == 8'd20 ) begin
ram_ff20 <= di;
end
if ( we && wa == 8'd21 ) begin
ram_ff21 <= di;
end
if ( we && wa == 8'd22 ) begin
ram_ff22 <= di;
end
if ( we && wa == 8'd23 ) begin
ram_ff23 <= di;
end
if ( we && wa == 8'd24 ) begin
ram_ff24 <= di;
end
if ( we && wa == 8'd25 ) begin
ram_ff25 <= di;
end
if ( we && wa == 8'd26 ) begin
ram_ff26 <= di;
end
if ( we && wa == 8'd27 ) begin
ram_ff27 <= di;
end
if ( we && wa == 8'd28 ) begin
ram_ff28 <= di;
end
if ( we && wa == 8'd29 ) begin
ram_ff29 <= di;
end
if ( we && wa == 8'd30 ) begin
ram_ff30 <= di;
end
if ( we && wa == 8'd31 ) begin
ram_ff31 <= di;
end
if ( we && wa == 8'd32 ) begin
ram_ff32 <= di;
end
if ( we && wa == 8'd33 ) begin
ram_ff33 <= di;
end
if ( we && wa == 8'd34 ) begin
ram_ff34 <= di;
end
if ( we && wa == 8'd35 ) begin
ram_ff35 <= di;
end
if ( we && wa == 8'd36 ) begin
ram_ff36 <= di;
end
if ( we && wa == 8'd37 ) begin
ram_ff37 <= di;
end
if ( we && wa == 8'd38 ) begin
ram_ff38 <= di;
end
if ( we && wa == 8'd39 ) begin
ram_ff39 <= di;
end
if ( we && wa == 8'd40 ) begin
ram_ff40 <= di;
end
if ( we && wa == 8'd41 ) begin
ram_ff41 <= di;
end
if ( we && wa == 8'd42 ) begin
ram_ff42 <= di;
end
if ( we && wa == 8'd43 ) begin
ram_ff43 <= di;
end
if ( we && wa == 8'd44 ) begin
ram_ff44 <= di;
end
if ( we && wa == 8'd45 ) begin
ram_ff45 <= di;
end
if ( we && wa == 8'd46 ) begin
ram_ff46 <= di;
end
if ( we && wa == 8'd47 ) begin
ram_ff47 <= di;
end
if ( we && wa == 8'd48 ) begin
ram_ff48 <= di;
end
if ( we && wa == 8'd49 ) begin
ram_ff49 <= di;
end
if ( we && wa == 8'd50 ) begin
ram_ff50 <= di;
end
if ( we && wa == 8'd51 ) begin
ram_ff51 <= di;
end
if ( we && wa == 8'd52 ) begin
ram_ff52 <= di;
end
if ( we && wa == 8'd53 ) begin
ram_ff53 <= di;
end
if ( we && wa == 8'd54 ) begin
ram_ff54 <= di;
end
if ( we && wa == 8'd55 ) begin
ram_ff55 <= di;
end
if ( we && wa == 8'd56 ) begin
ram_ff56 <= di;
end
if ( we && wa == 8'd57 ) begin
ram_ff57 <= di;
end
if ( we && wa == 8'd58 ) begin
ram_ff58 <= di;
end
if ( we && wa == 8'd59 ) begin
ram_ff59 <= di;
end
if ( we && wa == 8'd60 ) begin
ram_ff60 <= di;
end
if ( we && wa == 8'd61 ) begin
ram_ff61 <= di;
end
if ( we && wa == 8'd62 ) begin
ram_ff62 <= di;
end
if ( we && wa == 8'd63 ) begin
ram_ff63 <= di;
end
if ( we && wa == 8'd64 ) begin
ram_ff64 <= di;
end
if ( we && wa == 8'd65 ) begin
ram_ff65 <= di;
end
if ( we && wa == 8'd66 ) begin
ram_ff66 <= di;
end
if ( we && wa == 8'd67 ) begin
ram_ff67 <= di;
end
if ( we && wa == 8'd68 ) begin
ram_ff68 <= di;
end
if ( we && wa == 8'd69 ) begin
ram_ff69 <= di;
end
if ( we && wa == 8'd70 ) begin
ram_ff70 <= di;
end
if ( we && wa == 8'd71 ) begin
ram_ff71 <= di;
end
if ( we && wa == 8'd72 ) begin
ram_ff72 <= di;
end
if ( we && wa == 8'd73 ) begin
ram_ff73 <= di;
end
if ( we && wa == 8'd74 ) begin
ram_ff74 <= di;
end
if ( we && wa == 8'd75 ) begin
ram_ff75 <= di;
end
if ( we && wa == 8'd76 ) begin
ram_ff76 <= di;
end
if ( we && wa == 8'd77 ) begin
ram_ff77 <= di;
end
if ( we && wa == 8'd78 ) begin
ram_ff78 <= di;
end
if ( we && wa == 8'd79 ) begin
ram_ff79 <= di;
end
if ( we && wa == 8'd80 ) begin
ram_ff80 <= di;
end
if ( we && wa == 8'd81 ) begin
ram_ff81 <= di;
end
if ( we && wa == 8'd82 ) begin
ram_ff82 <= di;
end
if ( we && wa == 8'd83 ) begin
ram_ff83 <= di;
end
if ( we && wa == 8'd84 ) begin
ram_ff84 <= di;
end
if ( we && wa == 8'd85 ) begin
ram_ff85 <= di;
end
if ( we && wa == 8'd86 ) begin
ram_ff86 <= di;
end
if ( we && wa == 8'd87 ) begin
ram_ff87 <= di;
end
if ( we && wa == 8'd88 ) begin
ram_ff88 <= di;
end
if ( we && wa == 8'd89 ) begin
ram_ff89 <= di;
end
if ( we && wa == 8'd90 ) begin
ram_ff90 <= di;
end
if ( we && wa == 8'd91 ) begin
ram_ff91 <= di;
end
if ( we && wa == 8'd92 ) begin
ram_ff92 <= di;
end
if ( we && wa == 8'd93 ) begin
ram_ff93 <= di;
end
if ( we && wa == 8'd94 ) begin
ram_ff94 <= di;
end
if ( we && wa == 8'd95 ) begin
ram_ff95 <= di;
end
if ( we && wa == 8'd96 ) begin
ram_ff96 <= di;
end
if ( we && wa == 8'd97 ) begin
ram_ff97 <= di;
end
if ( we && wa == 8'd98 ) begin
ram_ff98 <= di;
end
if ( we && wa == 8'd99 ) begin
ram_ff99 <= di;
end
if ( we && wa == 8'd100 ) begin
ram_ff100 <= di;
end
if ( we && wa == 8'd101 ) begin
ram_ff101 <= di;
end
if ( we && wa == 8'd102 ) begin
ram_ff102 <= di;
end
if ( we && wa == 8'd103 ) begin
ram_ff103 <= di;
end
if ( we && wa == 8'd104 ) begin
ram_ff104 <= di;
end
if ( we && wa == 8'd105 ) begin
ram_ff105 <= di;
end
if ( we && wa == 8'd106 ) begin
ram_ff106 <= di;
end
if ( we && wa == 8'd107 ) begin
ram_ff107 <= di;
end
if ( we && wa == 8'd108 ) begin
ram_ff108 <= di;
end
if ( we && wa == 8'd109 ) begin
ram_ff109 <= di;
end
if ( we && wa == 8'd110 ) begin
ram_ff110 <= di;
end
if ( we && wa == 8'd111 ) begin
ram_ff111 <= di;
end
if ( we && wa == 8'd112 ) begin
ram_ff112 <= di;
end
if ( we && wa == 8'd113 ) begin
ram_ff113 <= di;
end
if ( we && wa == 8'd114 ) begin
ram_ff114 <= di;
end
if ( we && wa == 8'd115 ) begin
ram_ff115 <= di;
end
if ( we && wa == 8'd116 ) begin
ram_ff116 <= di;
end
if ( we && wa == 8'd117 ) begin
ram_ff117 <= di;
end
if ( we && wa == 8'd118 ) begin
ram_ff118 <= di;
end
if ( we && wa == 8'd119 ) begin
ram_ff119 <= di;
end
if ( we && wa == 8'd120 ) begin
ram_ff120 <= di;
end
if ( we && wa == 8'd121 ) begin
ram_ff121 <= di;
end
if ( we && wa == 8'd122 ) begin
ram_ff122 <= di;
end
if ( we && wa == 8'd123 ) begin
ram_ff123 <= di;
end
if ( we && wa == 8'd124 ) begin
ram_ff124 <= di;
end
if ( we && wa == 8'd125 ) begin
ram_ff125 <= di;
end
if ( we && wa == 8'd126 ) begin
ram_ff126 <= di;
end
if ( we && wa == 8'd127 ) begin
ram_ff127 <= di;
end
if ( we && wa == 8'd128 ) begin
ram_ff128 <= di;
end
if ( we && wa == 8'd129 ) begin
ram_ff129 <= di;
end
if ( we && wa == 8'd130 ) begin
ram_ff130 <= di;
end
if ( we && wa == 8'd131 ) begin
ram_ff131 <= di;
end
if ( we && wa == 8'd132 ) begin
ram_ff132 <= di;
end
if ( we && wa == 8'd133 ) begin
ram_ff133 <= di;
end
if ( we && wa == 8'd134 ) begin
ram_ff134 <= di;
end
if ( we && wa == 8'd135 ) begin
ram_ff135 <= di;
end
if ( we && wa == 8'd136 ) begin
ram_ff136 <= di;
end
if ( we && wa == 8'd137 ) begin
ram_ff137 <= di;
end
if ( we && wa == 8'd138 ) begin
ram_ff138 <= di;
end
if ( we && wa == 8'd139 ) begin
ram_ff139 <= di;
end
if ( we && wa == 8'd140 ) begin
ram_ff140 <= di;
end
if ( we && wa == 8'd141 ) begin
ram_ff141 <= di;
end
if ( we && wa == 8'd142 ) begin
ram_ff142 <= di;
end
if ( we && wa == 8'd143 ) begin
ram_ff143 <= di;
end
if ( we && wa == 8'd144 ) begin
ram_ff144 <= di;
end
if ( we && wa == 8'd145 ) begin
ram_ff145 <= di;
end
if ( we && wa == 8'd146 ) begin
ram_ff146 <= di;
end
if ( we && wa == 8'd147 ) begin
ram_ff147 <= di;
end
if ( we && wa == 8'd148 ) begin
ram_ff148 <= di;
end
if ( we && wa == 8'd149 ) begin
ram_ff149 <= di;
end
if ( we && wa == 8'd150 ) begin
ram_ff150 <= di;
end
if ( we && wa == 8'd151 ) begin
ram_ff151 <= di;
end
if ( we && wa == 8'd152 ) begin
ram_ff152 <= di;
end
if ( we && wa == 8'd153 ) begin
ram_ff153 <= di;
end
if ( we && wa == 8'd154 ) begin
ram_ff154 <= di;
end
if ( we && wa == 8'd155 ) begin
ram_ff155 <= di;
end
if ( we && wa == 8'd156 ) begin
ram_ff156 <= di;
end
if ( we && wa == 8'd157 ) begin
ram_ff157 <= di;
end
if ( we && wa == 8'd158 ) begin
ram_ff158 <= di;
end
if ( we && wa == 8'd159 ) begin
ram_ff159 <= di;
end
if ( we && wa == 8'd160 ) begin
ram_ff160 <= di;
end
if ( we && wa == 8'd161 ) begin
ram_ff161 <= di;
end
if ( we && wa == 8'd162 ) begin
ram_ff162 <= di;
end
if ( we && wa == 8'd163 ) begin
ram_ff163 <= di;
end
if ( we && wa == 8'd164 ) begin
ram_ff164 <= di;
end
if ( we && wa == 8'd165 ) begin
ram_ff165 <= di;
end
if ( we && wa == 8'd166 ) begin
ram_ff166 <= di;
end
if ( we && wa == 8'd167 ) begin
ram_ff167 <= di;
end
if ( we && wa == 8'd168 ) begin
ram_ff168 <= di;
end
if ( we && wa == 8'd169 ) begin
ram_ff169 <= di;
end
if ( we && wa == 8'd170 ) begin
ram_ff170 <= di;
end
if ( we && wa == 8'd171 ) begin
ram_ff171 <= di;
end
if ( we && wa == 8'd172 ) begin
ram_ff172 <= di;
end
if ( we && wa == 8'd173 ) begin
ram_ff173 <= di;
end
if ( we && wa == 8'd174 ) begin
ram_ff174 <= di;
end
if ( we && wa == 8'd175 ) begin
ram_ff175 <= di;
end
if ( we && wa == 8'd176 ) begin
ram_ff176 <= di;
end
if ( we && wa == 8'd177 ) begin
ram_ff177 <= di;
end
if ( we && wa == 8'd178 ) begin
ram_ff178 <= di;
end
if ( we && wa == 8'd179 ) begin
ram_ff179 <= di;
end
if ( we && wa == 8'd180 ) begin
ram_ff180 <= di;
end
if ( we && wa == 8'd181 ) begin
ram_ff181 <= di;
end
if ( we && wa == 8'd182 ) begin
ram_ff182 <= di;
end
if ( we && wa == 8'd183 ) begin
ram_ff183 <= di;
end
if ( we && wa == 8'd184 ) begin
ram_ff184 <= di;
end
if ( we && wa == 8'd185 ) begin
ram_ff185 <= di;
end
if ( we && wa == 8'd186 ) begin
ram_ff186 <= di;
end
if ( we && wa == 8'd187 ) begin
ram_ff187 <= di;
end
if ( we && wa == 8'd188 ) begin
ram_ff188 <= di;
end
if ( we && wa == 8'd189 ) begin
ram_ff189 <= di;
end
if ( we && wa == 8'd190 ) begin
ram_ff190 <= di;
end
if ( we && wa == 8'd191 ) begin
ram_ff191 <= di;
end
if ( we && wa == 8'd192 ) begin
ram_ff192 <= di;
end
if ( we && wa == 8'd193 ) begin
ram_ff193 <= di;
end
if ( we && wa == 8'd194 ) begin
ram_ff194 <= di;
end
if ( we && wa == 8'd195 ) begin
ram_ff195 <= di;
end
if ( we && wa == 8'd196 ) begin
ram_ff196 <= di;
end
if ( we && wa == 8'd197 ) begin
ram_ff197 <= di;
end
if ( we && wa == 8'd198 ) begin
ram_ff198 <= di;
end
if ( we && wa == 8'd199 ) begin
ram_ff199 <= di;
end
if ( we && wa == 8'd200 ) begin
ram_ff200 <= di;
end
if ( we && wa == 8'd201 ) begin
ram_ff201 <= di;
end
if ( we && wa == 8'd202 ) begin
ram_ff202 <= di;
end
if ( we && wa == 8'd203 ) begin
ram_ff203 <= di;
end
if ( we && wa == 8'd204 ) begin
ram_ff204 <= di;
end
if ( we && wa == 8'd205 ) begin
ram_ff205 <= di;
end
if ( we && wa == 8'd206 ) begin
ram_ff206 <= di;
end
if ( we && wa == 8'd207 ) begin
ram_ff207 <= di;
end
if ( we && wa == 8'd208 ) begin
ram_ff208 <= di;
end
if ( we && wa == 8'd209 ) begin
ram_ff209 <= di;
end
if ( we && wa == 8'd210 ) begin
ram_ff210 <= di;
end
if ( we && wa == 8'd211 ) begin
ram_ff211 <= di;
end
if ( we && wa == 8'd212 ) begin
ram_ff212 <= di;
end
if ( we && wa == 8'd213 ) begin
ram_ff213 <= di;
end
if ( we && wa == 8'd214 ) begin
ram_ff214 <= di;
end
if ( we && wa == 8'd215 ) begin
ram_ff215 <= di;
end
if ( we && wa == 8'd216 ) begin
ram_ff216 <= di;
end
if ( we && wa == 8'd217 ) begin
ram_ff217 <= di;
end
if ( we && wa == 8'd218 ) begin
ram_ff218 <= di;
end
if ( we && wa == 8'd219 ) begin
ram_ff219 <= di;
end
if ( we && wa == 8'd220 ) begin
ram_ff220 <= di;
end
if ( we && wa == 8'd221 ) begin
ram_ff221 <= di;
end
if ( we && wa == 8'd222 ) begin
ram_ff222 <= di;
end
if ( we && wa == 8'd223 ) begin
ram_ff223 <= di;
end
if ( we && wa == 8'd224 ) begin
ram_ff224 <= di;
end
if ( we && wa == 8'd225 ) begin
ram_ff225 <= di;
end
if ( we && wa == 8'd226 ) begin
ram_ff226 <= di;
end
if ( we && wa == 8'd227 ) begin
ram_ff227 <= di;
end
if ( we && wa == 8'd228 ) begin
ram_ff228 <= di;
end
if ( we && wa == 8'd229 ) begin
ram_ff229 <= di;
end
if ( we && wa == 8'd230 ) begin
ram_ff230 <= di;
end
if ( we && wa == 8'd231 ) begin
ram_ff231 <= di;
end
if ( we && wa == 8'd232 ) begin
ram_ff232 <= di;
end
if ( we && wa == 8'd233 ) begin
ram_ff233 <= di;
end
if ( we && wa == 8'd234 ) begin
ram_ff234 <= di;
end
if ( we && wa == 8'd235 ) begin
ram_ff235 <= di;
end
if ( we && wa == 8'd236 ) begin
ram_ff236 <= di;
end
if ( we && wa == 8'd237 ) begin
ram_ff237 <= di;
end
if ( we && wa == 8'd238 ) begin
ram_ff238 <= di;
end
if ( we && wa == 8'd239 ) begin
ram_ff239 <= di;
end
if ( we && wa == 8'd240 ) begin
ram_ff240 <= di;
end
if ( we && wa == 8'd241 ) begin
ram_ff241 <= di;
end
if ( we && wa == 8'd242 ) begin
ram_ff242 <= di;
end
if ( we && wa == 8'd243 ) begin
ram_ff243 <= di;
end
if ( we && wa == 8'd244 ) begin
ram_ff244 <= di;
end
if ( we && wa == 8'd245 ) begin
ram_ff245 <= di;
end
if ( we && wa == 8'd246 ) begin
ram_ff246 <= di;
end
if ( we && wa == 8'd247 ) begin
ram_ff247 <= di;
end
if ( we && wa == 8'd248 ) begin
ram_ff248 <= di;
end
if ( we && wa == 8'd249 ) begin
ram_ff249 <= di;
end
if ( we && wa == 8'd250 ) begin
ram_ff250 <= di;
end
if ( we && wa == 8'd251 ) begin
ram_ff251 <= di;
end
if ( we && wa == 8'd252 ) begin
ram_ff252 <= di;
end
if ( we && wa == 8'd253 ) begin
ram_ff253 <= di;
end
if ( we && wa == 8'd254 ) begin
ram_ff254 <= di;
end
if ( we && wa == 8'd255 ) begin
ram_ff255 <= di;
end
end
reg [6:0] dout;
always @(*) begin
case( ra )
8'd0: dout = ram_ff0;
8'd1: dout = ram_ff1;
8'd2: dout = ram_ff2;
8'd3: dout = ram_ff3;
8'd4: dout = ram_ff4;
8'd5: dout = ram_ff5;
8'd6: dout = ram_ff6;
8'd7: dout = ram_ff7;
8'd8: dout = ram_ff8;
8'd9: dout = ram_ff9;
8'd10: dout = ram_ff10;
8'd11: dout = ram_ff11;
8'd12: dout = ram_ff12;
8'd13: dout = ram_ff13;
8'd14: dout = ram_ff14;
8'd15: dout = ram_ff15;
8'd16: dout = ram_ff16;
8'd17: dout = ram_ff17;
8'd18: dout = ram_ff18;
8'd19: dout = ram_ff19;
8'd20: dout = ram_ff20;
8'd21: dout = ram_ff21;
8'd22: dout = ram_ff22;
8'd23: dout = ram_ff23;
8'd24: dout = ram_ff24;
8'd25: dout = ram_ff25;
8'd26: dout = ram_ff26;
8'd27: dout = ram_ff27;
8'd28: dout = ram_ff28;
8'd29: dout = ram_ff29;
8'd30: dout = ram_ff30;
8'd31: dout = ram_ff31;
8'd32: dout = ram_ff32;
8'd33: dout = ram_ff33;
8'd34: dout = ram_ff34;
8'd35: dout = ram_ff35;
8'd36: dout = ram_ff36;
8'd37: dout = ram_ff37;
8'd38: dout = ram_ff38;
8'd39: dout = ram_ff39;
8'd40: dout = ram_ff40;
8'd41: dout = ram_ff41;
8'd42: dout = ram_ff42;
8'd43: dout = ram_ff43;
8'd44: dout = ram_ff44;
8'd45: dout = ram_ff45;
8'd46: dout = ram_ff46;
8'd47: dout = ram_ff47;
8'd48: dout = ram_ff48;
8'd49: dout = ram_ff49;
8'd50: dout = ram_ff50;
8'd51: dout = ram_ff51;
8'd52: dout = ram_ff52;
8'd53: dout = ram_ff53;
8'd54: dout = ram_ff54;
8'd55: dout = ram_ff55;
8'd56: dout = ram_ff56;
8'd57: dout = ram_ff57;
8'd58: dout = ram_ff58;
8'd59: dout = ram_ff59;
8'd60: dout = ram_ff60;
8'd61: dout = ram_ff61;
8'd62: dout = ram_ff62;
8'd63: dout = ram_ff63;
8'd64: dout = ram_ff64;
8'd65: dout = ram_ff65;
8'd66: dout = ram_ff66;
8'd67: dout = ram_ff67;
8'd68: dout = ram_ff68;
8'd69: dout = ram_ff69;
8'd70: dout = ram_ff70;
8'd71: dout = ram_ff71;
8'd72: dout = ram_ff72;
8'd73: dout = ram_ff73;
8'd74: dout = ram_ff74;
8'd75: dout = ram_ff75;
8'd76: dout = ram_ff76;
8'd77: dout = ram_ff77;
8'd78: dout = ram_ff78;
8'd79: dout = ram_ff79;
8'd80: dout = ram_ff80;
8'd81: dout = ram_ff81;
8'd82: dout = ram_ff82;
8'd83: dout = ram_ff83;
8'd84: dout = ram_ff84;
8'd85: dout = ram_ff85;
8'd86: dout = ram_ff86;
8'd87: dout = ram_ff87;
8'd88: dout = ram_ff88;
8'd89: dout = ram_ff89;
8'd90: dout = ram_ff90;
8'd91: dout = ram_ff91;
8'd92: dout = ram_ff92;
8'd93: dout = ram_ff93;
8'd94: dout = ram_ff94;
8'd95: dout = ram_ff95;
8'd96: dout = ram_ff96;
8'd97: dout = ram_ff97;
8'd98: dout = ram_ff98;
8'd99: dout = ram_ff99;
8'd100: dout = ram_ff100;
8'd101: dout = ram_ff101;
8'd102: dout = ram_ff102;
8'd103: dout = ram_ff103;
8'd104: dout = ram_ff104;
8'd105: dout = ram_ff105;
8'd106: dout = ram_ff106;
8'd107: dout = ram_ff107;
8'd108: dout = ram_ff108;
8'd109: dout = ram_ff109;
8'd110: dout = ram_ff110;
8'd111: dout = ram_ff111;
8'd112: dout = ram_ff112;
8'd113: dout = ram_ff113;
8'd114: dout = ram_ff114;
8'd115: dout = ram_ff115;
8'd116: dout = ram_ff116;
8'd117: dout = ram_ff117;
8'd118: dout = ram_ff118;
8'd119: dout = ram_ff119;
8'd120: dout = ram_ff120;
8'd121: dout = ram_ff121;
8'd122: dout = ram_ff122;
8'd123: dout = ram_ff123;
8'd124: dout = ram_ff124;
8'd125: dout = ram_ff125;
8'd126: dout = ram_ff126;
8'd127: dout = ram_ff127;
8'd128: dout = ram_ff128;
8'd129: dout = ram_ff129;
8'd130: dout = ram_ff130;
8'd131: dout = ram_ff131;
8'd132: dout = ram_ff132;
8'd133: dout = ram_ff133;
8'd134: dout = ram_ff134;
8'd135: dout = ram_ff135;
8'd136: dout = ram_ff136;
8'd137: dout = ram_ff137;
8'd138: dout = ram_ff138;
8'd139: dout = ram_ff139;
8'd140: dout = ram_ff140;
8'd141: dout = ram_ff141;
8'd142: dout = ram_ff142;
8'd143: dout = ram_ff143;
8'd144: dout = ram_ff144;
8'd145: dout = ram_ff145;
8'd146: dout = ram_ff146;
8'd147: dout = ram_ff147;
8'd148: dout = ram_ff148;
8'd149: dout = ram_ff149;
8'd150: dout = ram_ff150;
8'd151: dout = ram_ff151;
8'd152: dout = ram_ff152;
8'd153: dout = ram_ff153;
8'd154: dout = ram_ff154;
8'd155: dout = ram_ff155;
8'd156: dout = ram_ff156;
8'd157: dout = ram_ff157;
8'd158: dout = ram_ff158;
8'd159: dout = ram_ff159;
8'd160: dout = ram_ff160;
8'd161: dout = ram_ff161;
8'd162: dout = ram_ff162;
8'd163: dout = ram_ff163;
8'd164: dout = ram_ff164;
8'd165: dout = ram_ff165;
8'd166: dout = ram_ff166;
8'd167: dout = ram_ff167;
8'd168: dout = ram_ff168;
8'd169: dout = ram_ff169;
8'd170: dout = ram_ff170;
8'd171: dout = ram_ff171;
8'd172: dout = ram_ff172;
8'd173: dout = ram_ff173;
8'd174: dout = ram_ff174;
8'd175: dout = ram_ff175;
8'd176: dout = ram_ff176;
8'd177: dout = ram_ff177;
8'd178: dout = ram_ff178;
8'd179: dout = ram_ff179;
8'd180: dout = ram_ff180;
8'd181: dout = ram_ff181;
8'd182: dout = ram_ff182;
8'd183: dout = ram_ff183;
8'd184: dout = ram_ff184;
8'd185: dout = ram_ff185;
8'd186: dout = ram_ff186;
8'd187: dout = ram_ff187;
8'd188: dout = ram_ff188;
8'd189: dout = ram_ff189;
8'd190: dout = ram_ff190;
8'd191: dout = ram_ff191;
8'd192: dout = ram_ff192;
8'd193: dout = ram_ff193;
8'd194: dout = ram_ff194;
8'd195: dout = ram_ff195;
8'd196: dout = ram_ff196;
8'd197: dout = ram_ff197;
8'd198: dout = ram_ff198;
8'd199: dout = ram_ff199;
8'd200: dout = ram_ff200;
8'd201: dout = ram_ff201;
8'd202: dout = ram_ff202;
8'd203: dout = ram_ff203;
8'd204: dout = ram_ff204;
8'd205: dout = ram_ff205;
8'd206: dout = ram_ff206;
8'd207: dout = ram_ff207;
8'd208: dout = ram_ff208;
8'd209: dout = ram_ff209;
8'd210: dout = ram_ff210;
8'd211: dout = ram_ff211;
8'd212: dout = ram_ff212;
8'd213: dout = ram_ff213;
8'd214: dout = ram_ff214;
8'd215: dout = ram_ff215;
8'd216: dout = ram_ff216;
8'd217: dout = ram_ff217;
8'd218: dout = ram_ff218;
8'd219: dout = ram_ff219;
8'd220: dout = ram_ff220;
8'd221: dout = ram_ff221;
8'd222: dout = ram_ff222;
8'd223: dout = ram_ff223;
8'd224: dout = ram_ff224;
8'd225: dout = ram_ff225;
8'd226: dout = ram_ff226;
8'd227: dout = ram_ff227;
8'd228: dout = ram_ff228;
8'd229: dout = ram_ff229;
8'd230: dout = ram_ff230;
8'd231: dout = ram_ff231;
8'd232: dout = ram_ff232;
8'd233: dout = ram_ff233;
8'd234: dout = ram_ff234;
8'd235: dout = ram_ff235;
8'd236: dout = ram_ff236;
8'd237: dout = ram_ff237;
8'd238: dout = ram_ff238;
8'd239: dout = ram_ff239;
8'd240: dout = ram_ff240;
8'd241: dout = ram_ff241;
8'd242: dout = ram_ff242;
8'd243: dout = ram_ff243;
8'd244: dout = ram_ff244;
8'd245: dout = ram_ff245;
8'd246: dout = ram_ff246;
8'd247: dout = ram_ff247;
8'd248: dout = ram_ff248;
8'd249: dout = ram_ff249;
8'd250: dout = ram_ff250;
8'd251: dout = ram_ff251;
8'd252: dout = ram_ff252;
8'd253: dout = ram_ff253;
8'd254: dout = ram_ff254;
8'd255: dout = ram_ff255;
//VCS coverage off
default: dout = {7{`x_or_0}};
//VCS coverage on
endcase
end
`endif // EMU
endmodule // NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7
// emulation model of flopram guts
//
`ifdef EMU
module vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7 (
Wa0, we0, Di0,
Ra0, Do0
);
input [7:0] Wa0;
input we0;
input [6:0] Di0;
input [7:0] Ra0;
output [6:0] Do0;
// Only visible during Spyglass to avoid blackboxes.
`ifdef SPYGLASS_FLOPRAM
assign Do0 = 7'd0;
wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0);
`endif
// synopsys translate_off
`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg [6:0] mem[255:0];
// expand mem for debug ease
`ifdef EMU_EXPAND_FLOPRAM_MEM
wire [6:0] Q0 = mem[0];
wire [6:0] Q1 = mem[1];
wire [6:0] Q2 = mem[2];
wire [6:0] Q3 = mem[3];
wire [6:0] Q4 = mem[4];
wire [6:0] Q5 = mem[5];
wire [6:0] Q6 = mem[6];
wire [6:0] Q7 = mem[7];
wire [6:0] Q8 = mem[8];
wire [6:0] Q9 = mem[9];
wire [6:0] Q10 = mem[10];
wire [6:0] Q11 = mem[11];
wire [6:0] Q12 = mem[12];
wire [6:0] Q13 = mem[13];
wire [6:0] Q14 = mem[14];
wire [6:0] Q15 = mem[15];
wire [6:0] Q16 = mem[16];
wire [6:0] Q17 = mem[17];
wire [6:0] Q18 = mem[18];
wire [6:0] Q19 = mem[19];
wire [6:0] Q20 = mem[20];
wire [6:0] Q21 = mem[21];
wire [6:0] Q22 = mem[22];
wire [6:0] Q23 = mem[23];
wire [6:0] Q24 = mem[24];
wire [6:0] Q25 = mem[25];
wire [6:0] Q26 = mem[26];
wire [6:0] Q27 = mem[27];
wire [6:0] Q28 = mem[28];
wire [6:0] Q29 = mem[29];
wire [6:0] Q30 = mem[30];
wire [6:0] Q31 = mem[31];
wire [6:0] Q32 = mem[32];
wire [6:0] Q33 = mem[33];
wire [6:0] Q34 = mem[34];
wire [6:0] Q35 = mem[35];
wire [6:0] Q36 = mem[36];
wire [6:0] Q37 = mem[37];
wire [6:0] Q38 = mem[38];
wire [6:0] Q39 = mem[39];
wire [6:0] Q40 = mem[40];
wire [6:0] Q41 = mem[41];
wire [6:0] Q42 = mem[42];
wire [6:0] Q43 = mem[43];
wire [6:0] Q44 = mem[44];
wire [6:0] Q45 = mem[45];
wire [6:0] Q46 = mem[46];
wire [6:0] Q47 = mem[47];
wire [6:0] Q48 = mem[48];
wire [6:0] Q49 = mem[49];
wire [6:0] Q50 = mem[50];
wire [6:0] Q51 = mem[51];
wire [6:0] Q52 = mem[52];
wire [6:0] Q53 = mem[53];
wire [6:0] Q54 = mem[54];
wire [6:0] Q55 = mem[55];
wire [6:0] Q56 = mem[56];
wire [6:0] Q57 = mem[57];
wire [6:0] Q58 = mem[58];
wire [6:0] Q59 = mem[59];
wire [6:0] Q60 = mem[60];
wire [6:0] Q61 = mem[61];
wire [6:0] Q62 = mem[62];
wire [6:0] Q63 = mem[63];
wire [6:0] Q64 = mem[64];
wire [6:0] Q65 = mem[65];
wire [6:0] Q66 = mem[66];
wire [6:0] Q67 = mem[67];
wire [6:0] Q68 = mem[68];
wire [6:0] Q69 = mem[69];
wire [6:0] Q70 = mem[70];
wire [6:0] Q71 = mem[71];
wire [6:0] Q72 = mem[72];
wire [6:0] Q73 = mem[73];
wire [6:0] Q74 = mem[74];
wire [6:0] Q75 = mem[75];
wire [6:0] Q76 = mem[76];
wire [6:0] Q77 = mem[77];
wire [6:0] Q78 = mem[78];
wire [6:0] Q79 = mem[79];
wire [6:0] Q80 = mem[80];
wire [6:0] Q81 = mem[81];
wire [6:0] Q82 = mem[82];
wire [6:0] Q83 = mem[83];
wire [6:0] Q84 = mem[84];
wire [6:0] Q85 = mem[85];
wire [6:0] Q86 = mem[86];
wire [6:0] Q87 = mem[87];
wire [6:0] Q88 = mem[88];
wire [6:0] Q89 = mem[89];
wire [6:0] Q90 = mem[90];
wire [6:0] Q91 = mem[91];
wire [6:0] Q92 = mem[92];
wire [6:0] Q93 = mem[93];
wire [6:0] Q94 = mem[94];
wire [6:0] Q95 = mem[95];
wire [6:0] Q96 = mem[96];
wire [6:0] Q97 = mem[97];
wire [6:0] Q98 = mem[98];
wire [6:0] Q99 = mem[99];
wire [6:0] Q100 = mem[100];
wire [6:0] Q101 = mem[101];
wire [6:0] Q102 = mem[102];
wire [6:0] Q103 = mem[103];
wire [6:0] Q104 = mem[104];
wire [6:0] Q105 = mem[105];
wire [6:0] Q106 = mem[106];
wire [6:0] Q107 = mem[107];
wire [6:0] Q108 = mem[108];
wire [6:0] Q109 = mem[109];
wire [6:0] Q110 = mem[110];
wire [6:0] Q111 = mem[111];
wire [6:0] Q112 = mem[112];
wire [6:0] Q113 = mem[113];
wire [6:0] Q114 = mem[114];
wire [6:0] Q115 = mem[115];
wire [6:0] Q116 = mem[116];
wire [6:0] Q117 = mem[117];
wire [6:0] Q118 = mem[118];
wire [6:0] Q119 = mem[119];
wire [6:0] Q120 = mem[120];
wire [6:0] Q121 = mem[121];
wire [6:0] Q122 = mem[122];
wire [6:0] Q123 = mem[123];
wire [6:0] Q124 = mem[124];
wire [6:0] Q125 = mem[125];
wire [6:0] Q126 = mem[126];
wire [6:0] Q127 = mem[127];
wire [6:0] Q128 = mem[128];
wire [6:0] Q129 = mem[129];
wire [6:0] Q130 = mem[130];
wire [6:0] Q131 = mem[131];
wire [6:0] Q132 = mem[132];
wire [6:0] Q133 = mem[133];
wire [6:0] Q134 = mem[134];
wire [6:0] Q135 = mem[135];
wire [6:0] Q136 = mem[136];
wire [6:0] Q137 = mem[137];
wire [6:0] Q138 = mem[138];
wire [6:0] Q139 = mem[139];
wire [6:0] Q140 = mem[140];
wire [6:0] Q141 = mem[141];
wire [6:0] Q142 = mem[142];
wire [6:0] Q143 = mem[143];
wire [6:0] Q144 = mem[144];
wire [6:0] Q145 = mem[145];
wire [6:0] Q146 = mem[146];
wire [6:0] Q147 = mem[147];
wire [6:0] Q148 = mem[148];
wire [6:0] Q149 = mem[149];
wire [6:0] Q150 = mem[150];
wire [6:0] Q151 = mem[151];
wire [6:0] Q152 = mem[152];
wire [6:0] Q153 = mem[153];
wire [6:0] Q154 = mem[154];
wire [6:0] Q155 = mem[155];
wire [6:0] Q156 = mem[156];
wire [6:0] Q157 = mem[157];
wire [6:0] Q158 = mem[158];
wire [6:0] Q159 = mem[159];
wire [6:0] Q160 = mem[160];
wire [6:0] Q161 = mem[161];
wire [6:0] Q162 = mem[162];
wire [6:0] Q163 = mem[163];
wire [6:0] Q164 = mem[164];
wire [6:0] Q165 = mem[165];
wire [6:0] Q166 = mem[166];
wire [6:0] Q167 = mem[167];
wire [6:0] Q168 = mem[168];
wire [6:0] Q169 = mem[169];
wire [6:0] Q170 = mem[170];
wire [6:0] Q171 = mem[171];
wire [6:0] Q172 = mem[172];
wire [6:0] Q173 = mem[173];
wire [6:0] Q174 = mem[174];
wire [6:0] Q175 = mem[175];
wire [6:0] Q176 = mem[176];
wire [6:0] Q177 = mem[177];
wire [6:0] Q178 = mem[178];
wire [6:0] Q179 = mem[179];
wire [6:0] Q180 = mem[180];
wire [6:0] Q181 = mem[181];
wire [6:0] Q182 = mem[182];
wire [6:0] Q183 = mem[183];
wire [6:0] Q184 = mem[184];
wire [6:0] Q185 = mem[185];
wire [6:0] Q186 = mem[186];
wire [6:0] Q187 = mem[187];
wire [6:0] Q188 = mem[188];
wire [6:0] Q189 = mem[189];
wire [6:0] Q190 = mem[190];
wire [6:0] Q191 = mem[191];
wire [6:0] Q192 = mem[192];
wire [6:0] Q193 = mem[193];
wire [6:0] Q194 = mem[194];
wire [6:0] Q195 = mem[195];
wire [6:0] Q196 = mem[196];
wire [6:0] Q197 = mem[197];
wire [6:0] Q198 = mem[198];
wire [6:0] Q199 = mem[199];
wire [6:0] Q200 = mem[200];
wire [6:0] Q201 = mem[201];
wire [6:0] Q202 = mem[202];
wire [6:0] Q203 = mem[203];
wire [6:0] Q204 = mem[204];
wire [6:0] Q205 = mem[205];
wire [6:0] Q206 = mem[206];
wire [6:0] Q207 = mem[207];
wire [6:0] Q208 = mem[208];
wire [6:0] Q209 = mem[209];
wire [6:0] Q210 = mem[210];
wire [6:0] Q211 = mem[211];
wire [6:0] Q212 = mem[212];
wire [6:0] Q213 = mem[213];
wire [6:0] Q214 = mem[214];
wire [6:0] Q215 = mem[215];
wire [6:0] Q216 = mem[216];
wire [6:0] Q217 = mem[217];
wire [6:0] Q218 = mem[218];
wire [6:0] Q219 = mem[219];
wire [6:0] Q220 = mem[220];
wire [6:0] Q221 = mem[221];
wire [6:0] Q222 = mem[222];
wire [6:0] Q223 = mem[223];
wire [6:0] Q224 = mem[224];
wire [6:0] Q225 = mem[225];
wire [6:0] Q226 = mem[226];
wire [6:0] Q227 = mem[227];
wire [6:0] Q228 = mem[228];
wire [6:0] Q229 = mem[229];
wire [6:0] Q230 = mem[230];
wire [6:0] Q231 = mem[231];
wire [6:0] Q232 = mem[232];
wire [6:0] Q233 = mem[233];
wire [6:0] Q234 = mem[234];
wire [6:0] Q235 = mem[235];
wire [6:0] Q236 = mem[236];
wire [6:0] Q237 = mem[237];
wire [6:0] Q238 = mem[238];
wire [6:0] Q239 = mem[239];
wire [6:0] Q240 = mem[240];
wire [6:0] Q241 = mem[241];
wire [6:0] Q242 = mem[242];
wire [6:0] Q243 = mem[243];
wire [6:0] Q244 = mem[244];
wire [6:0] Q245 = mem[245];
wire [6:0] Q246 = mem[246];
wire [6:0] Q247 = mem[247];
wire [6:0] Q248 = mem[248];
wire [6:0] Q249 = mem[249];
wire [6:0] Q250 = mem[250];
wire [6:0] Q251 = mem[251];
wire [6:0] Q252 = mem[252];
wire [6:0] Q253 = mem[253];
wire [6:0] Q254 = mem[254];
wire [6:0] Q255 = mem[255];
`endif
// asynchronous ram writes
always @(*) begin
if ( we0 == 1'b1 ) begin
#0.1;
mem[Wa0] = Di0;
end
end
assign Do0 = mem[Ra0];
`endif
`endif
// synopsys translate_on
// synopsys dc_script_begin
// set_dont_touch { find (design, vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7) }
// set_attribute { find (design, vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7) } require_dont_touch true -type boolean
// synopsys dc_script_end
// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7] }
endmodule // vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7
//vmw: Memory vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7
//vmw: Address-size 8
//vmw: Data-size 7
//vmw: Sensitivity level 1
//vmw: Ports W R
//vmw: terminal we0 WriteEnable0
//vmw: terminal Wa0 address0
//vmw: terminal Di0[6:0] data0[6:0]
//vmw:
//vmw: terminal Ra0 address1
//vmw: terminal Do0[6:0] data1[6:0]
//vmw:
//qt: CELL vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7
//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1
//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1
//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1
//qt:
//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1
//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1
//qt:
`endif // EMU