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macroplacement
Commit f600e416 by ZhiangWang033
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202206091312

parent c42eb974
Showing with 3153 additions and 0 deletions
CodeElements/Grouping/ariane.fix 0 → 100644
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CodeElements/Grouping/design/1_synth.sdc 0 → 100644
#period set in nano-seconds - currently: 2ns = 500 MHz freq
create_clock [get_ports clk_i] -name core_clock -period 4
#
#set_input_delay -clock core_clock 0 [get_ports clk_i]
set_input_delay -clock core_clock 0 [get_ports rst_ni]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}]
set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}]
set_input_delay -clock core_clock 0 [get_ports ipi_i]
set_input_delay -clock core_clock 0 [get_ports time_irq_i]
set_input_delay -clock core_clock 0 [get_ports debug_req_i]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}]
set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}]
set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}]
CodeElements/Grouping/design/1_synth.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
CodeElements/Grouping/design/2_floorplan.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
CodeElements/Grouping/grouping.py 0 → 100644
import os
import argparse
import time
import shutil
import sys
from math import floor
sys.path.append('./utils')
####################################################################################
#### Extract hypergraph, instance, IO ports and outline from netlist
####################################################################################
def GenerateHypergraph(openroad_exe, setup_file, extract_hypergraph_file):
temp_file = os.getcwd() + "/extract_hypergraph.tcl"
cmd = "cp " + setup_file + " " + temp_file
os.system(cmd)
with open(extract_hypergraph_file) as f:
content = f.read().splitlines()
f.close()
f = open(temp_file, "a")
f.write("\n")
for line in content:
f.write(line + "\n")
f.close()
cmd = openroad_exe + " " + temp_file
os.system(cmd)
cmd = "rm " + temp_file
os.system(cmd)
if __name__ == '__main__':
parser = argparse.ArgumentParser()
parser.add_argument("design", help = "design name", type = str)
parser.add_argument("n_rows", help = "number of rows", type = int)
parser.add_argument("n_cols", help = "number of cols", type = int)
parser.add_argument("--setup_file", help = "setup file for openroad (default = setup.tcl)", type = str, default = "setup.tcl")
args = parser.parse_args()
design = args.design
n_rows = args.n_rows
n_cols = args.n_cols
setup_file = args.setup_file
pwd = os.getcwd()
# Specify the location of hmetis exe and openroad exe
openroad_exe = pwd + "/utils/openroad"
extract_hypergraph_file = pwd + "/utils/extract_hypergraph.tcl"
# Generate Hypergraph file
rpt_dir = pwd + "/rtl_mp"
hypergraph_file = rpt_dir + "/" + design + ".hgr"
io_name_file = hypergraph_file + ".io"
instance_name_file = hypergraph_file + ".instance"
outline_file = hypergraph_file + ".outline"
GenerateHypergraph(openroad_exe, setup_file, extract_hypergraph_file)
# Generate fix file
fix_file = design + ".fix"
print("[INFO] Generated fix file : ", fix_file)
# Step 1: Grouping bundled IOs based on n_rows and n_cols
with open(outline_file) as f:
content = f.read().splitlines()
f.close()
items = content[0].split()
floorplan_lx = float(items[0])
floorplan_ly = float(items[1])
floorplan_ux = float(items[2])
floorplan_uy = float(items[3])
width = (floorplan_ux - floorplan_lx) / n_cols
height = (floorplan_uy - floorplan_ly) / n_rows
group_map = { }
io_inst_map = { }
vertex_list = []
grid_row_max = 100000000
with open(io_name_file) as f:
content = f.read().splitlines()
f.close()
for line in content:
items = line.split()
io_name = items[0]
vertex_list.append(io_name)
x = (float(items[1]) + float(items[3])) / 2.0
y = (float(items[2]) + float(items[4])) / 2.0
hash_id = floor(y / height) * grid_row_max + floor(x / width)
io_inst_map[io_name] = hash_id
if hash_id not in group_map:
group_map[hash_id] = [io_name]
else:
group_map[hash_id].append(io_name)
hash_id = max(group_map.keys()) + 1
with open(instance_name_file) as f:
content = f.read().splitlines()
f.close()
for line in content:
items = line.split()
inst_name = items[0]
vertex_list.append(inst_name)
if (int(items[1]) == 1):
group_map[hash_id] = [inst_name]
io_inst_map[inst_name] = hash_id
hash_id += 1
glue_inst = { }
with open(hypergraph_file) as f:
content = f.read().splitlines()
f.close()
for i in range(1, len(content)):
items = [vertex_list[int(item) -1] for item in content[i].split()]
if(len(items) > 100):
continue
group_list = []
flag = False
for item in items:
if item in io_inst_map:
flag = True
group_list.append(item)
if (flag == True):
for item in items:
if item not in group_list:
for inst in group_list:
group_map[io_inst_map[inst]].append(item)
if item not in glue_inst:
glue_inst[item] = [inst]
else:
glue_inst[item].append(inst)
for key, value in glue_inst.items():
if(len(value) > 1):
print(value)
group_id = 0
f = open(fix_file, "w")
for key, value in group_map.items():
line = "group_" + str(group_id) + ": "
group_id += 1
for io in value:
line += io + " "
line += "\n"
f.write(line)
f.close()
CodeElements/Grouping/lefs/NangateOpenCellLibrary.macro.mod.lef 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
CodeElements/Grouping/lefs/NangateOpenCellLibrary.tech.lef 0 → 100644
#
# ******************************************************************************
# * *
# * Copyright (C) 2004-2010, Nangate Inc. *
# * All rights reserved. *
# * *
# * Nangate and the Nangate logo are trademarks of Nangate Inc. *
# * *
# * All trademarks, logos, software marks, and trade names (collectively the *
# * "Marks") in this program are proprietary to Nangate or other respective *
# * owners that have granted Nangate the right and license to use such Marks. *
# * You are not permitted to use the Marks without the prior written consent *
# * of Nangate or such third party that may own the Marks. *
# * *
# * This file has been provided pursuant to a License Agreement containing *
# * restrictions on its use. This file contains valuable trade secrets and *
# * proprietary information of Nangate Inc., and is protected by U.S. and *
# * international laws and/or treaties. *
# * *
# * The copyright notice(s) in this file does not indicate actual or intended *
# * publication of this file. *
# * *
# * NGLibraryCreator, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 *
# * *
# ******************************************************************************
#
#
# Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
# Local time is now Fri, 3 Dec 2010, 19:32:18.
# Main process id is 27821.
VERSION 5.6 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
UNITS
DATABASE MICRONS 2000 ;
END UNITS
MANUFACTURINGGRID 0.0050 ;
LAYER poly
TYPE MASTERSLICE ;
END poly
LAYER active
TYPE MASTERSLICE ;
END active
LAYER metal1
TYPE ROUTING ;
SPACING 0.065 ;
WIDTH 0.07 ;
PITCH 0.14 ;
DIRECTION HORIZONTAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.38 ;
THICKNESS 0.13 ;
HEIGHT 0.37 ;
CAPACITANCE CPERSQDIST 7.7161e-05 ;
EDGECAPACITANCE 2.7365e-05 ;
END metal1
LAYER via1
TYPE CUT ;
SPACING 0.08 ;
WIDTH 0.07 ;
RESISTANCE 5 ;
END via1
LAYER metal2
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 0.3000 0.9000 1.8000 2.7000 4.0000
WIDTH 0.0000 0.0700 0.0700 0.0700 0.0700 0.0700 0.0700
WIDTH 0.0900 0.0700 0.0900 0.0900 0.0900 0.0900 0.0900
WIDTH 0.2700 0.0700 0.0900 0.2700 0.2700 0.2700 0.2700
WIDTH 0.5000 0.0700 0.0900 0.2700 0.5000 0.5000 0.5000
WIDTH 0.9000 0.0700 0.0900 0.2700 0.5000 0.9000 0.9000
WIDTH 1.5000 0.0700 0.0900 0.2700 0.5000 0.9000 1.5000 ;
WIDTH 0.07 ;
PITCH 0.19 ;
DIRECTION VERTICAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.25 ;
THICKNESS 0.14 ;
HEIGHT 0.62 ;
CAPACITANCE CPERSQDIST 4.0896e-05 ;
EDGECAPACITANCE 2.5157e-05 ;
END metal2
LAYER via2
TYPE CUT ;
SPACING 0.09 ;
WIDTH 0.07 ;
RESISTANCE 5 ;
END via2
LAYER metal3
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 0.3000 0.9000 1.8000 2.7000 4.0000
WIDTH 0.0000 0.0700 0.0700 0.0700 0.0700 0.0700 0.0700
WIDTH 0.0900 0.0700 0.0900 0.0900 0.0900 0.0900 0.0900
WIDTH 0.2700 0.0700 0.0900 0.2700 0.2700 0.2700 0.2700
WIDTH 0.5000 0.0700 0.0900 0.2700 0.5000 0.5000 0.5000
WIDTH 0.9000 0.0700 0.0900 0.2700 0.5000 0.9000 0.9000
WIDTH 1.5000 0.0700 0.0900 0.2700 0.5000 0.9000 1.5000 ;
WIDTH 0.07 ;
PITCH 0.14 ;
DIRECTION HORIZONTAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.25 ;
THICKNESS 0.14 ;
HEIGHT 0.88 ;
CAPACITANCE CPERSQDIST 2.7745e-05 ;
EDGECAPACITANCE 2.5157e-05 ;
END metal3
LAYER via3
TYPE CUT ;
SPACING 0.09 ;
WIDTH 0.07 ;
RESISTANCE 5 ;
END via3
LAYER metal4
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000
WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400
WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700
WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000
WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000
WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ;
WIDTH 0.14 ;
PITCH 0.28 ;
DIRECTION VERTICAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.21 ;
THICKNESS 0.28 ;
HEIGHT 1.14 ;
CAPACITANCE CPERSQDIST 2.0743e-05 ;
EDGECAPACITANCE 3.0908e-05 ;
END metal4
LAYER via4
TYPE CUT ;
SPACING 0.16 ;
WIDTH 0.14 ;
RESISTANCE 3 ;
END via4
LAYER metal5
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000
WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400
WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700
WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000
WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000
WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ;
WIDTH 0.14 ;
PITCH 0.28 ;
DIRECTION HORIZONTAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.21 ;
THICKNESS 0.28 ;
HEIGHT 1.71 ;
CAPACITANCE CPERSQDIST 1.3527e-05 ;
EDGECAPACITANCE 2.3863e-06 ;
END metal5
LAYER via5
TYPE CUT ;
SPACING 0.16 ;
WIDTH 0.14 ;
RESISTANCE 3 ;
END via5
LAYER metal6
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000
WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400
WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700
WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000
WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000
WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ;
WIDTH 0.14 ;
PITCH 0.28 ;
DIRECTION VERTICAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.21 ;
THICKNESS 0.28 ;
HEIGHT 2.28 ;
CAPACITANCE CPERSQDIST 1.0036e-05 ;
EDGECAPACITANCE 2.3863e-05 ;
END metal6
LAYER via6
TYPE CUT ;
SPACING 0.16 ;
WIDTH 0.14 ;
RESISTANCE 3 ;
END via6
LAYER metal7
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 1.8000 2.7000 4.0000
WIDTH 0.0000 0.4000 0.4000 0.4000 0.4000
WIDTH 0.5000 0.4000 0.5000 0.5000 0.5000
WIDTH 0.9000 0.4000 0.5000 0.9000 0.9000
WIDTH 1.5000 0.4000 0.5000 0.9000 1.5000 ;
WIDTH 0.4 ;
PITCH 0.8 ;
DIRECTION HORIZONTAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.075 ;
THICKNESS 0.8 ;
HEIGHT 2.85 ;
CAPACITANCE CPERSQDIST 7.9771e-06 ;
EDGECAPACITANCE 3.2577e-05 ;
END metal7
LAYER via7
TYPE CUT ;
SPACING 0.44 ;
WIDTH 0.4 ;
RESISTANCE 1 ;
END via7
LAYER metal8
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 1.8000 2.7000 4.0000
WIDTH 0.0000 0.4000 0.4000 0.4000 0.4000
WIDTH 0.5000 0.4000 0.5000 0.5000 0.5000
WIDTH 0.9000 0.4000 0.5000 0.9000 0.9000
WIDTH 1.5000 0.4000 0.5000 0.9000 1.5000 ;
WIDTH 0.4 ;
PITCH 0.8 ;
DIRECTION VERTICAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.075 ;
THICKNESS 0.8 ;
HEIGHT 4.47 ;
CAPACITANCE CPERSQDIST 5.0391e-06 ;
EDGECAPACITANCE 2.3932e-05 ;
END metal8
LAYER via8
TYPE CUT ;
SPACING 0.44 ;
WIDTH 0.4 ;
RESISTANCE 1 ;
END via8
LAYER metal9
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 2.7000 4.0000
WIDTH 0.0000 0.8000 0.8000 0.8000
WIDTH 0.9000 0.8000 0.9000 0.9000
WIDTH 1.5000 0.8000 0.9000 1.5000 ;
WIDTH 0.8 ;
PITCH 1.6 ;
DIRECTION HORIZONTAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.03 ;
THICKNESS 2 ;
HEIGHT 6.09 ;
CAPACITANCE CPERSQDIST 3.6827e-06 ;
EDGECAPACITANCE 3.0803e-05 ;
END metal9
LAYER via9
TYPE CUT ;
SPACING 0.88 ;
WIDTH 0.8 ;
RESISTANCE 0.5 ;
END via9
LAYER metal10
TYPE ROUTING ;
SPACINGTABLE
PARALLELRUNLENGTH 0.0000 2.7000 4.0000
WIDTH 0.0000 0.8000 0.8000 0.8000
WIDTH 0.9000 0.8000 0.9000 0.9000
WIDTH 1.5000 0.8000 0.9000 1.5000 ;
WIDTH 0.8 ;
PITCH 1.6 ;
DIRECTION VERTICAL ;
OFFSET 0.095 0.07 ;
RESISTANCE RPERSQ 0.03 ;
THICKNESS 2 ;
HEIGHT 10.09 ;
CAPACITANCE CPERSQDIST 2.2124e-06 ;
EDGECAPACITANCE 2.3667e-05 ;
END metal10
LAYER OVERLAP
TYPE OVERLAP ;
END OVERLAP
VIA via1_4 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.035 -0.07 0.035 0.07 ;
LAYER metal2 ;
RECT -0.035 -0.07 0.035 0.07 ;
END via1_4
VIA via1_0 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal2 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via1_0
VIA via1_1 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal2 ;
RECT -0.035 -0.07 0.035 0.07 ;
END via1_1
VIA via1_2 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal2 ;
RECT -0.07 -0.035 0.07 0.035 ;
END via1_2
VIA via1_3 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.035 -0.07 0.035 0.07 ;
LAYER metal2 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via1_3
VIA via1_5 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.035 -0.07 0.035 0.07 ;
LAYER metal2 ;
RECT -0.07 -0.035 0.07 0.035 ;
END via1_5
VIA via1_6 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.07 -0.035 0.07 0.035 ;
LAYER metal2 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via1_6
VIA via1_7 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.07 -0.035 0.07 0.035 ;
LAYER metal2 ;
RECT -0.035 -0.07 0.035 0.07 ;
END via1_7
VIA via1_8 DEFAULT
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal1 ;
RECT -0.07 -0.035 0.07 0.035 ;
LAYER metal2 ;
RECT -0.07 -0.035 0.07 0.035 ;
END via1_8
VIA via2_8 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.07 -0.035 0.07 0.035 ;
LAYER metal3 ;
RECT -0.07 -0.035 0.07 0.035 ;
END via2_8
VIA via2_4 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.035 -0.07 0.035 0.07 ;
LAYER metal3 ;
RECT -0.035 -0.07 0.035 0.07 ;
END via2_4
VIA via2_5 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.035 -0.07 0.035 0.07 ;
LAYER metal3 ;
RECT -0.07 -0.035 0.07 0.035 ;
END via2_5
VIA via2_7 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.07 -0.035 0.07 0.035 ;
LAYER metal3 ;
RECT -0.035 -0.07 0.035 0.07 ;
END via2_7
VIA via2_6 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.07 -0.035 0.07 0.035 ;
LAYER metal3 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via2_6
VIA via2_0 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal3 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via2_0
VIA via2_1 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal3 ;
RECT -0.035 -0.07 0.035 0.07 ;
END via2_1
VIA via2_2 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal3 ;
RECT -0.07 -0.035 0.07 0.035 ;
END via2_2
VIA via2_3 DEFAULT
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal2 ;
RECT -0.035 -0.07 0.035 0.07 ;
LAYER metal3 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via2_3
VIA via3_2 DEFAULT
LAYER via3 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal3 ;
RECT -0.07 -0.035 0.07 0.035 ;
LAYER metal4 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via3_2
VIA via3_0 DEFAULT
LAYER via3 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal3 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal4 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via3_0
VIA via3_1 DEFAULT
LAYER via3 ;
RECT -0.035 -0.035 0.035 0.035 ;
LAYER metal3 ;
RECT -0.035 -0.07 0.035 0.07 ;
LAYER metal4 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via3_1
VIA via4_0 DEFAULT
LAYER via4 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal4 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal5 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via4_0
VIA via5_0 DEFAULT
LAYER via5 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal5 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal6 ;
RECT -0.07 -0.07 0.07 0.07 ;
END via5_0
VIA via6_0 DEFAULT
LAYER via6 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal6 ;
RECT -0.07 -0.07 0.07 0.07 ;
LAYER metal7 ;
RECT -0.2 -0.2 0.2 0.2 ;
END via6_0
VIA via7_0 DEFAULT
LAYER via7 ;
RECT -0.2 -0.2 0.2 0.2 ;
LAYER metal7 ;
RECT -0.2 -0.2 0.2 0.2 ;
LAYER metal8 ;
RECT -0.2 -0.2 0.2 0.2 ;
END via7_0
VIA via8_0 DEFAULT
LAYER via8 ;
RECT -0.2 -0.2 0.2 0.2 ;
LAYER metal8 ;
RECT -0.2 -0.2 0.2 0.2 ;
LAYER metal9 ;
RECT -0.4 -0.4 0.4 0.4 ;
END via8_0
VIA via9_0 DEFAULT
LAYER via9 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER metal9 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER metal10 ;
RECT -0.4 -0.4 0.4 0.4 ;
END via9_0
VIARULE Via1Array-0 GENERATE
LAYER metal1 ;
ENCLOSURE 0.035 0.035 ;
LAYER metal2 ;
ENCLOSURE 0.035 0.035 ;
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.15 BY 0.15 ;
END Via1Array-0
VIARULE Via1Array-1 GENERATE
LAYER metal1 ;
ENCLOSURE 0 0.035 ;
LAYER metal2 ;
ENCLOSURE 0 0.035 ;
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.15 BY 0.15 ;
END Via1Array-1
VIARULE Via1Array-2 GENERATE
LAYER metal1 ;
ENCLOSURE 0.035 0 ;
LAYER metal2 ;
ENCLOSURE 0.035 0 ;
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.15 BY 0.15 ;
END Via1Array-2
VIARULE Via1Array-3 GENERATE
LAYER metal1 ;
ENCLOSURE 0 0.035 ;
LAYER metal2 ;
ENCLOSURE 0.035 0 ;
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.15 BY 0.15 ;
END Via1Array-3
VIARULE Via1Array-4 GENERATE
LAYER metal1 ;
ENCLOSURE 0.035 0 ;
LAYER metal2 ;
ENCLOSURE 0 0.035 ;
LAYER via1 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.15 BY 0.15 ;
END Via1Array-4
VIARULE Via2Array-0 GENERATE
LAYER metal2 ;
ENCLOSURE 0.035 0.035 ;
LAYER metal3 ;
ENCLOSURE 0.035 0.035 ;
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.16 BY 0.16 ;
END Via2Array-0
VIARULE Via2Array-1 GENERATE
LAYER metal2 ;
ENCLOSURE 0 0.035 ;
LAYER metal3 ;
ENCLOSURE 0 0.035 ;
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.16 BY 0.16 ;
END Via2Array-1
VIARULE Via2Array-2 GENERATE
LAYER metal2 ;
ENCLOSURE 0.035 0 ;
LAYER metal3 ;
ENCLOSURE 0.035 0 ;
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.16 BY 0.16 ;
END Via2Array-2
VIARULE Via2Array-3 GENERATE
LAYER metal2 ;
ENCLOSURE 0 0.035 ;
LAYER metal3 ;
ENCLOSURE 0.035 0 ;
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.16 BY 0.16 ;
END Via2Array-3
VIARULE Via2Array-4 GENERATE
LAYER metal2 ;
ENCLOSURE 0.035 0 ;
LAYER metal3 ;
ENCLOSURE 0 0.035 ;
LAYER via2 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.16 BY 0.16 ;
END Via2Array-4
VIARULE Via3Array-0 GENERATE
LAYER metal3 ;
ENCLOSURE 0.035 0.035 ;
LAYER metal4 ;
ENCLOSURE 0.035 0.035 ;
LAYER via3 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.16 BY 0.16 ;
END Via3Array-0
VIARULE Via3Array-1 GENERATE
LAYER metal3 ;
ENCLOSURE 0 0.035 ;
LAYER metal4 ;
ENCLOSURE 0.035 0.035 ;
LAYER via3 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.16 BY 0.16 ;
END Via3Array-1
VIARULE Via3Array-2 GENERATE
LAYER metal3 ;
ENCLOSURE 0.035 0 ;
LAYER metal4 ;
ENCLOSURE 0.035 0.035 ;
LAYER via3 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.16 BY 0.16 ;
END Via3Array-2
VIARULE Via4Array-0 GENERATE
LAYER metal4 ;
ENCLOSURE 0 0 ;
LAYER metal5 ;
ENCLOSURE 0 0 ;
LAYER via4 ;
RECT -0.07 -0.07 0.07 0.07 ;
SPACING 0.3 BY 0.3 ;
END Via4Array-0
VIARULE Via5Array-0 GENERATE
LAYER metal5 ;
ENCLOSURE 0 0 ;
LAYER metal6 ;
ENCLOSURE 0 0 ;
LAYER via5 ;
RECT -0.07 -0.07 0.07 0.07 ;
SPACING 0.3 BY 0.3 ;
END Via5Array-0
VIARULE Via6Array-0 GENERATE
LAYER metal6 ;
ENCLOSURE 0 0 ;
LAYER metal7 ;
ENCLOSURE 0.13 0.13 ;
LAYER via6 ;
RECT -0.07 -0.07 0.07 0.07 ;
SPACING 0.3 BY 0.3 ;
END Via6Array-0
VIARULE Via7Array-0 GENERATE
LAYER metal7 ;
ENCLOSURE 0 0 ;
LAYER metal8 ;
ENCLOSURE 0 0 ;
LAYER via7 ;
RECT -0.2 -0.2 0.2 0.2 ;
SPACING 0.84 BY 0.84 ;
END Via7Array-0
VIARULE Via8Array-0 GENERATE
LAYER metal8 ;
ENCLOSURE 0 0 ;
LAYER metal9 ;
ENCLOSURE 0.2 0.2 ;
LAYER via8 ;
RECT -0.2 -0.2 0.2 0.2 ;
SPACING 0.84 BY 0.84 ;
END Via8Array-0
VIARULE Via9Array-0 GENERATE
LAYER metal10 ;
ENCLOSURE 0 0 ;
LAYER metal9 ;
ENCLOSURE 0 0 ;
LAYER via9 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.68 BY 1.68 ;
END Via9Array-0
SPACING
SAMENET metal1 metal1 0.065 ;
SAMENET metal2 metal2 0.07 ;
SAMENET metal3 metal3 0.07 ;
SAMENET metal4 metal4 0.14 ;
SAMENET metal5 metal5 0.14 ;
SAMENET metal6 metal6 0.14 ;
SAMENET metal7 metal7 0.4 ;
SAMENET metal8 metal8 0.4 ;
SAMENET metal9 metal9 0.8 ;
SAMENET metal10 metal10 0.8 ;
SAMENET via1 via1 0.08 ;
SAMENET via2 via2 0.09 ;
SAMENET via3 via3 0.09 ;
SAMENET via4 via4 0.16 ;
SAMENET via5 via5 0.16 ;
SAMENET via6 via6 0.16 ;
SAMENET via7 via7 0.44 ;
SAMENET via8 via8 0.44 ;
SAMENET via9 via9 0.88 ;
SAMENET via1 via2 0.0 STACK ;
SAMENET via2 via3 0.0 STACK ;
SAMENET via3 via4 0.0 STACK ;
SAMENET via4 via5 0.0 STACK ;
SAMENET via5 via6 0.0 STACK ;
SAMENET via6 via7 0.0 STACK ;
SAMENET via7 via8 0.0 STACK ;
SAMENET via8 via9 0.0 STACK ;
END SPACING
SITE FreePDK45_38x28_10R_NP_162NW_34O
SYMMETRY y ;
CLASS core ;
SIZE 0.19 BY 1.4 ;
END FreePDK45_38x28_10R_NP_162NW_34O
END LIBRARY
#
# End of file
#
CodeElements/Grouping/lefs/fakeram45_256x16.lef 0 → 100644
VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_256x16
FOREIGN fakeram45_256x16 0 0 ;
SYMMETRY X Y R90 ;
SIZE 57.570 BY 133.000 ;
CLASS BLOCK ;
PIN w_mask_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.065 0.070 2.135 ;
END
END w_mask_in[0]
PIN w_mask_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.165 0.070 4.235 ;
END
END w_mask_in[1]
PIN w_mask_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.265 0.070 6.335 ;
END
END w_mask_in[2]
PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.365 0.070 8.435 ;
END
END w_mask_in[3]
PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.465 0.070 10.535 ;
END
END w_mask_in[4]
PIN w_mask_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.565 0.070 12.635 ;
END
END w_mask_in[5]
PIN w_mask_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.665 0.070 14.735 ;
END
END w_mask_in[6]
PIN w_mask_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.765 0.070 16.835 ;
END
END w_mask_in[7]
PIN w_mask_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.865 0.070 18.935 ;
END
END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.965 0.070 21.035 ;
END
END w_mask_in[9]
PIN w_mask_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.065 0.070 23.135 ;
END
END w_mask_in[10]
PIN w_mask_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.165 0.070 25.235 ;
END
END w_mask_in[11]
PIN w_mask_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.265 0.070 27.335 ;
END
END w_mask_in[12]
PIN w_mask_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 29.365 0.070 29.435 ;
END
END w_mask_in[13]
PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 31.465 0.070 31.535 ;
END
END w_mask_in[14]
PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 33.565 0.070 33.635 ;
END
END w_mask_in[15]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 34.615 0.070 34.685 ;
END
END rd_out[0]
PIN rd_out[1]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.715 0.070 36.785 ;
END
END rd_out[1]
PIN rd_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.815 0.070 38.885 ;
END
END rd_out[2]
PIN rd_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.915 0.070 40.985 ;
END
END rd_out[3]
PIN rd_out[4]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.015 0.070 43.085 ;
END
END rd_out[4]
PIN rd_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.115 0.070 45.185 ;
END
END rd_out[5]
PIN rd_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.215 0.070 47.285 ;
END
END rd_out[6]
PIN rd_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.315 0.070 49.385 ;
END
END rd_out[7]
PIN rd_out[8]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.415 0.070 51.485 ;
END
END rd_out[8]
PIN rd_out[9]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.515 0.070 53.585 ;
END
END rd_out[9]
PIN rd_out[10]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.615 0.070 55.685 ;
END
END rd_out[10]
PIN rd_out[11]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.715 0.070 57.785 ;
END
END rd_out[11]
PIN rd_out[12]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.815 0.070 59.885 ;
END
END rd_out[12]
PIN rd_out[13]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.915 0.070 61.985 ;
END
END rd_out[13]
PIN rd_out[14]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 64.015 0.070 64.085 ;
END
END rd_out[14]
PIN rd_out[15]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 66.115 0.070 66.185 ;
END
END rd_out[15]
PIN wd_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 67.165 0.070 67.235 ;
END
END wd_in[0]
PIN wd_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.265 0.070 69.335 ;
END
END wd_in[1]
PIN wd_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.365 0.070 71.435 ;
END
END wd_in[2]
PIN wd_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.465 0.070 73.535 ;
END
END wd_in[3]
PIN wd_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.565 0.070 75.635 ;
END
END wd_in[4]
PIN wd_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.665 0.070 77.735 ;
END
END wd_in[5]
PIN wd_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.765 0.070 79.835 ;
END
END wd_in[6]
PIN wd_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.865 0.070 81.935 ;
END
END wd_in[7]
PIN wd_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.965 0.070 84.035 ;
END
END wd_in[8]
PIN wd_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.065 0.070 86.135 ;
END
END wd_in[9]
PIN wd_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.165 0.070 88.235 ;
END
END wd_in[10]
PIN wd_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.265 0.070 90.335 ;
END
END wd_in[11]
PIN wd_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.365 0.070 92.435 ;
END
END wd_in[12]
PIN wd_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.465 0.070 94.535 ;
END
END wd_in[13]
PIN wd_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.565 0.070 96.635 ;
END
END wd_in[14]
PIN wd_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 98.665 0.070 98.735 ;
END
END wd_in[15]
PIN addr_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 99.715 0.070 99.785 ;
END
END addr_in[0]
PIN addr_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 101.815 0.070 101.885 ;
END
END addr_in[1]
PIN addr_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.915 0.070 103.985 ;
END
END addr_in[2]
PIN addr_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 106.015 0.070 106.085 ;
END
END addr_in[3]
PIN addr_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 108.115 0.070 108.185 ;
END
END addr_in[4]
PIN addr_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 110.215 0.070 110.285 ;
END
END addr_in[5]
PIN addr_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 112.315 0.070 112.385 ;
END
END addr_in[6]
PIN addr_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 114.415 0.070 114.485 ;
END
END addr_in[7]
PIN we_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 115.465 0.070 115.535 ;
END
END we_in
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 117.565 0.070 117.635 ;
END
END ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 119.665 0.070 119.735 ;
END
END clk
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER metal4 ;
RECT 1.960 2.100 2.240 130.900 ;
RECT 5.320 2.100 5.600 130.900 ;
RECT 8.680 2.100 8.960 130.900 ;
RECT 12.040 2.100 12.320 130.900 ;
RECT 15.400 2.100 15.680 130.900 ;
RECT 18.760 2.100 19.040 130.900 ;
RECT 22.120 2.100 22.400 130.900 ;
RECT 25.480 2.100 25.760 130.900 ;
RECT 28.840 2.100 29.120 130.900 ;
RECT 32.200 2.100 32.480 130.900 ;
RECT 35.560 2.100 35.840 130.900 ;
RECT 38.920 2.100 39.200 130.900 ;
RECT 42.280 2.100 42.560 130.900 ;
RECT 45.640 2.100 45.920 130.900 ;
RECT 49.000 2.100 49.280 130.900 ;
RECT 52.360 2.100 52.640 130.900 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER metal4 ;
RECT 3.640 2.100 3.920 130.900 ;
RECT 7.000 2.100 7.280 130.900 ;
RECT 10.360 2.100 10.640 130.900 ;
RECT 13.720 2.100 14.000 130.900 ;
RECT 17.080 2.100 17.360 130.900 ;
RECT 20.440 2.100 20.720 130.900 ;
RECT 23.800 2.100 24.080 130.900 ;
RECT 27.160 2.100 27.440 130.900 ;
RECT 30.520 2.100 30.800 130.900 ;
RECT 33.880 2.100 34.160 130.900 ;
RECT 37.240 2.100 37.520 130.900 ;
RECT 40.600 2.100 40.880 130.900 ;
RECT 43.960 2.100 44.240 130.900 ;
RECT 47.320 2.100 47.600 130.900 ;
RECT 50.680 2.100 50.960 130.900 ;
RECT 54.040 2.100 54.320 130.900 ;
END
END VDD
OBS
LAYER metal1 ;
RECT 0 0 57.570 133.000 ;
LAYER metal2 ;
RECT 0 0 57.570 133.000 ;
LAYER metal3 ;
RECT 0.070 0 57.570 133.000 ;
RECT 0 0.000 0.070 2.065 ;
RECT 0 2.135 0.070 4.165 ;
RECT 0 4.235 0.070 6.265 ;
RECT 0 6.335 0.070 8.365 ;
RECT 0 8.435 0.070 10.465 ;
RECT 0 10.535 0.070 12.565 ;
RECT 0 12.635 0.070 14.665 ;
RECT 0 14.735 0.070 16.765 ;
RECT 0 16.835 0.070 18.865 ;
RECT 0 18.935 0.070 20.965 ;
RECT 0 21.035 0.070 23.065 ;
RECT 0 23.135 0.070 25.165 ;
RECT 0 25.235 0.070 27.265 ;
RECT 0 27.335 0.070 29.365 ;
RECT 0 29.435 0.070 31.465 ;
RECT 0 31.535 0.070 33.565 ;
RECT 0 33.635 0.070 34.615 ;
RECT 0 34.685 0.070 36.715 ;
RECT 0 36.785 0.070 38.815 ;
RECT 0 38.885 0.070 40.915 ;
RECT 0 40.985 0.070 43.015 ;
RECT 0 43.085 0.070 45.115 ;
RECT 0 45.185 0.070 47.215 ;
RECT 0 47.285 0.070 49.315 ;
RECT 0 49.385 0.070 51.415 ;
RECT 0 51.485 0.070 53.515 ;
RECT 0 53.585 0.070 55.615 ;
RECT 0 55.685 0.070 57.715 ;
RECT 0 57.785 0.070 59.815 ;
RECT 0 59.885 0.070 61.915 ;
RECT 0 61.985 0.070 64.015 ;
RECT 0 64.085 0.070 66.115 ;
RECT 0 66.185 0.070 67.165 ;
RECT 0 67.235 0.070 69.265 ;
RECT 0 69.335 0.070 71.365 ;
RECT 0 71.435 0.070 73.465 ;
RECT 0 73.535 0.070 75.565 ;
RECT 0 75.635 0.070 77.665 ;
RECT 0 77.735 0.070 79.765 ;
RECT 0 79.835 0.070 81.865 ;
RECT 0 81.935 0.070 83.965 ;
RECT 0 84.035 0.070 86.065 ;
RECT 0 86.135 0.070 88.165 ;
RECT 0 88.235 0.070 90.265 ;
RECT 0 90.335 0.070 92.365 ;
RECT 0 92.435 0.070 94.465 ;
RECT 0 94.535 0.070 96.565 ;
RECT 0 96.635 0.070 98.665 ;
RECT 0 98.735 0.070 99.715 ;
RECT 0 99.785 0.070 101.815 ;
RECT 0 101.885 0.070 103.915 ;
RECT 0 103.985 0.070 106.015 ;
RECT 0 106.085 0.070 108.115 ;
RECT 0 108.185 0.070 110.215 ;
RECT 0 110.285 0.070 112.315 ;
RECT 0 112.385 0.070 114.415 ;
RECT 0 114.485 0.070 115.465 ;
RECT 0 115.535 0.070 117.565 ;
RECT 0 117.635 0.070 119.665 ;
RECT 0 119.735 0.070 133.000 ;
LAYER metal4 ;
RECT 0 0 57.570 2.100 ;
RECT 0 130.900 57.570 133.000 ;
RECT 0.000 2.100 1.960 130.900 ;
RECT 2.240 2.100 3.640 130.900 ;
RECT 3.920 2.100 5.320 130.900 ;
RECT 5.600 2.100 7.000 130.900 ;
RECT 7.280 2.100 8.680 130.900 ;
RECT 8.960 2.100 10.360 130.900 ;
RECT 10.640 2.100 12.040 130.900 ;
RECT 12.320 2.100 13.720 130.900 ;
RECT 14.000 2.100 15.400 130.900 ;
RECT 15.680 2.100 17.080 130.900 ;
RECT 17.360 2.100 18.760 130.900 ;
RECT 19.040 2.100 20.440 130.900 ;
RECT 20.720 2.100 22.120 130.900 ;
RECT 22.400 2.100 23.800 130.900 ;
RECT 24.080 2.100 25.480 130.900 ;
RECT 25.760 2.100 27.160 130.900 ;
RECT 27.440 2.100 28.840 130.900 ;
RECT 29.120 2.100 30.520 130.900 ;
RECT 30.800 2.100 32.200 130.900 ;
RECT 32.480 2.100 33.880 130.900 ;
RECT 34.160 2.100 35.560 130.900 ;
RECT 35.840 2.100 37.240 130.900 ;
RECT 37.520 2.100 38.920 130.900 ;
RECT 39.200 2.100 40.600 130.900 ;
RECT 40.880 2.100 42.280 130.900 ;
RECT 42.560 2.100 43.960 130.900 ;
RECT 44.240 2.100 45.640 130.900 ;
RECT 45.920 2.100 47.320 130.900 ;
RECT 47.600 2.100 49.000 130.900 ;
RECT 49.280 2.100 50.680 130.900 ;
RECT 50.960 2.100 52.360 130.900 ;
RECT 52.640 2.100 54.040 130.900 ;
RECT 54.320 2.100 57.570 130.900 ;
LAYER OVERLAP ;
RECT 0 0 57.570 133.000 ;
END
END fakeram45_256x16
END LIBRARY
CodeElements/Grouping/libs/NangateOpenCellLibrary_typical.lib 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
CodeElements/Grouping/libs/fakeram45_256x16.lib 0 → 100644
library(fakeram45_256x16) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-05-18 16:05:50Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1uW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_256x16_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_256x16_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_256x16_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_256x16_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_256x16_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_256x16_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 16;
bit_from : 15;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_256x16_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 8;
bit_from : 7;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_256x16) {
area : 7656.810;
interface_timing : true;
memory() {
type : ram;
address_width : 8;
word_width : 16;
}
pin(clk) {
direction : input;
capacitance : 0.025;
clock : true;
min_period : 0.210 ;
internal_power(){
rise_power(fakeram45_256x16_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("2.355, 2.355")
}
fall_power(fakeram45_256x16_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("2.355, 2.355")
}
}
}
bus(rd_out) {
bus_type : fakeram45_256x16_DATA;
direction : output;
max_capacitance : 0.500;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(fakeram45_256x16_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.261, 0.261", \
"0.261, 0.261" \
)
}
cell_fall(fakeram45_256x16_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.261, 0.261", \
"0.261, 0.261" \
)
}
rise_transition(fakeram45_256x16_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
fall_transition(fakeram45_256x16_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
pin(ce_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
bus(addr_in) {
bus_type : fakeram45_256x16_ADDRESS;
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
bus(wd_in) {
bus_type : fakeram45_256x16_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_256x16_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x16_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
fall_power(fakeram45_256x16_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.024, 0.024")
}
}
}
cell_leakage_power : 432.350;
}
}
CodeElements/Grouping/rtl_mp/ariane.hgr 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
CodeElements/Grouping/rtl_mp/ariane.hgr.instance 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
CodeElements/Grouping/rtl_mp/ariane.hgr.io 0 → 100644
clk_i 0 876.155 0.07 876.225
rst_ni 0 785.435 0.07 785.505
boot_addr_i[63] 0 1325.28 0.07 1325.34
boot_addr_i[62] 0 658.035 0.07 658.105
boot_addr_i[61] 0 1317.99 0.07 1318.06
boot_addr_i[60] 0 1167.07 0.07 1167.15
boot_addr_i[59] 0 1408.99 0.07 1409.06
boot_addr_i[58] 0 1041.64 0.07 1041.7
boot_addr_i[57] 0 705.355 0.07 705.425
boot_addr_i[56] 0 728.875 0.07 728.945
boot_addr_i[55] 0 1474.52 0.07 1474.58
boot_addr_i[54] 0 1370.92 0.07 1370.98
boot_addr_i[53] 0 825.475 0.07 825.545
boot_addr_i[52] 0 1210.76 0.07 1210.82
boot_addr_i[51] 0 1309.04 0.07 1309.1
boot_addr_i[50] 0 701.715 0.07 701.785
boot_addr_i[49] 0 945.315 0.07 945.385
boot_addr_i[48] 0 1272.64 0.07 1272.7
boot_addr_i[47] 0 1190.88 0.07 1190.94
boot_addr_i[46] 0 1121.71 0.07 1121.79
boot_addr_i[45] 0 1349.07 0.07 1349.15
boot_addr_i[44] 0 1103.52 0.07 1103.58
boot_addr_i[43] 0 1090.92 0.07 1090.98
boot_addr_i[42] 0 763.595 0.07 763.665
boot_addr_i[41] 0 1478.16 0.07 1478.22
boot_addr_i[40] 0 610.715 0.07 610.785
boot_addr_i[39] 0 947.275 0.07 947.345
boot_addr_i[38] 0 1179.95 0.07 1180.03
boot_addr_i[37] 0 832.755 0.07 832.825
boot_addr_i[36] 0 1219.99 0.07 1220.06
boot_addr_i[35] 0 867.195 0.07 867.265
boot_addr_i[34] 0 609.035 0.07 609.105
boot_addr_i[33] 0 1079.99 0.07 1080.06
boot_addr_i[32] 0 990.675 0.07 990.745
boot_addr_i[31] 0 856.275 0.07 856.345
boot_addr_i[30] 0 768.915 0.07 768.985
boot_addr_i[29] 0 1105.47 0.07 1105.55
boot_addr_i[28] 0 1365.31 0.07 1365.39
boot_addr_i[27] 0 1141.59 0.07 1141.67
boot_addr_i[26] 0 1468.92 0.07 1468.98
boot_addr_i[25] 0 840.035 0.07 840.105
boot_addr_i[24] 0 1277.95 0.07 1278.03
boot_addr_i[23] 0 923.475 0.07 923.545
boot_addr_i[22] 0 1236.23 0.07 1236.31
boot_addr_i[21] 0 992.635 0.07 992.705
boot_addr_i[20] 0 1316.31 0.07 1316.39
boot_addr_i[19] 0 941.675 0.07 941.745
boot_addr_i[18] 0 807.275 0.07 807.345
boot_addr_i[17] 0 681.835 0.07 681.905
boot_addr_i[16] 0 854.595 0.07 854.665
boot_addr_i[15] 0 1312.68 0.07 1312.74
boot_addr_i[14] 0 1096.23 0.07 1096.31
boot_addr_i[13] 0 641.795 0.07 641.865
boot_addr_i[12] 0 741.755 0.07 741.825
boot_addr_i[11] 0 1407.04 0.07 1407.1
boot_addr_i[10] 0 1305.4 0.07 1305.46
boot_addr_i[9] 0 1203.47 0.07 1203.55
boot_addr_i[8] 0 1267.04 0.07 1267.1
boot_addr_i[7] 0 1489.07 0.07 1489.15
boot_addr_i[6] 0 1425.23 0.07 1425.31
boot_addr_i[5] 0 983.675 0.07 983.745
boot_addr_i[4] 0 1012.52 0.07 1012.59
boot_addr_i[3] 0 897.995 0.07 898.065
boot_addr_i[2] 0 1439.8 0.07 1439.86
boot_addr_i[1] 0 1136.28 0.07 1136.34
boot_addr_i[0] 0 974.435 0.07 974.505
hart_id_i[63] 0 1107.16 0.07 1107.22
hart_id_i[62] 0 616.315 0.07 616.385
hart_id_i[61] 0 1412.64 0.07 1412.7
hart_id_i[60] 0 1449.04 0.07 1449.1
hart_id_i[59] 0 743.435 0.07 743.505
hart_id_i[58] 0 1209.07 0.07 1209.15
hart_id_i[57] 0 978.075 0.07 978.145
hart_id_i[56] 0 1376.23 0.07 1376.31
hart_id_i[55] 0 887.075 0.07 887.145
hart_id_i[54] 0 938.035 0.07 938.105
hart_id_i[53] 0 1483.47 0.07 1483.55
hart_id_i[52] 0 1452.68 0.07 1452.74
hart_id_i[51] 0 667.275 0.07 667.345
hart_id_i[50] 0 881.755 0.07 881.825
hart_id_i[49] 0 698.075 0.07 698.145
hart_id_i[48] 0 1319.95 0.07 1320.03
hart_id_i[47] 0 1499.71 0.07 1499.79
hart_id_i[46] 0 1347.11 0.07 1347.19
hart_id_i[45] 0 659.995 0.07 660.065
hart_id_i[44] 0 1345.44 0.07 1345.51
hart_id_i[43] 0 980.035 0.07 980.105
hart_id_i[42] 0 1245.19 0.07 1245.27
hart_id_i[41] 0 987.035 0.07 987.105
hart_id_i[40] 0 1061.8 0.07 1061.86
hart_id_i[39] 0 1139.92 0.07 1139.98
hart_id_i[38] 0 1481.8 0.07 1481.86
hart_id_i[37] 0 1258.07 0.07 1258.15
hart_id_i[36] 0 1065.44 0.07 1065.51
hart_id_i[35] 0 994.315 0.07 994.385
hart_id_i[34] 0 1170.71 0.07 1170.79
hart_id_i[33] 0 1385.19 0.07 1385.27
hart_id_i[32] 0 1461.64 0.07 1461.7
hart_id_i[31] 0 1261.71 0.07 1261.79
hart_id_i[30] 0 703.675 0.07 703.745
hart_id_i[29] 0 1310.71 0.07 1310.79
hart_id_i[28] 0 1130.68 0.07 1130.74
hart_id_i[27] 0 1427.19 0.07 1427.27
hart_id_i[26] 0 865.235 0.07 865.305
hart_id_i[25] 0 1001.59 0.07 1001.66
hart_id_i[24] 0 1339.83 0.07 1339.91
hart_id_i[23] 0 1192.56 0.07 1192.62
hart_id_i[22] 0 1088.95 0.07 1089.03
hart_id_i[21] 0 714.595 0.07 714.665
hart_id_i[20] 0 1027.07 0.07 1027.15
hart_id_i[19] 0 1463.59 0.07 1463.67
hart_id_i[18] 0 819.875 0.07 819.945
hart_id_i[17] 0 1019.79 0.07 1019.86
hart_id_i[16] 0 963.515 0.07 963.585
hart_id_i[15] 0 1367.28 0.07 1367.34
hart_id_i[14] 0 1147.19 0.07 1147.27
hart_id_i[13] 0 623.595 0.07 623.665
hart_id_i[12] 0 1490.76 0.07 1490.82
hart_id_i[11] 0 759.955 0.07 760.025
hart_id_i[10] 0 767.235 0.07 767.305
hart_id_i[9] 0 805.315 0.07 805.385
hart_id_i[8] 0 969.115 0.07 969.185
hart_id_i[7] 0 970.795 0.07 970.865
hart_id_i[6] 0 1363.64 0.07 1363.7
hart_id_i[5] 0 1098.19 0.07 1098.27
hart_id_i[4] 0 787.115 0.07 787.185
hart_id_i[3] 0 1494.4 0.07 1494.46
hart_id_i[2] 0 1201.8 0.07 1201.86
hart_id_i[1] 0 1128.99 0.07 1129.06
hart_id_i[0] 0 750.715 0.07 750.785
irq_i[1] 0 649.075 0.07 649.145
irq_i[0] 0 1336.19 0.07 1336.27
ipi_i 0 847.315 0.07 847.385
time_irq_i 0 1163.44 0.07 1163.51
debug_req_i 0 672.595 0.07 672.665
axi_req_o[277] 0 689.115 0.07 689.185
axi_req_o[276] 0 1050.88 0.07 1050.94
axi_req_o[275] 0 1177.99 0.07 1178.06
axi_req_o[274] 0 1132.64 0.07 1132.7
axi_req_o[273] 0 1416.28 0.07 1416.34
axi_req_o[272] 0 959.875 0.07 959.945
axi_req_o[271] 0 934.395 0.07 934.465
axi_req_o[270] 0 814.555 0.07 814.625
axi_req_o[269] 0 652.715 0.07 652.785
axi_req_o[268] 0 1165.4 0.07 1165.46
axi_req_o[267] 0 1314.35 0.07 1314.43
axi_req_o[266] 0 1005.23 0.07 1005.3
axi_req_o[265] 0 899.955 0.07 900.025
axi_req_o[264] 0 1148.88 0.07 1148.94
axi_req_o[263] 0 765.275 0.07 765.345
axi_req_o[262] 0 1250.8 0.07 1250.86
axi_req_o[261] 0 1379.88 0.07 1379.94
axi_req_o[260] 0 1423.56 0.07 1423.62
axi_req_o[259] 0 954.555 0.07 954.625
axi_req_o[258] 0 1243.52 0.07 1243.58
axi_req_o[257] 0 1383.52 0.07 1383.58
axi_req_o[256] 0 1352.71 0.07 1352.79
axi_req_o[255] 0 627.235 0.07 627.305
axi_req_o[254] 0 1016.16 0.07 1016.22
axi_req_o[253] 0 1029.04 0.07 1029.1
axi_req_o[252] 0 1145.23 0.07 1145.31
axi_req_o[251] 0 607.075 0.07 607.145
axi_req_o[250] 0 1172.68 0.07 1172.74
axi_req_o[249] 0 1259.76 0.07 1259.82
axi_req_o[248] 0 1196.19 0.07 1196.27
axi_req_o[247] 0 1456.31 0.07 1456.39
axi_req_o[246] 0 1112.76 0.07 1112.82
axi_req_o[245] 0 1137.95 0.07 1138.03
axi_req_o[244] 0 1063.47 0.07 1063.55
axi_req_o[243] 0 1298.11 0.07 1298.19
axi_req_o[242] 0 1134.31 0.07 1134.39
axi_req_o[241] 0 1254.44 0.07 1254.51
axi_req_o[240] 0 1158.11 0.07 1158.19
axi_req_o[239] 0 910.875 0.07 910.945
axi_req_o[238] 0 956.235 0.07 956.305
axi_req_o[237] 0 1496.35 0.07 1496.43
axi_req_o[236] 0 770.875 0.07 770.945
axi_req_o[235] 0 1085.31 0.07 1085.39
axi_req_o[234] 0 943.635 0.07 943.705
axi_req_o[233] 0 1221.68 0.07 1221.74
axi_req_o[232] 0 1078.04 0.07 1078.1
axi_req_o[231] 0 1328.92 0.07 1328.98
axi_req_o[230] 0 676.235 0.07 676.305
axi_req_o[229] 0 1214.4 0.07 1214.46
axi_req_o[228] 0 1074.4 0.07 1074.46
axi_req_o[227] 0 872.515 0.07 872.585
axi_req_o[226] 0 1143.56 0.07 1143.62
axi_req_o[225] 0 1092.59 0.07 1092.67
axi_req_o[224] 0 1152.52 0.07 1152.58
axi_req_o[223] 0 836.395 0.07 836.465
axi_req_o[222] 0 1467.23 0.07 1467.31
axi_req_o[221] 0 972.755 0.07 972.825
axi_req_o[220] 0 1150.83 0.07 1150.91
axi_req_o[219] 0 1198.16 0.07 1198.22
axi_req_o[218] 0 1003.55 0.07 1003.62
axi_req_o[217] 0 1119.76 0.07 1119.82
axi_req_o[216] 0 852.635 0.07 852.705
axi_req_o[215] 0 1076.35 0.07 1076.43
axi_req_o[214] 0 1008.88 0.07 1008.95
axi_req_o[213] 0 961.835 0.07 961.905
axi_req_o[212] 0 1018.11 0.07 1018.18
axi_req_o[211] 0 1207.11 0.07 1207.19
axi_req_o[210] 0 997.955 0.07 998.025
axi_req_o[209] 0 1283.56 0.07 1283.62
axi_req_o[208] 0 921.795 0.07 921.865
axi_req_o[207] 0 1083.64 0.07 1083.7
axi_req_o[206] 0 674.555 0.07 674.625
axi_req_o[205] 0 1030.71 0.07 1030.79
axi_req_o[204] 0 803.635 0.07 803.705
axi_req_o[203] 0 685.475 0.07 685.545
axi_req_o[202] 0 1059.83 0.07 1059.91
axi_req_o[201] 0 1299.8 0.07 1299.86
axi_req_o[200] 0 630.875 0.07 630.945
axi_req_o[199] 0 1323.59 0.07 1323.67
axi_req_o[198] 0 868.875 0.07 868.945
axi_req_o[197] 0 903.595 0.07 903.665
axi_req_o[196] 0 1434.47 0.07 1434.55
axi_req_o[195] 0 1447.07 0.07 1447.15
axi_req_o[194] 0 1307.07 0.07 1307.15
axi_req_o[193] 0 857.955 0.07 858.025
axi_req_o[192] 0 808.955 0.07 809.025
axi_req_o[191] 0 1343.47 0.07 1343.55
axi_req_o[190] 0 1010.84 0.07 1010.91
axi_req_o[189] 0 919.835 0.07 919.905
axi_req_o[188] 0 1069.07 0.07 1069.15
axi_req_o[187] 0 619.955 0.07 620.025
axi_req_o[186] 0 789.075 0.07 789.145
axi_req_o[185] 0 1390.8 0.07 1390.86
axi_req_o[184] 0 908.915 0.07 908.985
axi_req_o[183] 0 918.155 0.07 918.225
axi_req_o[182] 0 1296.16 0.07 1296.22
axi_req_o[181] 0 708.995 0.07 709.065
axi_req_o[180] 0 1265.35 0.07 1265.43
axi_req_o[179] 0 1047.23 0.07 1047.31
axi_req_o[178] 0 1205.44 0.07 1205.51
axi_req_o[177] 0 636.195 0.07 636.265
axi_req_o[176] 0 1058.16 0.07 1058.22
axi_req_o[175] 0 1039.95 0.07 1040.03
axi_req_o[174] 0 1485.44 0.07 1485.51
axi_req_o[173] 0 645.435 0.07 645.505
axi_req_o[172] 0 799.995 0.07 800.065
axi_req_o[171] 0 939.995 0.07 940.065
axi_req_o[170] 0 1159.8 0.07 1159.86
axi_req_o[169] 0 948.955 0.07 949.025
axi_req_o[168] 0 1457.99 0.07 1458.06
axi_req_o[167] 0 736.155 0.07 736.225
axi_req_o[166] 0 1436.16 0.07 1436.22
axi_req_o[165] 0 634.515 0.07 634.585
axi_req_o[164] 0 914.515 0.07 914.585
axi_req_o[163] 0 1256.11 0.07 1256.19
axi_req_o[162] 0 1225.31 0.07 1225.39
axi_req_o[161] 0 999.915 0.07 999.985
axi_req_o[160] 0 1479.83 0.07 1479.91
axi_req_o[159] 0 1067.11 0.07 1067.19
axi_req_o[158] 0 632.555 0.07 632.625
axi_req_o[157] 0 1036.31 0.07 1036.39
axi_req_o[156] 0 843.675 0.07 843.745
axi_req_o[155] 0 967.155 0.07 967.225
axi_req_o[154] 0 1417.95 0.07 1418.03
axi_req_o[153] 0 1169.04 0.07 1169.1
axi_req_o[152] 0 778.155 0.07 778.225
axi_req_o[151] 0 716.275 0.07 716.345
axi_req_o[150] 0 739.795 0.07 739.865
axi_req_o[149] 0 617.995 0.07 618.065
axi_req_o[148] 0 1470.88 0.07 1470.94
axi_req_o[147] 0 1287.19 0.07 1287.27
axi_req_o[146] 0 661.675 0.07 661.745
axi_req_o[145] 0 692.755 0.07 692.825
axi_req_o[144] 0 1238.19 0.07 1238.27
axi_req_o[143] 0 1252.47 0.07 1252.55
axi_req_o[142] 0 1239.88 0.07 1239.94
axi_req_o[141] 0 1361.68 0.07 1361.74
axi_req_o[140] 0 1034.35 0.07 1034.43
axi_req_o[139] 0 1327.23 0.07 1327.31
axi_req_o[138] 0 601.755 0.07 601.825
axi_req_o[137] 0 818.195 0.07 818.265
axi_req_o[136] 0 1354.4 0.07 1354.46
axi_req_o[135] 0 1465.28 0.07 1465.34
axi_req_o[134] 0 1438.11 0.07 1438.19
axi_req_o[133] 0 670.915 0.07 670.985
axi_req_o[132] 0 738.115 0.07 738.185
axi_req_o[131] 0 1183.59 0.07 1183.67
axi_req_o[130] 0 830.795 0.07 830.865
axi_req_o[129] 0 1032.68 0.07 1032.74
axi_req_o[128] 0 870.835 0.07 870.905
axi_req_o[127] 0 812.595 0.07 812.665
axi_req_o[126] 0 1285.23 0.07 1285.31
axi_req_o[125] 0 816.235 0.07 816.305
axi_req_o[124] 0 892.675 0.07 892.745
axi_req_o[123] 0 850.955 0.07 851.025
axi_req_o[122] 0 848.995 0.07 849.065
axi_req_o[121] 0 1181.64 0.07 1181.7
axi_req_o[120] 0 1230.92 0.07 1230.98
axi_req_o[119] 0 1268.99 0.07 1269.06
axi_req_o[118] 0 930.755 0.07 930.825
axi_req_o[117] 0 752.675 0.07 752.745
axi_req_o[116] 0 712.635 0.07 712.705
axi_req_o[115] 0 792.715 0.07 792.785
axi_req_o[114] 0 665.315 0.07 665.385
axi_req_o[113] 0 1187.23 0.07 1187.31
axi_req_o[112] 0 996.275 0.07 996.345
axi_req_o[111] 0 1101.83 0.07 1101.91
axi_req_o[110] 0 883.435 0.07 883.505
axi_req_o[109] 0 612.675 0.07 612.745
axi_req_o[108] 0 1274.31 0.07 1274.39
axi_req_o[107] 0 654.395 0.07 654.465
axi_req_o[106] 0 1025.4 0.07 1025.46
axi_req_o[105] 0 1174.35 0.07 1174.43
axi_req_o[104] 0 1216.35 0.07 1216.43
axi_req_o[103] 0 861.595 0.07 861.665
axi_req_o[102] 0 1381.56 0.07 1381.62
axi_req_o[101] 0 965.475 0.07 965.545
axi_req_o[100] 0 988.995 0.07 989.065
axi_req_o[99] 0 679.875 0.07 679.945
axi_req_o[98] 0 1199.83 0.07 1199.91
axi_req_o[97] 0 1356.35 0.07 1356.43
axi_req_o[96] 0 916.195 0.07 916.265
axi_req_o[95] 0 1419.92 0.07 1419.98
axi_req_o[94] 0 727.195 0.07 727.265
axi_req_o[93] 0 874.475 0.07 874.545
axi_req_o[92] 0 1194.52 0.07 1194.58
axi_req_o[91] 0 829.115 0.07 829.185
axi_req_o[90] 0 801.675 0.07 801.745
axi_req_o[89] 0 718.235 0.07 718.305
axi_req_o[88] 0 1081.68 0.07 1081.74
axi_req_o[87] 0 1281.59 0.07 1281.67
axi_req_o[86] 0 1116.11 0.07 1116.19
axi_req_o[85] 0 1396.11 0.07 1396.19
axi_req_o[84] 0 621.635 0.07 621.705
axi_req_o[83] 0 1303.44 0.07 1303.51
axi_req_o[82] 0 798.035 0.07 798.105
axi_req_o[81] 0 1087.28 0.07 1087.34
axi_req_o[80] 0 614.355 0.07 614.425
axi_req_o[79] 0 1127.04 0.07 1127.1
axi_req_o[78] 0 901.635 0.07 901.705
axi_req_o[77] 0 700.035 0.07 700.105
axi_req_o[76] 0 1338.16 0.07 1338.22
axi_req_o[75] 0 1014.47 0.07 1014.54
axi_req_o[74] 0 749.035 0.07 749.105
axi_req_o[73] 0 1450.71 0.07 1450.79
axi_req_o[72] 0 1377.92 0.07 1377.98
axi_req_o[71] 0 821.835 0.07 821.905
axi_req_o[70] 0 721.875 0.07 721.945
axi_req_o[69] 0 650.755 0.07 650.825
axi_req_o[68] 0 838.075 0.07 838.145
axi_req_o[67] 0 656.355 0.07 656.425
axi_req_o[66] 0 896.315 0.07 896.385
axi_req_o[65] 0 779.835 0.07 779.905
axi_req_o[64] 0 863.555 0.07 863.625
axi_req_o[63] 0 981.715 0.07 981.785
axi_req_o[62] 0 927.115 0.07 927.185
axi_req_o[61] 0 1270.68 0.07 1270.74
axi_req_o[60] 0 1321.64 0.07 1321.7
axi_req_o[59] 0 841.715 0.07 841.785
axi_req_o[58] 0 628.915 0.07 628.985
axi_req_o[57] 0 1048.92 0.07 1048.98
axi_req_o[56] 0 1388.83 0.07 1388.91
axi_req_o[55] 0 1359.99 0.07 1360.06
axi_req_o[54] 0 1399.76 0.07 1399.82
axi_req_o[53] 0 952.595 0.07 952.665
axi_req_o[52] 0 1430.83 0.07 1430.91
axi_req_o[51] 0 890.715 0.07 890.785
axi_req_o[50] 0 1410.68 0.07 1410.74
axi_req_o[49] 0 1276.28 0.07 1276.34
axi_req_o[48] 0 1218.04 0.07 1218.1
axi_req_o[47] 0 696.395 0.07 696.465
axi_req_o[46] 0 1045.28 0.07 1045.34
axi_req_o[45] 0 754.355 0.07 754.425
axi_req_o[44] 0 1118.07 0.07 1118.15
axi_req_o[43] 0 1401.71 0.07 1401.79
axi_req_o[42] 0 1125.35 0.07 1125.43
axi_req_o[41] 0 1405.35 0.07 1405.43
axi_req_o[40] 0 1403.4 0.07 1403.46
axi_req_o[39] 0 1056.19 0.07 1056.27
axi_req_o[38] 0 925.435 0.07 925.505
axi_req_o[37] 0 1387.16 0.07 1387.22
axi_req_o[36] 0 1445.4 0.07 1445.46
axi_req_o[35] 0 1394.44 0.07 1394.51
axi_req_o[34] 0 1037.99 0.07 1038.06
axi_req_o[33] 0 958.195 0.07 958.265
axi_req_o[32] 0 912.555 0.07 912.625
axi_req_o[31] 0 625.275 0.07 625.345
axi_req_o[30] 0 810.915 0.07 810.985
axi_req_o[29] 0 1350.76 0.07 1350.82
axi_req_o[28] 0 668.955 0.07 669.025
axi_req_o[27] 0 734.475 0.07 734.545
axi_req_o[26] 0 1332.56 0.07 1332.62
axi_req_o[25] 0 1421.59 0.07 1421.67
axi_req_o[24] 0 1472.56 0.07 1472.62
axi_req_o[23] 0 747.075 0.07 747.145
axi_req_o[22] 0 643.475 0.07 643.545
axi_req_o[21] 0 1241.83 0.07 1241.91
axi_req_o[20] 0 1156.16 0.07 1156.22
axi_req_o[19] 0 605.395 0.07 605.465
axi_req_o[18] 0 663.635 0.07 663.705
axi_req_o[17] 0 1330.88 0.07 1330.94
axi_req_o[16] 0 1459.95 0.07 1460.03
axi_req_o[15] 0 1414.31 0.07 1414.39
axi_req_o[14] 0 690.795 0.07 690.865
axi_req_o[13] 0 1292.52 0.07 1292.58
axi_req_o[12] 0 976.395 0.07 976.465
axi_req_o[11] 0 950.915 0.07 950.985
axi_req_o[10] 0 794.395 0.07 794.465
axi_req_o[9] 0 1023.43 0.07 1023.51
axi_req_o[8] 0 647.115 0.07 647.185
axi_req_o[7] 0 774.515 0.07 774.585
axi_req_o[6] 0 687.155 0.07 687.225
axi_req_o[5] 0 1294.47 0.07 1294.55
axi_req_o[4] 0 1290.83 0.07 1290.91
axi_req_o[3] 0 1232.59 0.07 1232.67
axi_req_o[2] 0 907.235 0.07 907.305
axi_req_o[1] 0 772.555 0.07 772.625
axi_req_o[0] 0 1476.19 0.07 1476.27
axi_resp_i[81] 0 719.915 0.07 719.985
axi_resp_i[80] 0 859.915 0.07 859.985
axi_resp_i[79] 0 694.435 0.07 694.505
axi_resp_i[78] 0 1247.16 0.07 1247.22
axi_resp_i[77] 0 1372.59 0.07 1372.67
axi_resp_i[76] 0 834.435 0.07 834.505
axi_resp_i[75] 0 1498.04 0.07 1498.1
axi_resp_i[74] 0 1492.71 0.07 1492.79
axi_resp_i[73] 0 745.395 0.07 745.465
axi_resp_i[72] 0 1374.28 0.07 1374.34
axi_resp_i[71] 0 1054.52 0.07 1054.58
axi_resp_i[70] 0 1052.56 0.07 1052.62
axi_resp_i[69] 0 1007.2 0.07 1007.27
axi_resp_i[68] 0 710.955 0.07 711.025
axi_resp_i[67] 0 1123.4 0.07 1123.46
axi_resp_i[66] 0 1454.35 0.07 1454.43
axi_resp_i[65] 0 929.075 0.07 929.145
axi_resp_i[64] 0 1279.92 0.07 1279.98
axi_resp_i[63] 0 1099.88 0.07 1099.94
axi_resp_i[62] 0 1428.88 0.07 1428.94
axi_resp_i[61] 0 827.155 0.07 827.225
axi_resp_i[60] 0 845.355 0.07 845.425
axi_resp_i[59] 0 879.795 0.07 879.865
axi_resp_i[58] 0 1228.95 0.07 1229.03
axi_resp_i[57] 0 1301.76 0.07 1301.82
axi_resp_i[56] 0 1443.44 0.07 1443.51
axi_resp_i[55] 0 707.315 0.07 707.385
axi_resp_i[54] 0 885.395 0.07 885.465
axi_resp_i[53] 0 823.515 0.07 823.585
axi_resp_i[52] 0 776.195 0.07 776.265
axi_resp_i[51] 0 761.635 0.07 761.705
axi_resp_i[50] 0 1109.11 0.07 1109.19
axi_resp_i[49] 0 1154.47 0.07 1154.55
axi_resp_i[48] 0 725.515 0.07 725.585
axi_resp_i[47] 0 1341.8 0.07 1341.86
axi_resp_i[46] 0 894.355 0.07 894.425
axi_resp_i[45] 0 1176.31 0.07 1176.39
axi_resp_i[44] 0 603.435 0.07 603.505
axi_resp_i[43] 0 905.275 0.07 905.345
axi_resp_i[42] 0 1432.52 0.07 1432.58
axi_resp_i[41] 0 723.555 0.07 723.625
axi_resp_i[40] 0 1094.56 0.07 1094.62
axi_resp_i[39] 0 1070.76 0.07 1070.82
axi_resp_i[38] 0 932.715 0.07 932.785
axi_resp_i[37] 0 1185.28 0.07 1185.34
axi_resp_i[36] 0 1368.95 0.07 1369.03
axi_resp_i[35] 0 936.355 0.07 936.425
axi_resp_i[34] 0 1358.04 0.07 1358.1
axi_resp_i[33] 0 790.755 0.07 790.825
axi_resp_i[32] 0 781.795 0.07 781.865
axi_resp_i[31] 0 1212.71 0.07 1212.79
axi_resp_i[30] 0 1110.8 0.07 1110.86
axi_resp_i[29] 0 783.475 0.07 783.545
axi_resp_i[28] 0 1487.11 0.07 1487.19
axi_resp_i[27] 0 1263.4 0.07 1263.46
axi_resp_i[26] 0 1441.76 0.07 1441.82
axi_resp_i[25] 0 796.355 0.07 796.425
axi_resp_i[24] 0 638.155 0.07 638.225
axi_resp_i[23] 0 1021.76 0.07 1021.83
axi_resp_i[22] 0 1161.76 0.07 1161.82
axi_resp_i[21] 0 1248.83 0.07 1248.91
axi_resp_i[20] 0 1334.52 0.07 1334.58
axi_resp_i[19] 0 1234.56 0.07 1234.62
axi_resp_i[18] 0 757.995 0.07 758.065
axi_resp_i[17] 0 683.515 0.07 683.585
axi_resp_i[16] 0 889.035 0.07 889.105
axi_resp_i[15] 0 756.315 0.07 756.385
axi_resp_i[14] 0 1188.92 0.07 1188.98
axi_resp_i[13] 0 1288.88 0.07 1288.94
axi_resp_i[12] 0 1223.64 0.07 1223.7
axi_resp_i[11] 0 1114.44 0.07 1114.51
axi_resp_i[10] 0 1398.07 0.07 1398.15
axi_resp_i[9] 0 1392.47 0.07 1392.55
axi_resp_i[8] 0 639.835 0.07 639.905
axi_resp_i[7] 0 1227.28 0.07 1227.34
axi_resp_i[6] 0 1043.59 0.07 1043.67
axi_resp_i[5] 0 985.355 0.07 985.425
axi_resp_i[4] 0 1072.71 0.07 1072.79
axi_resp_i[3] 0 878.115 0.07 878.185
axi_resp_i[2] 0 732.515 0.07 732.585
axi_resp_i[1] 0 730.835 0.07 730.905
axi_resp_i[0] 0 678.195 0.07 678.265
CodeElements/Grouping/rtl_mp/ariane.hgr.weight 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
CodeElements/Grouping/setup.tcl 0 → 100644
set design "ariane"
set top_design "ariane"
set netlist "./design/1_synth.v"
set sdc "./design/1_synth.sdc"
# If the netlist is post-synthesis, the def_file is the floorplan_def with placed pins
set def_file "./design/2_floorplan.def"
set ALL_LEFS "
./lefs/NangateOpenCellLibrary.tech.lef
./lefs/NangateOpenCellLibrary.macro.mod.lef
./lefs/fakeram45_256x16.lef
"
set LIB_BC "
./libs/NangateOpenCellLibrary_typical.lib
./libs/fakeram45_256x16.lib
"
set site "FreePDK45_38x28_10R_NP_162NW_34O"
foreach lef_file ${ALL_LEFS} {
read_lef $lef_file
}
foreach lib_file ${LIB_BC} {
read_liberty $lib_file
}
CodeElements/Grouping/utils/extract_hypergraph.tcl 0 → 100644
#######################################################################
### Author: Zhiang, May, 2022
### Uses OpenROAD API to convert the netlist to a hypergraph (in hemtis format)
### This file cannot be used directly. It will be called by
### generate_cluster.py
### All the parameters set here are meaningless.
### !!! Please don't touch this file !!!
########################################################################
read_verilog $netlist
link_design $top_design
read_sdc $sdc
read_def $def_file -floorplan_initialize
#Generate the hypergraph
partition_design -max_num_inst 2000000 -min_num_inst 40000 \
-max_num_macro 12 -min_num_macro 4 \
-net_threshold 20 -virtual_weight 50 \
-num_hop 0 -timing_weight 1000 \
-report_file ${top_design}.hgr
exit
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