Updated Flow scripts for SKY130HD

Signed-off-by: sakundu <sakundu@ucsd.edu>

.gitignore

 Flows/*/*/run/*/
+Flows/*/*/run-*
 Flows/job
 CodeElements/*/*/__pycache__

Flows/SKY130HD/ariane133/scripts/cadence/design_setup.tcl

@@ -3,6 +3,7 @@
 
 set DESIGN ariane 
 set sdc  ../../constraints/${DESIGN}.sdc
+set rtldir ../../rtl
 
 # def file with die size and placed IO pins
 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {

Flows/SKY130HD/ariane136/scripts/cadence/design_setup.tcl

@@ -3,6 +3,7 @@
 
 set DESIGN ariane 
 set sdc  ../../constraints/${DESIGN}.sdc
+set rtldir ../../../../../Testcases/ariane136/rtl
 
 # def file with die size and placed IO pins
 if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {

Flows/SKY130HD/mempool_tile/constraints/mempool_tile_wrap.sdc

@@ -20,7 +20,7 @@ set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
 
 # Create virtual clock.
 create_clock -name "vclk_i" -period $clock_cycle
-set_clock_uncertainty $clk_uncertainty [get_clocks vclk_i]
+set_clock_uncertainty $uncertainty [get_clocks vclk_i]
 set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
 set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
 
@@ -34,22 +34,22 @@ set_max_fanout $maxFanout [current_design]
 set_false_path -from tile_id_i
 
 # TCDM Master
-set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_master_*req_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*req_*"]
+set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_master_*req_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*req_*"]
 
-set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_master_*resp_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*resp_*"]
+set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_master_*resp_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*resp_*"]
 
 # TCDM Slave
-set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_slave_*req_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*req_*"]
+set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_slave_*req_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*req_*"]
 
-set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_slave_*resp_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
+set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_slave_*resp_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*resp_*"]
 
 # Refill port
-set_input_delay  [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ refill_*"] 
-set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ refill_*"]
+#set_input_delay  [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ refill_*"] 
+#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ refill_*"]
 
 # Reset
 set_input_delay  [expr 0.30*$clock_cycle] -clock vclk_i rst_ni

Flows/SKY130HD/nvdla/scripts/cadence/rtl_list.tcl

@@ -371,7 +371,7 @@ nv_ram_rwsthp_80x15.v
 nv_ram_rwsthp_80x17.v
 nv_ram_rwsthp_80x72.v
 nv_ram_rwsthp_80x9.v
-fakeram_256x64_dp.v
+fakeram130_256x64_dp.v
 
 
 -v NV_NVDLA_XXIF_libs.v

Flows/SKY130HD/nvdla/scripts/cadence/run_genus_hybrid.tcl

@@ -54,11 +54,13 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
 # Load Design and Initialize
 #################################################
 set_db init_hdl_search_path $rtldir 
-source rtl_list.tcl
 
-foreach rtl_file $rtl_all {
-    read_hdl -sv $rtl_file
-}
+read_hdl -f rtl_list.tcl
+#source rtl_list.tcl
+#
+#foreach rtl_file $rtl_all {
+#    read_hdl -sv $rtl_file
+#}
 
 elaborate $DESIGN
 time_info Elaboration

Flows/util/genJobList.py

@@ -5,7 +5,7 @@ import re
 import time
 
 testcases = ['ariane136', 'ariane133', 'mempool_tile', 'nvdla']
-enablements = ['NanGate45', 'ASAP7']
+enablements = ['NanGate45', 'ASAP7', 'SKY130HD']
 flows = [1, 2]
 job_file = "all_jobs"