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Merge pull request #21 from TILOS-AI-Institute/flow_scripts 

Flow scripts
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CodeElements/Plc_client/test/ariane133/initial.plc
# Placement file for Circuit Training # Placement file for Circuit Training
# Source input file(s) : environment/test_data/ariane/ariane.txt # Source input file(s) : ./output_ariane_NanGate45/22cols_30rows/g500_ub5_nruns10_c5_r3_v3_rc1/netlist.pb.txt
# This file : environment/test_data/ariane/init.plc # This file : ./output_ariane_NanGate45/22cols_30rows/g500_ub5_nruns10_c5_r3_v3_rc1/initial.plc
# Date : 2022-03-13 09:30:00 # Original initial placement :
# Columns : 50 Rows : 50 # Date : 2022-08-26 08:27:04
# Width : 1599.99 Height : 1598.8 # Columns : 22 Rows : 30
# Area : 1244102.4819999968 # Width : 1357.360 Height : 1356.880
# Wirelength : 0.0 # Area (stdcell+macros) : 1448306.937872215
# Wirelength cost : 0.0 # Wirelength : 3264054.817
# Congestion cost : 0.0 # Wirelength cost : 0.0540
# Block : ariane # Congestion cost : 0.8487
# Routes per micron, hor : 70.33 ver : 74.51 # Density cost : 0.6405
# Routes used by macros, hor : 51.79 ver : 51.79 # Fake net cost : 0.0000
# Smoothing factor : 2 # 90% Congestion metric: (0.01363636363636364, 0.0006827604141139862)
# Overlap threshold : 0.004 # Project : unset_project
#s # Block : unset_block
# Routes per micron, hor : 11.285 ver : 12.605
# Routes used by macros, hor : 7.143 ver : 8.339
# Smoothing factor : 0
# Use incremental cost : False
#
# To view this file (most options are default):
# viewer_binary --netlist_file ./output_ariane_NanGate45/22cols_30rows/g500_ub5_nruns10_c5_r3_v3_rc1/netlist.pb.txt --canvas_width 1357.36 --canvas_height 1356.88 --grid_cols 22 --grid_rows=30 --init_placement ./output_ariane_NanGate45/22cols_30rows/g500_ub5_nruns10_c5_r3_v3_rc1/initial.plc --project unset_project --block_name unset_block --congestion_smooth_range 0 --overlap_threshold 0 --noboundary_check
# or you can simply run:
# viewer_binary --init_placement ./output_ariane_NanGate45/22cols_30rows/g500_ub5_nruns10_c5_r3_v3_rc1/initial.plc
#
# #
# #
# Counts of node types: # Counts of node types:
# HARD_MACROs : 133 # HARD_MACROs : 133
# HARD_MACRO_PINs : 7847 # HARD_MACRO_PINs : 7847
# MACROs : 662 # MACROs : 935
# MACRO_PINs : 24487 # MACRO_PINs : 18475
# PORTs : 495 # PORTs : 495
# SOFT_MACROs : 529 # SOFT_MACROs : 802
# SOFT_MACRO_PINs : 16640 # SOFT_MACRO_PINs : 10628
# STDCELLs : 0 # STDCELLs : 0
# #
# Hard Macro Placements:
0 0.035 874.23 - 1 # |0|0|0|0|0|0|0|0|0|0|1|1|1|1|1|1|1|1|1|1|2|2|
1 0.035 903.21 - 1 # |0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|
2 0.035 873.81 - 1 # ---------------------------------------------
3 0.035 873.39 - 1 # 29|5|5|5|5|5|5|5|5|5|5|6|5|5|5|4|1|3|5|4|4|4|4|
4 0.035 872.97 - 1 # 28|8|8|8|8|8|8|8|8|8|8|9|8|8|8|8|3|4|8|8|8|8|8|
5 0.035 872.55 - 1 # 27|8|8|8|8|8|8|8|8|8|8|9|8|8|8|8|3|4|8|8|8|8|8|
6 0.035 872.13 - 1 # 26|5|4|5|5|5|5|6|6|6|6|7|6|6|5|5|5|3|2|3|4|6|3|
7 0.035 871.71 - 1 # 25|8|8|8|8|8|8|8|8|8|8|9|8|8|8|8|8|4|2|7|7|8| |
8 0.035 871.29 - 1 # 24|8|8|8|8|8|8|8|8|8|8|9|8|8|8|8|8|4|2|8|8|8| |
9 0.035 870.87 - 1 # 23|6|5|4|4|4|5|5|5|4|5|6|6|5|6|5|6|4|4|8|7|5|1|
10 0.035 870.45 - 1 # 22|8| |7|4|6|8|8|8|8|8|8|9|8|8|7|7|8|5|1|1| |8|
11 0.035 870.03 - 1 # 21|8| |7|8|8|8|8|8|8|8|8|9|8|8|8|7|8|5|2|8|8|8|
12 0.035 869.61 - 1 # 20|6| |6|8|7|6|5|6|7|6|6|6|6|6|8|6|6|4|3|8|8|6|
13 0.035 869.19 - 1 # 19|8|7|1|3|1| | |1|4|7|7|8|8|7|6|7|8|8|7|6|8|8|
14 0.035 868.77 - 1 # 18|8|8|2| | | | |3|8|8|8|8|9|8|8|7|8|8|6|3|2|8|
15 0.035 868.35 - 1 # 17|7|8|2| | | | |3|8|8|8|8|9|8|8|6|6|6|7|8|8|8|
16 0.035 867.93 - 1 # 16| | | | | | | |1|5|5|1|3|6|6|6|7|8|8|8|8|8|6|
17 0.035 867.51 - 1 # 15| | | | | | | | |2|8|8|9|9|8|7|8|8|8|6|4|6|8|
18 0.035 867.09 - 1 # 14| | | | | | | | |2|8|8|9|9|8|7|7|7|7|7|5|4|8|
19 0.035 866.67 - 1 # 13| | | | | | | | | |2|6|6|6|6|6|4|5|7|7|8|8|6|
20 0.035 866.25 - 1 # 12| | | | | | | | | | |8|9|8|8|8|8|8|8|8|8|8|8|
21 0.035 865.83 - 1 # 11| | | | | | | | | | |8|9|8|8|8|8|8|8|6|2|4|8|
22 0.035 865.41 - 1 # 10| | | | | | | | | | |7|6|4|6|6|6|4|4|6|7|6|6|
23 0.035 864.99 - 1 # 9| | | | | | |1|5|5|5|6|7|8|8|8|8|8|8|8|8|8|8|
24 0.035 864.57 - 1 # 8| | | | | | |3|8|8|8|8|9|8|8|8|8|8|8|8|8|8|8|
25 0.035 864.15 - 1 # 7| | | | | | |3|8|8|8|8|9|7|4|5|6|6|5|2| |2|6|
26 0.035 863.73 - 1 # 6| | | | | | |1|3|5|6|6|5|6|7|6|7|7|7|8|8|8|8|
27 0.035 863.31 - 1 # 5| | | | | | | |2|8|8|8|9|8|8|8|8|8|8|8|8|8|8|
28 0.035 862.89 - 1 # 4| | | | | | | |2|8|8|8|9|8|8|8|7|8|7|6|7|7|5|
29 0.035 862.47 - 1 # 3| | | | | |1|2|3|6|5|5|6|4|3|4|3|3|3|3|3|3|3|
30 0.035 862.05 - 1 # 2| | | | | |4|8|8|8|8|8|9|8|8|8|8|8|8|8|8|8|8|
31 0.035 861.63 - 1 # 1| | | | | |4|8|8|8|8|8|9|8|8|8|8|8|8|8|8|8|8|
32 0.035 861.21 - 1 # 0| | | | | |3|5|5|5|5|6|6|5|5|4|4|4|4|4|4|4|4|
33 0.035 860.79 - 1 # ---------------------------------------------
34 0.035 860.37 - 1 #
35 0.035 859.95 - 1 # Overall Placement Density:
36 0.035 859.53 - 1 # |0|0|0|0|0|0|0|0|0|0|1|1|1|1|1|1|1|1|1|1|2|2|
37 0.035 859.11 - 1 # |0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|
38 0.035 858.69 - 1 # ---------------------------------------------
39 0.035 858.27 - 1 # 29|5|5|5|5|5|5|5|5|5|5|6|5|5|5|4|1|3|5|4|4|4|4|
40 0.035 857.85 - 1 # 28|8|8|8|8|8|8|8|8|8|8|9|8|8|8|8|3|4|8|8|8|8|8|
41 0.035 857.43 - 1 # 27|8|8|8|8|8|8|8|8|8|8|9|8|8|8|8|3|4|8|8|8|8|8|
42 0.035 857.01 - 1 # 26|5|4|5|5|5|5|6|6|6|6|7|6|6|5|5|5|3|2|3|4|6|3|
43 0.035 856.59 - 1 # 25|8|8|8|8|8|8|8|8|8|8|9|8|8|8|8|8|4|2|7|7|8| |
44 0.035 856.17 - 1 # 24|8|8|8|8|8|8|8|8|8|8|9|8|8|8|9|8|4|2|8|8|8| |
45 0.035 855.75 - 1 # 23|6|5|5|6|5|5|5|5|4|5|6|6|5|6|6|6|4|4|8|8|5|1|
46 0.035 855.33 - 1 # 22|8| |8|5|7|8|8|8|8|8|8|9|8|8|8|8|8|5|1|2|1|8|
47 0.035 854.91 - 1 # 21|8|1|7|8|9|8|8|9|9|8|8|9|8|8|9|7|8|5|2|8|8|8|
48 0.035 854.49 - 1 # 20|6| |6|8|8|8|6|7|7|6|6|6|6|6|8|6|6|4|3|8|8|6|
49 0.035 854.07 - 1 # 19|8|7|5|8|6|6|8|5|4|7|7|8|8|7|7|7|8|8|8|7|8|8|
50 0.035 853.65 - 1 # 18|8|8|6|#|7|7|4|9|8|8|8|8|9|8|8|7|8|8|6|3|2|8|
51 0.035 853.23 - 1 # 17|7|8|8|!|#|9|!|!|#|8|9|9|9|8|8|6|6|6|7|8|8|8|
52 0.035 852.81 - 1 # 16|5|8|#|#|8|#|!|9|5|6|5|4|6|6|6|7|8|8|8|8|8|6|
53 0.035 852.39 - 1 # 15|9|!|7|8|!|7|#|!|#|8|8|9|9|8|7|8|8|8|6|4|6|8|
54 0.035 851.97 - 1 # 14|7|#|6|4|4|6|8|#|!|8|8|9|9|8|7|7|7|7|7|5|4|8|
55 0.035 851.55 - 1 # 13|#|!|8|!|!|8|!|!|#|#|7|6|6|6|6|7|8|7|7|8|8|6|
56 0.035 851.13 - 1 # 12|9|!|9|6|7|6|!|!|!|7|9|9|8|8|8|8|8|8|8|8|8|8|
57 0.035 850.71 - 1 # 11|5|9|7|6|7|8|7|8|!|!|9|9|8|8|8|8|!|8|6|2|4|8|
58 0.035 850.29 - 1 # 10|8|8|6|8|!|#|#|!|!|!|9|6|4|6|6|6|5|6|7|7|6|6|
59 0.035 849.87 - 1 # 9|5|7|5|7|!|9|8|5|6|6|6|7|9|8|8|8|8|8|8|8|8|8|
60 0.035 849.45 - 1 # 8|!|!|!|!|9|!|8|8|8|8|8|9|8|8|8|8|8|8|8|8|8|8|
61 0.035 849.03 - 1 # 7|9|8|8|6|!|9|6|8|8|8|9|9|7|5|6|6|6|6|3|1|2|6|
62 0.035 848.61 - 1 # 6|!|!|!|!|9|!|#|7|5|6|7|5|6|7|6|7|7|7|8|8|8|8|
63 0.035 848.19 - 1 # 5|4|7|6|9|!|#|#|8|8|8|8|9|8|8|8|8|8|8|8|8|8|8|
64 0.035 847.77 - 1 # 4| |9|!|!|!|!|9|8|8|8|8|9|#|8|8|7|8|7|6|7|7|5|
65 0.035 847.35 - 1 # 3|9|!|!|9|#|7|7|6|6|6|6|6|5|3|4|3|3|3|3|3|3|3|
66 0.035 901.53 - 1 # 2|2|8|!|!|!|8|8|8|8|8|8|9|8|8|8|8|8|8|8|8|8|8|
67 0.035 901.11 - 1 # 1|5|!|!|!|!|9|8|8|8|8|8|9|8|8|8|8|8|8|8|8|8|8|
68 0.035 900.69 - 1 # 0| |9|!|#|#|3|5|5|5|5|6|6|5|5|4|4|4|4|4|4|4|4|
69 0.035 900.27 - 1 # ---------------------------------------------
70 0.035 899.85 - 1 #
71 0.035 899.43 - 1 # Horizontal Routing Congestion:
72 0.035 899.01 - 1 # |0|0|0|0|0|0|0|0|0|0|1|1|1|1|1|1|1|1|1|1|2|2|
73 0.035 898.59 - 1 # |0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|
74 0.035 898.17 - 1 # ---------------------------------------------
75 0.035 897.75 - 1 # 29|4|4|4|4|4|4|4|4|4| |4|4|4|4|3| |4|3|3|3|3| |
76 0.035 897.33 - 1 # 28|6|6|6|6|6|6|6|6|6| |6|6|6|6|6| |6|6|6|6|6| |
77 0.035 896.91 - 1 # 27|6|6|6|6|6|6|6|6|6| |6|6|6|6|6| |6|6|6|6|6| |
78 0.035 896.49 - 1 # 26|4|3|4|4|4|4|4|4|4| |4|4|4|3|4|3|1|2|2|4|2| |
79 0.035 896.07 - 1 # 25|6|6|6|6|6|6|6|6|6| |6|6|6|6|6|6| |5|5|6| | |
80 0.035 895.65 - 1 # 24|6|6|6|6|6|6|6|6|7| |6|7|9|#|7|6| |6|6|6| | |
81 0.035 895.23 - 1 # 23|5|5|6|7|4|5|4|3|4|1|3|4|5|5|5|5|2|6|7|4| | |
82 0.035 894.81 - 1 # 22|6|2|9|5|8|7|8|7|6|7| |6|6|7|8|7|6| |1| |6| |
83 0.035 894.39 - 1 # 21|7| |7|8|8|7|9|#|9|8|1|7|7|9|9|7|6| |6|6|6| |
84 0.035 893.97 - 1 # 20|5| |6|7|7|6|5|6|5|5| |5|5|6|7|5|5|1|6|7|4| |
85 0.035 893.55 - 1 # 19|6|6|1|4|1|2|4|5|7|7|7|1|6|6|5|6|7|7|6|6|6| |
86 0.035 893.13 - 1 # 18|6|7|2|3|2|3|2|8|8|8|7|1|7|7|6|6|6|7|3|1|6| |
87 0.035 892.71 - 1 # 17|5|6|5|7|3|2|1|7|9|9|8|2|8|7|6|5|5|5|6|6|6| |
88 0.035 892.29 - 1 # 16|1| |1|1|2|1|1|5|7|7|6|3|7|6|6|6|6|6|7|6|5| |
89 0.035 891.87 - 1 # 15|3| |2|4|4|1|2|1|6|6|7| |6|6|6|6|6|6|3|4|6| |
90 0.035 891.45 - 1 # 14|3|2|1|1|1|1|1|1|6|6|7| |6|6|7|6|5|5|4|3|6| |
91 0.035 891.03 - 1 # 13|2|4|4|4|2|1|1| |2|5|3|2|5|5|5|3|5|5|6|6|4| |
92 0.035 890.61 - 1 # 12|2|3|3|1|1|1|2|2|1|6| |6|6|6|6|6|6|6|6|6|6| |
93 0.035 890.19 - 1 # 11|5|2|5|5|4|2|4|3|3|9|2|9|7|7|7|7|6|6|1|3|6| |
94 0.035 889.77 - 1 # 10|4|4|7|5|5|2|3|7|5|#|3|8|5|6|6|6|2|5|7|5|4| |
95 0.035 889.35 - 1 # 9|1|3|5|5|4|1|4|4|4|4| |5|8|8|7|6|6|7|7|6|6| |
96 0.035 888.93 - 1 # 8|3|5|7|3|3|2|7|6|6|6| |6|6|7|6|6|6|6|6|6|6| |
97 0.035 888.51 - 1 # 7|2|2|2|2|4|1|6|6|6|7|1|7|5|3|5|5|4|3|3|2|4| |
98 0.035 888.09 - 1 # 6|1|1|2|2|2|2|4|5|6|5| |4|4|6|4|6|5|6|6|6|6| |
99 0.035 887.67 - 1 # 5| |3|2|2|2|2|1|7|7|7| |6|6|6|6|6|6|6|6|6|6| |
100 0.035 887.25 - 1 # 4| |1|2|2|1|1|2|9|7|8|2|9|9|8|7|6|6|4|5|5|4| |
101 0.035 886.83 - 1 # 3|1|2|1| | |2|2|6|5|8|3|7|5|3|4|2|2|2|2|2|2| |
102 0.035 886.41 - 1 # 2| |1|2|3|1|6|6|6|6|6| |6|6|6|6|6|6|6|6|6|6| |
103 0.035 885.99 - 1 # 1|1|3|2|2|1|6|6|6|6|6| |6|7|7|6|6|6|6|6|6|6| |
104 0.035 885.57 - 1 # 0| | |1|1| |4|4|4|4|4| |4|4|3|3|3|3|3|3|3|3| |
105 0.035 885.15 - 1 # ---------------------------------------------
106 0.035 884.73 - 1 #
107 0.035 884.31 - 1 # Vertical Routing Congestion:
108 0.035 883.89 - 1 # |0|0|0|0|0|0|0|0|0|0|1|1|1|1|1|1|1|1|1|1|2|2|
109 0.035 883.47 - 1 # |0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|
110 0.035 883.05 - 1 # ---------------------------------------------
111 0.035 882.63 - 1 # 29| | | | | | | | | | | | | | | | | | | | | | |
112 0.035 882.21 - 1 # 28|5|5|5|5|5|5|5|5|5|5|6|5|5|5|5|2|3|5|5|5|5|5|
113 0.035 881.79 - 1 # 27|5|5|5|6|5|5|5|5|5|5|6|6|5|5|5|2|3|5|5|6|5|5|
114 0.035 881.37 - 1 # 26|5|5|6|6|6|5|6|6|6|5|6|6|6|5|6|2|3|5|5|6|5|5|
115 0.035 880.95 - 1 # 25|5|5|6|6|6|6|6|6|6|5|6|6|6|5|6|5|3| | |1|5| |
116 0.035 880.53 - 1 # 24|6|5|6|6|6|6|6|6|6|5|6|6|6|6|6|6|3|2|5|6|5| |
117 0.035 880.11 - 1 # 23|6|5|7|7|7|6|6|6|7|5|6|6|5|6|8|6|3|2|6|7|5| |
118 0.035 879.69 - 1 # 22|6| |6|3|6|6|6|6|6|5|6|6|5|6|3|5|5|5|6|5| |5|
119 0.035 879.27 - 1 # 21|6|1|5|6|8|6|6|7|7|5|6|6|5|6|8|7|5|3|2|5|1|5|
120 0.035 878.85 - 1 # 20|5|1|5|6|7|7|6|9|7|5|5|6|5|5|7|6|5|3|3|6|6|5|
121 0.035 878.43 - 1 # 19|5|1| |4|3|1|1|3|1| | | | | |6|6|5|5|6|7|5| |
122 0.035 878.01 - 1 # 18|5|6|3|1|1|2|2|5|6|5|5|6|6|5|6|6|5|5|5|1|1|5|
123 0.035 877.59 - 1 # 17|5|5|4|2|3|2|2|5|6|6|7|6|6|5|6|5|5|5|7|6|5|5|
124 0.035 877.17 - 1 # 16| |5|2|1|2|2|1|5|6|6|9|5|6|5|5|5|5|5|7|6|5| |
125 0.035 876.75 - 1 # 15|2|3|2|3|3|3|1|2|2|6|7|5|6|5|5|6|5|5|6|5|6|5|
126 0.035 876.33 - 1 # 14|4|5|1|3|2|2|2|2|2|6|7|5|6|5|5|5|5|5|4| | |5|
127 0.035 875.91 - 1 # 13|6|7|2|3|2|2|3|2|2|6|6|5|6|5|5|1| | |2|5|5|5|
128 0.035 875.49 - 1 # 12|4|7|3|5|4|4|3|2|1|1|6|6|5|5|5|5|5|5|6|6|5|5|
129 0.035 875.07 - 1 # 11|4|4|4|4|4|3|3|3|2|2|6|6|6|5|5|5|6|6|6|6|5|5|
130 0.035 902.79 - 1 # 10|2|4|4|5|4|2|2|4|2|1|6|6|6|6|5|6|6|6|5| |1|5|
131 0.035 902.37 - 1 # 9|1|3|2|5|5|3|2|2|1|1|1| |6|5|5|5|5|5|7|6|5|5|
132 0.035 901.95 - 1 # 8|1|2|3|6|4|2|3|7|6|7|7|6|6|5|6|5|5|5|7|6|5|5|
133 0.035 903.63 - 1 # 7|2|3|5|4|3|2|3|7|6|7|7|6|6|6|5|6|5|5|5|1|5|5|
134 0.035 874.65 - 1 # 6|1|2|4|3|2|2|4|8|6|6|6|6| | | |3|2|2|7|7|6|5|
135 0.035 780.15 - 1 # 5|1|2|2|2|1|1|1|4|6|6|6|6|6|5|5|5|5|5|7|6|5|5|
136 0.035 733.53 - 1 # 4| |1|2|2|1|1| |3|6|6|6|7|7|5|5|5|5|5|6|6|5|5|
137 0.035 731.85 - 1 # 3| | |1| |1|1|1|4|6|6|6|6|7|5|5|1|3|2|1| | | |
138 0.035 731.43 - 1 # 2| |1|2|1|1|3|5|6|6|5|6|6|6|5|5|5|5|5|6|6|5|5|
139 0.035 731.01 - 1 # 1| |1|2|1|1|3|5|6|6|5|6|6|6|5|5|5|5|5|6|5|5|5|
140 0.035 730.59 - 1 # 0| | |1| | |2|5|5|5|5|5|6|5|5|5|5|5|5|5|5|5|5|
141 0.035 730.17 - 1 # ---------------------------------------------
142 0.035 729.75 - 1 #
143 0.035 729.33 - 1 # User comments:
144 0.035 728.91 - 1 # Original source netlist with standard cells: /home/zf4_projects/DREAMPlace/sakundu/ABK_MP/08162022_flow_scripts/MacroPlacement/Flows/NanGate45/ariane133/run-20220816-035413/flow2_68/ariane.pb.txt
145 0.035 728.49 - 1 # Groups file: ./output_ariane_NanGate45/22cols_30rows/g500_ub5_nruns10_c5_r3_v3_rc1/groups.final
146 0.035 728.07 - 1 # worst 10 spread
147 0.035 727.65 - 1 # grp: 399 - spread: 157719.59006495326
148 0.035 721.77 - 1 # grp: 643 - spread: 145040.33710442024
149 0.035 721.35 - 1 # grp: 300 - spread: 133290.39404356093
150 0.035 720.93 - 1 # grp: 585 - spread: 132823.85964308356
151 0.035 720.51 - 1 # grp: 371 - spread: 130724.32054491894
152 0.035 727.23 - 1 # grp: 45 - spread: 128019.20568798434
153 0.035 720.09 - 1 # grp: 393 - spread: 120621.34756839756
154 0.035 719.67 - 1 # grp: 656 - spread: 120517.1573639346
155 0.035 733.11 - 1 # grp: 633 - spread: 109915.3661602272
156 0.035 732.69 - 1 # grp: 513 - spread: 100384.88193357224
157 0.035 732.27 - 1 #
158 0.035 726.81 - 1 #
159 0.035 726.39 - 1 # node_index x y orientation fixed
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555 495.805 1354.67 N 0 336 0.07 269.71 - 1
615 557.305 1354.67 N 0 337 0.07 275.03 - 1
675 616.935 1354.67 N 0 338 0.07 280.35 - 1
735 676.565 1354.67 N 0 339 0.07 285.67 - 1
795 436.175 1489.54 N 0 340 0.07 291.27 - 1
855 436.175 1549.17 N 0 341 0.07 296.59 - 1
915 436.175 1608.8 N 0 342 0.07 301.91 - 1
975 569.175 1489.54 N 0 343 0.07 307.23 - 1
1035 569.175 1549.17 N 0 344 0.07 312.55 - 1
1095 569.175 1608.8 N 0 345 0.07 318.15 - 1
1155 736.195 1354.67 N 0 346 0.07 323.47 - 1
1215 795.825 1354.67 N 0 347 0.07 328.79 - 1
1275 855.455 1354.67 N 0 348 0.07 334.11 - 1
1335 915.085 1354.67 N 0 349 0.07 339.43 - 1
1395 974.715 1354.67 N 0 350 0.07 345.03 - 1
1455 734.325 1489.54 N 0 351 0.07 350.35 - 1
1515 734.325 1549.17 N 0 352 0.07 355.67 - 1
1575 734.325 1608.8 N 0 353 0.07 360.99 - 1
1635 867.325 1489.54 N 0 354 0.07 366.31 - 1
1695 867.325 1549.17 N 0 355 0.07 371.91 - 1
1755 867.325 1608.8 N 0 356 0.07 377.23 - 1
1815 1034.345 1354.67 N 0 357 0.07 382.55 - 1
1875 1093.975 1354.67 N 0 358 0.07 387.87 - 1
1935 1153.605 1354.67 N 0 359 0.07 393.19 - 1
1995 1213.235 1354.67 N 0 360 0.07 398.79 - 1
2055 1272.865 1354.67 N 0 361 0.07 404.11 - 1
2115 1032.475 1489.54 N 0 362 0.07 409.43 - 1
2175 1032.475 1549.17 N 0 363 0.07 414.75 - 1
2235 1032.475 1608.8 N 0 364 0.07 420.07 - 1
2295 1165.475 1489.54 N 0 365 0.07 425.67 - 1
2355 1165.475 1549.17 N 0 366 0.07 430.99 - 1
2415 1165.475 1608.8 N 0 367 0.07 436.31 - 1
2475 1332.495 1354.67 N 0 368 0.07 441.63 - 1
2535 1392.125 1354.67 N 0 369 0.07 446.95 - 1
2595 1451.755 1354.67 N 0 370 0.07 452.55 - 1
2655 1511.385 1354.67 N 0 371 0.07 457.87 - 1
2715 1571.015 1354.67 N 0 372 0.07 463.19 - 1
2775 1330.625 1489.54 N 0 373 0.07 468.51 - 1
2835 1330.625 1549.17 N 0 374 0.07 473.83 - 1
2895 1330.625 1608.8 N 0 375 0.07 479.43 - 1
2955 1463.625 1489.54 N 0 376 0.07 484.75 - 1
3015 1463.625 1549.17 N 0 377 0.07 490.07 - 1
3075 1463.625 1608.8 N 0 378 0.07 495.39 - 1
3135 32.775 66.5 N 0 379 0.07 500.71 - 1
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3315 165.775 126.13 N 0 382 0.07 516.95 - 1
3375 298.775 66.5 N 0 383 0.07 522.27 - 1
3435 32.775 185.76 N 0 384 0.07 527.59 - 1
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3615 32.775 245.39 N 0 387 0.07 543.83 - 1
3675 165.775 245.39 N 0 388 0.07 549.15 - 1
3735 298.775 245.39 N 0 389 0.07 554.47 - 1
3795 32.775 305.02 N 0 390 0.07 560.07 - 1
3855 32.775 364.65 N 0 391 0.07 565.39 - 1
3915 165.775 305.02 N 0 392 0.07 570.71 - 1
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4035 298.775 305.02 N 0 394 0.07 581.35 - 1
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4815 564.775 185.76 N 0 407 0.07 651.35 - 1
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5415 431.775 424.28 N 0 417 0.07 705.11 - 1
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5535 697.775 424.28 N 0 419 0.07 715.75 - 1
5595 431.775 483.91 N 0 420 0.07 721.35 - 1
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5775 830.775 66.5 N 0 423 0.07 737.31 - 1
5835 830.775 126.13 N 0 424 0.07 742.63 - 1
5895 963.775 66.5 N 0 425 0.07 748.23 - 1
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6015 1096.775 66.5 N 0 427 0.07 758.87 - 1
6075 830.775 185.76 N 0 428 0.07 764.19 - 1
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6435 830.775 305.02 N 0 434 0.07 796.39 - 1
6495 830.775 364.65 N 0 435 0.07 801.99 - 1
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6735 830.775 424.28 N 0 439 0.07 823.27 - 1
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6855 1096.775 424.28 N 0 441 0.07 834.19 - 1
6915 830.775 483.91 N 0 442 0.07 839.51 - 1
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7035 1096.775 483.91 N 0 444 0.07 850.15 - 1
7095 1229.775 66.5 N 0 445 0.07 855.75 - 1
7155 1229.775 126.13 N 0 446 0.07 861.07 - 1
7215 1362.775 66.5 N 0 447 0.07 866.39 - 1
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7335 1495.775 66.5 N 0 449 0.07 877.03 - 1
7395 1229.775 185.76 N 0 450 0.07 882.63 - 1
7455 1362.775 185.76 N 0 451 0.07 887.95 - 1
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7575 1229.775 245.39 N 0 453 0.07 898.59 - 1
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7815 1362.775 305.02 N 0 457 0.07 920.15 - 1
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7935 1229.775 364.65 N 0 459 0.07 930.79 - 1
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8115 1229.775 424.28 N 0 462 0.07 947.03 - 1
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8475 564.775 865.2 N 0 468 0.07 979.23 - 1
8697 829.445 793.8 N 0 469 0.07 984.55 - 1
8701 538.175 798.7 N 0 470 0.07 990.15 - 1
8757 841.225 812.7 N 0 471 0.07 995.47 - 1
8761 751.83 844.2 N 0 472 0.07 1000.79 - 1
8774 732.925 802.9 N 0 473 0.07 1006.11 - 1
8785 734.825 859.6 N 0 474 0.07 1011.43 - 1
8796 758.955 852.6 N 0 475 0.07 1017.03 - 1
8809 841.89 804.3 N 0 476 0.07 1022.35 - 1
8814 634.885 802.2 N 0 477 0.07 1027.67 - 1
8834 745.085 803.6 N 0 478 0.07 1032.99 - 1
8846 703.665 782.6 N 0 479 0.07 1038.31 - 1
8851 756.77 802.2 N 0 480 0.07 1043.91 - 1
8863 770.07 804.3 N 0 481 0.07 1049.23 - 1
8876 693.215 799.4 N 0 482 0.07 1054.55 - 1
8890 679.63 924.7 N 0 483 0.07 1059.87 - 1
8904 683.335 919.1 N 0 484 0.07 1065.19 - 1
8917 681.34 923.3 N 0 485 0.07 1070.79 - 1
8939 680.675 931.0 N 0 486 0.07 1076.11 - 1
8962 650.845 930.3 N 0 487 0.07 1081.43 - 1
8978 650.94 940.8 N 0 488 0.07 1086.75 - 1
8993 677.255 924.0 N 0 489 0.07 1092.07 - 1
9012 677.73 929.6 N 0 490 0.07 1097.67 - 1
9033 711.55 917.0 N 0 491 0.07 1102.99 - 1
9057 704.045 908.6 N 0 492 0.07 1108.31 - 1
9077 697.775 928.2 N 0 493 0.07 1113.63 - 1
9092 697.585 928.2 N 0 494 0.07 1119.23 - 1
9106 704.71 914.2 N 0 495 1115.53 846.54 N 0
9128 708.51 884.8 N 0 555 1183.09 600.14 N 0
9144 699.485 934.5 N 0 615 1183.09 766.54 N 0
9157 699.295 932.4 N 0 675 1115.53 559.54 N 0
9172 645.905 874.3 N 0 735 1250.73 1267.74 N 0
9241 840.845 857.5 N 0 795 1250.73 88.94 N 0
9246 778.81 865.9 N 0 855 1318.38 836.74 N 0
9258 610.47 854.0 N 0 915 1183.09 88.94 N 0
9271 443.175 889.7 N 0 975 709.615 532.94 N 0
9287 514.33 807.1 N 0 1035 912.535 394.34 N 0
9315 701.48 826.0 N 0 1095 1047.89 559.54 N 0
9320 521.835 905.8 N 0 1155 1183.17 937.54 N 0
9339 612.655 861.0 N 0 1215 1318.38 549.74 N 0
9350 463.03 874.3 N 0 1275 1318.38 693.74 N 0
9368 611.515 854.0 N 0 1335 1250.73 587.54 N 0
9381 448.495 889.0 N 0 1395 1318.38 1267.74 N 0
9396 577.22 853.3 N 0 1455 1318.38 88.94 N 0
9409 611.325 849.1 N 0 1515 1318.38 980.74 N 0
9421 527.915 830.9 N 0 1575 1115.53 88.94 S 0
9443 640.775 852.6 N 0 1635 912.535 538.54 N 0
9454 750.595 859.6 N 0 1695 844.965 402.74 N 0
9464 739.86 860.3 N 0 1755 980.175 539.94 N 0
9474 589.95 823.2 N 0 1815 1250.73 926.34 N 0
9488 643.15 800.8 N 0 1875 1318.38 405.54 N 0
9517 596.79 820.4 N 0 1935 1250.73 756.74 N 0
9553 758.195 867.3 N 0 1995 1250.73 419.54 N 0
9564 780.14 847.0 N 0 2055 1183.17 1267.74 S 0
9574 739.955 868.0 N 0 2115 1318.38 261.14 N 0
9584 763.23 871.5 N 0 2175 1256.44 1123.74 N 0
9594 747.08 858.2 N 0 2235 1115.53 258.34 S 0
9603 593.94 818.3 N 0 2295 777.255 546.94 N 0
9640 490.485 897.4 N 0 2355 777.255 390.14 N 0
9656 589.19 872.2 N 0 2415 844.965 546.94 N 0
9669 612.275 861.7 N 0 2475 1047.89 846.54 N 0
9683 549.1 907.2 N 0 2535 1183.09 429.34 N 0
9701 644.765 865.2 N 0 2595 1115.53 703.54 S 0
9887 539.695 846.3 N 0 2655 1115.53 415.34 N 0
9902 579.12 930.3 N 0 2715 1188.8 1102.74 N 0
9949 591.375 880.6 N 0 2775 1250.73 252.74 N 0
9995 564.68 912.8 N 0 2835 1121.22 1102.74 N 0
10095 520.505 894.6 N 0 2895 1183.09 252.74 N 0
10141 567.435 843.5 N 0 2955 642.045 523.14 N 0
10230 606.385 894.6 N 0 3015 980.175 395.74 N 0
10244 610.47 922.6 N 0 3075 1047.81 395.74 N 0
10296 583.585 831.6 N 0 3135 168.565 975.14 S 0
10332 607.05 848.4 N 0 3195 777.325 983.54 S 0
10351 594.13 905.8 N 0 3255 637.485 835.34 N 0
10364 589.57 931.0 N 0 3315 506.695 976.54 N 0
10386 581.97 906.5 N 0 3375 236.205 945.74 S 0
10399 564.3 882.0 N 0 3435 844.895 978.14 N 0
10416 602.11 771.4 N 0 3495 570.605 686.74 S 0
10494 612.275 823.9 N 0 3555 580.035 1130.74 N 0
10640 572.66 737.8 N 0 3615 506.765 371.94 N 0
10648 564.775 837.2 N 0 3675 642.045 371.94 N 0
10795 610.185 731.5 N 0 3735 642.045 80.54 S 0
10918 613.7 765.1 N 0 3795 371.415 984.94 N 0
10994 588.525 821.1 N 0 3855 1053.52 990.54 N 0
11146 682.48 741.3 N 0 3915 1047.89 703.54 N 0
11287 614.46 682.5 N 0 3975 439.125 984.94 S 0
11297 617.5 682.5 N 0 4035 174.265 1127.94 N 0
11307 620.92 672.7 N 0 4095 783.025 1274.94 N 0
11317 618.355 667.8 N 0 4155 705.815 676.94 N 0
11327 616.17 752.5 N 0 4215 512.395 1274.94 N 0
11424 613.89 688.1 N 0 4275 506.765 80.54 S 0
11430 708.32 692.3 N 0 4335 912.535 84.94 N 0
11506 712.5 665.0 N 0 4395 1047.81 84.94 N 0
11582 333.45 847.0 N 0 4455 303.775 975.14 N 0
11638 512.81 829.5 N 0 4515 985.875 990.54 N 0
11679 481.65 884.1 N 0 4575 908.735 825.54 N 0
11725 325.375 902.3 N 0 4635 444.825 1130.74 N 0
11762 333.83 841.4 N 0 4695 106.625 1122.34 N 0
11830 517.18 835.1 N 0 4755 715.315 1274.94 N 0
11878 512.525 891.1 N 0 4815 773.455 690.94 N 0
11978 512.05 784.7 N 0 4875 580.035 1274.94 N 0
12064 564.87 928.9 N 0 4935 574.335 80.54 N 0
12079 582.35 837.2 N 0 4995 709.615 228.94 N 0
12097 577.22 878.5 N 0 5055 980.175 84.94 N 0
12146 583.11 859.6 N 0 5115 174.265 1274.94 N 0
12163 405.08 838.6 N 0 5175 1115.45 1267.74 N 0
12176 452.865 869.4 N 0 5235 980.175 703.54 N 0
12219 479.085 847.0 N 0 5295 309.475 1274.94 N 0
12232 477.09 844.2 N 0 5355 106.625 1274.94 S 0
12242 530.005 879.9 N 0 5415 918.235 1266.54 N 0
12252 522.69 999.6 N 0 5475 638.245 667.14 S 0
12341 511.765 930.3 N 0 5535 715.315 1130.74 N 0
12356 516.42 931.0 N 0 5595 371.485 80.54 S 0
12393 505.495 932.4 N 0 5655 777.255 236.14 N 0
12428 535.04 987.0 N 0 5715 844.965 84.94 N 0
12521 820.135 1026.9 N 0 5775 241.905 1274.94 N 0
12555 568.005 1025.5 N 0 5835 918.235 1122.34 N 0
12587 512.24 884.8 N 0 5895 912.535 682.54 N 0
12604 487.54 907.2 N 0 5955 377.185 1130.74 N 0
12621 430.635 873.6 N 0 6015 38.985 1127.94 N 0
12638 472.91 896.7 N 0 6075 850.595 1274.94 N 0
12655 368.22 814.8 N 0 6135 502.205 808.74 N 0
12665 272.65 850.5 N 0 6195 647.675 1274.94 N 0
12674 352.45 835.8 N 0 6255 439.125 80.54 S 0
12694 238.165 832.3 N 0 6315 642.045 228.94 N 0
12702 427.595 946.4 N 0 6375 1047.81 243.14 N 0
12704 545.395 947.1 N 0 6435 38.985 1274.94 N 0
12720 671.175 868.0 N 0 6495 985.875 1133.54 N 0
12732 565.915 946.4 N 0 6555 840.335 833.94 N 0
12832 615.79 947.8 N 0 6615 444.825 1274.94 N 0
12927 529.15 938.0 N 0 6675 38.985 984.94 S 0
13060 624.53 972.3 N 0 6735 783.025 1130.74 N 0
13190 609.995 844.2 N 0 6795 772.695 835.34 N 0
13200 519.46 818.3 N 0 6855 647.675 1130.74 N 0
13232 419.615 861.7 N 0 6915 506.765 223.54 N 0
13248 435.195 872.2 N 0 6975 844.965 247.34 N 0
13274 409.735 1047.2 N 0 7035 980.175 251.54 N 0
13283 418.095 1029.0 N 0 7095 241.905 1127.94 N 0
13293 406.79 851.2 N 0 7155 1047.81 1277.74 N 0
13299 424.175 871.5 N 0 7215 841.095 690.94 N 0
13306 482.885 941.5 N 0 7275 377.185 1274.94 N 0
13323 458.28 984.9 N 0 7335 38.985 840.74 S 0
13335 423.32 974.4 N 0 7395 980.175 846.54 N 0
13345 423.035 972.3 N 0 7455 569.845 832.54 N 0
13355 453.435 994.0 N 0 7515 641.975 983.54 N 0
13365 464.36 992.6 N 0 7575 574.335 228.94 N 0
13375 455.905 994.7 N 0 7635 912.535 235.94 N 0
13390 445.835 992.6 N 0 7695 709.615 80.54 N 0
13401 488.3 1153.6 N 0 7755 309.475 1127.94 N 0
13411 483.55 1152.9 N 0 7815 850.595 1122.34 N 0
13427 465.975 1152.2 N 0 7875 709.615 983.54 N 0
13437 472.435 1152.2 N 0 7935 512.395 1130.74 N 0
13454 466.07 1171.8 N 0 7995 107.005 830.94 S 0
13464 469.68 1153.6 N 0 8055 912.535 969.54 N 0
13481 463.885 1153.6 N 0 8115 705.055 835.34 N 0
13493 447.925 1134.7 N 0 8175 574.335 983.54 N 0
13502 423.32 1075.9 N 0 8235 439.125 366.34 N 0
13531 419.52 1057.7 N 0 8295 709.615 378.94 N 0
13579 395.58 1087.8 N 0 8355 777.255 80.54 N 0
13587 447.355 1082.9 N 0 8415 574.335 371.94 S 0
13596 434.72 1078.7 N 0 8475 1167.57 862.703 N 0
13605 418.095 1048.6 N 0 8512 1145.29 469.469 N 0
13615 398.905 1073.8 N 0 8554 1160.41 739.422 N 0
13622 427.31 1092.0 N 0 8588 1160.43 450.894 N 0
13640 423.89 1099.7 N 0 8614 1152.58 327.086 N 0
13657 431.11 1075.2 N 0 8648 1194.57 915.03 N 0
13675 423.415 1076.6 N 0 8674 1163.67 342.14 N 0
13691 415.34 1087.8 N 0 8709 700.316 522.075 N 0
13701 417.62 1087.8 N 0 8739 787.315 444.867 N 0
13712 401.28 1066.1 N 0 8766 928.513 482.788 N 0
13721 397.48 1082.2 N 0 8791 1221.6 827.74 N 0
13734 460.37 1122.8 N 0 8796 1185.3 465.387 N 0
13766 452.77 1117.9 N 0 8818 1258.72 846.079 N 0
13799 443.365 1121.4 N 0 8823 1195.19 339.64 N 0
13837 454.67 1115.8 N 0 8831 1281.96 1001.04 N 0
13876 457.71 1130.5 N 0 8835 1177.75 219.007 N 0
13906 440.04 1140.3 N 0 8839 1242.08 851.462 N 0
13939 443.555 1127.7 N 0 8846 829.209 499.686 N 0
13970 443.46 1129.8 N 0 8854 872.167 377.562 N 0
13991 550.335 1101.8 N 0 8861 1015.63 476.806 N 0
13999 539.885 1085.0 N 0 8866 1180.8 869.338 N 0
14031 548.245 1086.4 N 0 8876 1224.5 393.74 N 0
14081 553.47 1096.9 N 0 8886 1217.23 847.84 N 0
14112 564.965 1118.6 N 0 8889 1222.18 333.34 N 0
14118 562.4 1131.9 N 0 8892 1220.49 1037.28 N 0
14129 565.25 1094.1 N 0 8895 1174.52 329.066 N 0
14177 560.31 1159.2 N 0 8902 1222.64 1009.65 N 0
14200 587.575 823.9 N 0 8917 1150.56 274.54 N 0
14291 641.44 780.5 N 0 8921 777.827 514.031 N 0
14346 671.27 684.6 N 0 8931 811.636 351.944 N 0
14353 268.565 749.0 N 0 8935 809.648 468.14 N 0
14377 274.455 725.2 N 0 8940 1160.67 843.726 N 0
14384 322.81 733.6 N 0 8945 1157.13 358.337 N 0
14388 318.915 778.4 N 0 8953 1160.05 847.14 N 0
14395 503.975 865.2 N 0 8956 1159.12 339.85 N 0
14407 390.165 844.2 N 0 8961 1151.31 1047.87 N 0
14416 636.025 787.5 N 0 8995 1174.42 335.548 N 0
14426 632.985 770.7 N 0 9002 615.885 509.162 N 0
14438 637.165 764.4 N 0 9009 944.938 354.332 N 0
14449 659.68 784.0 N 0 9017 1021.16 468.253 N 0
14463 508.725 862.4 N 0 9023 257.111 1000.06 N 0
14488 424.745 837.2 N 0 9063 905.351 975.711 N 0
14496 497.135 868.0 N 0 9113 623.487 775.066 N 0
14513 621.11 693.0 N 0 9141 453.325 904.487 N 0
14523 604.39 772.1 N 0 9193 257.704 988.829 N 0
14535 399.095 836.5 N 0 9229 866.082 976.706 N 0
14549 576.46 805.0 N 0 9267 568.015 759.906 N 0
14572 608.38 794.5 N 0 9308 522.367 971.119 N 0
14587 407.93 856.1 N 0 9347 462.943 313.987 N 0
14605 608.38 793.8 N 0 9380 664.003 331.968 N 0
14617 512.145 798.0 N 0 9407 575.81 177.184 N 0
14636 611.61 790.3 N 0 9452 258.244 1010.48 N 0
14658 592.515 796.6 N 0 9464 942.325 1009.43 N 0
14670 838.945 726.6 N 0 9473 659.459 746.755 N 0
14675 406.6 851.2 N 0 9511 433.719 946.672 N 0
14684 397.48 847.0 N 0 9524 163.221 1021.86 N 0
14701 505.21 850.5 N 0 9559 878.016 1127.84 N 0
14721 403.465 821.1 N 0 9593 638.608 747.506 N 0
14732 428.45 851.2 N 0 9602 495.288 982.916 N 0
14740 412.11 823.9 N 0 9631 492.355 207.501 N 0
14761 645.715 819.7 N 0 9661 761.749 220.359 N 0
14783 560.12 822.5 N 0 9699 255.659 1050.92 N 0
14809 650.75 821.8 N 0 9705 934.435 1030.77 N 0
14825 414.39 849.8 N 0 9717 483.102 997.295 N 0
14834 619.97 790.3 N 0 9739 198.72 1043.34 N 0
14848 418.0 850.5 N 0 9755 892.298 1084.46 N 0
14883 602.205 886.2 N 0 9763 651.196 753.523 N 0
14899 402.61 870.1 N 0 9773 498.742 168.216 N 0
14926 596.315 790.3 N 0 9780 757.401 199.634 N 0
14939 619.78 793.1 N 0 9793 778.154 158.539 N 0
14953 360.525 795.2 N 0 9808 247.546 1047.14 N 0
14960 373.635 794.5 N 0 9841 943.639 1035.69 N 0
14967 366.035 752.5 N 0 9873 636.64 741.297 N 0
14994 361.57 756.7 N 0 9888 194.29 1047.03 N 0
15002 386.27 822.5 N 0 9895 897.391 1103.12 N 0
15020 510.15 837.2 N 0 9904 643.137 749.531 N 0
15047 637.07 771.4 N 0 9912 516.349 958.829 N 0
15056 655.31 774.2 N 0 9916 469.963 164.487 N 0
15069 644.1 860.3 N 0 9922 760.204 183.764 N 0
15085 571.9 773.5 N 0 9936 805.829 159.404 N 0
15098 474.145 840.0 N 0 9943 260.426 1048.61 N 0
15122 517.56 861.0 N 0 9954 932.593 1058.28 N 0
15143 414.865 841.4 N 0 9966 431.252 955.602 N 0
15164 582.92 798.0 N 0 9976 166.194 1045.86 N 0
15184 634.6 802.9 N 0 9982 869.587 1068.46 N 0
15199 650.465 800.8 N 0 9987 584.788 748.069 N 0
15221 659.585 763.0 N 0 9994 459.98 207.314 N 0
15233 418.665 879.9 N 0 10007 669.442 193.768 N 0
15257 425.6 957.6 N 0 10015 243.197 1045.88 N 0
15275 621.965 823.9 N 0 10025 940.199 1052.97 N 0
15290 414.675 645.4 N 0 10032 638.143 761.062 N 0
15339 335.54 631.4 N 0 10044 197.617 1024.84 N 0
15347 445.55 746.9 N 0 10055 818.649 1048.04 N 0
15365 387.315 605.5 N 0 10074 624.654 753.59 N 0
15378 409.64 639.8 N 0 10082 515.715 946.328 N 0
15399 430.73 722.4 N 0 10089 476.459 222.31 N 0
15423 407.36 626.5 N 0 10098 782.311 212.859 N 0
15440 384.75 650.3 N 0 10108 787.799 177.592 N 0
15471 422.465 756.7 N 0 10127 248.01 1035.9 N 0
15494 327.56 663.6 N 0 10136 653.761 731.895 N 0
15501 332.025 667.1 N 0 10142 196.302 969.315 N 0
15527 421.515 717.5 N 0 10151 930.759 954.71 N 0
15554 358.34 654.5 N 0 10163 626.732 767.532 N 0
15567 338.2 664.3 N 0 10175 482.295 891.899 N 0
15590 332.785 652.4 N 0 10192 513.149 228.876 N 0
15614 504.83 672.0 N 0 10200 671.918 167.02 N 0
15620 502.17 667.1 N 0 10209 227.389 1062.84 N 0
15629 484.025 667.8 N 0 10214 823.03 1030.3 N 0
15639 511.195 668.5 N 0 10220 635.722 771.409 N 0
15646 449.825 645.4 N 0 10226 470.725 894.453 N 0
15675 447.925 648.2 N 0 10233 204.417 941.994 N 0
15702 452.96 716.8 N 0 10239 927.94 1011.29 N 0
15754 404.605 726.6 N 0 10248 644.293 761.248 N 0
15762 414.2 761.6 N 0 10255 473.919 893.48 N 0
15788 437.19 658.7 N 0 10265 470.862 256.209 N 0
15807 487.35 724.5 N 0 10275 650.768 286.435 N 0
15848 455.335 720.3 N 0 10281 672.101 175.35 N 0
15884 418.95 796.6 N 0 10286 569.19 439.75 N 0
15896 439.47 694.4 N 0 10295 121.643 256.695 N 0
15908 404.7 676.2 N 0 10315 156.219 294.583 N 0
15919 423.035 715.4 N 0 10332 152.784 361.111 N 0
15948 510.53 800.1 N 0 10353 193.579 372.199 N 0
16153 359.195 548.8 N 0 10371 50.8127 353.627 N 0
16159 436.81 602.0 N 0 10387 104.688 361.897 N 0
16184 697.87 1004.5 N 0 10404 111.934 433.248 N 0
16195 707.655 1001.7 N 0 10415 83.8688 474.968 N 0
16206 704.71 1001.0 N 0 10427 20.2051 673.022 N 0
16217 695.02 1001.0 N 0 10457 10.4258 601.784 N 0
16236 690.745 1055.6 N 0 10480 56.0825 678.587 N 0
16244 690.27 1026.2 N 0 10505 422.571 876.627 N 0
16267 689.035 1123.5 N 0 10523 454.998 842.81 N 0
16279 700.815 1123.5 N 0 10544 316.999 927.867 N 0
16297 703.19 1123.5 N 0 10569 317.224 949.63 N 0
16313 679.915 1124.9 N 0 10583 16.7367 758.932 N 0
16317 682.575 1122.1 N 0 10588 248.996 103.848 N 0
16325 680.105 1123.5 N 0 10601 523.45 508.34 N 0
16338 691.125 1123.5 N 0 10604 413.787 904.512 N 0
16350 688.465 1122.1 N 0 10607 648.028 473.859 N 0
16363 644.195 1116.5 N 0 10641 256.853 452.241 N 0
16381 645.145 1117.9 N 0 10651 86.3273 534.974 N 0
16388 652.365 1117.9 N 0 10667 503.966 609.03 N 0
16396 642.39 1118.6 N 0 10672 538.198 614.023 N 0
16405 629.28 1036.7 N 0 10677 243.934 354.34 N 0
16420 664.81 1117.2 N 0 10696 390.329 796.622 N 0
16438 632.605 1117.2 N 0 10702 354.307 512.45 N 0
16456 648.375 1118.6 N 0 10710 524.323 484.22 N 0
16472 763.8 978.6 N 0 10713 200.75 385.701 N 0
16538 818.425 984.2 N 0 10726 64.5956 504.865 N 0
16583 809.115 1003.8 N 0 10729 163.101 532.984 N 0
16624 764.18 998.2 N 0 10755 178.976 788.7 N 0
16657 788.975 1023.4 N 0 10760 49.4305 521.192 N 0
16663 799.33 987.0 N 0 10770 368.851 518.634 N 0
16689 764.75 996.1 N 0 10773 588.458 440.892 N 0
16716 787.075 1058.4 N 0 10778 570.47 461.812 N 0
16723 758.195 1026.9 N 0 10790 877.515 681.24 N 0
16760 811.395 1031.1 N 0 10794 361.24 709.665 N 0
16784 779.38 1024.1 N 0 10800 355.297 205.21 N 0
16834 784.795 1017.1 N 0 10834 441.441 181.965 N 0
16876 791.445 1031.1 N 0 10847 345.909 658.548 N 0
16893 783.37 1028.3 N 0 10855 335.426 802.527 N 0
16923 787.55 1024.8 N 0 10859 314.005 894.91 N 0
16967 741.095 1050.7 N 0 10864 106.111 479.085 N 0
16974 763.61 1010.1 N 0 10883 621.936 463.45 N 0
17012 719.815 1041.6 N 0 10910 298.562 222.305 N 0
17029 718.865 1047.2 N 0 10916 909.675 943.185 N 0
17046 666.805 1065.4 N 0 10932 571.061 755.373 N 0
17056 663.005 1001.0 N 0 10949 322.351 688.125 N 0
17070 691.315 984.2 N 0 10966 439.519 973.303 N 0
17136 715.54 1019.2 N 0 10980 451.28 839.807 N 0
17181 682.1 1036.7 N 0 10992 415.748 224.562 N 0
17187 720.48 989.1 N 0 10996 486.424 839.063 N 0
17220 657.97 1022.7 N 0 11032 204.652 53.1343 N 0
17231 723.235 986.3 N 0 11038 387.38 165.993 N 0
17262 737.485 1005.9 N 0 11045 338.094 761.283 N 0
17309 741.475 983.5 N 0 11049 544.16 508.045 N 0
17361 730.74 973.0 N 0 11070 218.062 59.462 N 0
17405 747.46 981.4 N 0 11073 360.319 200.042 N 0
17434 750.69 925.4 N 0 11081 209.607 63.6939 N 0
17463 761.995 917.7 N 0 11091 463.724 931.599 N 0
17492 752.115 918.4 N 0 11099 203.269 318.769 N 0
17529 750.975 922.6 N 0 11110 87.3856 451.842 N 0
17547 807.5 955.5 N 0 11115 945.118 1016.71 N 0
17597 804.935 968.8 N 0 11129 237.63 61.0687 N 0
17650 806.835 946.4 N 0 11136 415.438 905.258 N 0
17702 807.12 974.4 N 0 11149 355.656 183.425 N 0
17745 822.035 912.1 N 0 11159 482.478 657.35 N 0
17771 834.48 912.8 N 0 11173 103.598 144.894 N 0
17778 853.1 910.7 N 0 11203 266.061 476.04 N 0
17783 848.35 918.4 N 0 11215 419.042 541.672 N 0
17791 786.885 977.2 N 0 11233 715.93 239.051 N 0
17836 782.23 963.2 N 0 11248 221.977 86.1158 N 0
17890 827.545 970.2 N 0 11254 446.545 723.578 N 0
17915 818.52 964.6 N 0 11276 111.264 579.256 N 0
17973 865.64 984.9 N 0 11280 248.392 478.63 N 0
17998 818.805 982.1 N 0 11291 124.685 120.261 N 0
18025 858.325 960.4 N 0 11304 116.464 466.182 N 0
18033 867.445 963.9 N 0 11309 476.836 198.836 N 0
18041 870.295 928.2 N 0 11325 740.335 398.58 N 0
18048 863.93 919.8 N 0 11328 41.4353 145.507 N 0
18057 867.825 948.5 N 0 11335 398.6 159.409 N 0
18065 867.065 945.7 N 0 11340 118.196 587.211 N 0
18077 782.61 984.2 N 0 11344 233.561 425.751 N 0
18134 783.94 977.2 N 0 11356 117.628 460.355 N 0
18189 811.68 991.2 N 0 11366 377.785 539.163 N 0
18223 818.235 998.2 N 0 11377 60.6854 177.066 N 0
18252 808.545 1020.6 N 0 11386 418.035 893.444 N 0
18261 825.265 1012.2 N 0 11394 120.854 511.691 N 0
18286 866.59 1007.3 N 0 11409 440.008 846.311 N 0
18292 820.515 998.9 N 0 11423 138.949 616.691 N 0
18322 533.52 482.3 N 0 11427 918.064 877.539 N 0
18383 418.855 597.1 N 0 11452 368.096 630.943 N 0
18396 501.6 475.3 N 0 11458 407.207 538.229 N 0
18409 346.845 598.5 N 0 11467 317.12 632.659 N 0
18428 346.655 601.3 N 0 11479 505.404 702.099 N 0
18449 336.205 569.8 N 0 11503 561.365 447.114 N 0
18478 341.715 599.9 N 0 11520 163.417 248.35 N 0
18497 461.7 507.5 N 0 11537 376.885 432.619 N 0
18506 368.695 608.3 N 0 11559 149.457 358.309 N 0
18552 484.785 525.0 N 0 11566 229.889 369.031 N 0
18566 447.07 518.7 N 0 11585 49.0423 690.442 N 0
18574 473.005 515.2 N 0 11593 452.603 823.61 N 0
18583 473.29 503.3 N 0 11603 326.735 676.585 N 0
18589 454.195 517.3 N 0 11629 196.726 432.767 N 0
18597 474.905 525.0 N 0 11660 132.942 227.364 N 0
18605 820.705 464.1 N 0 11669 280.88 722.277 N 0
18649 836.0 496.3 N 0 11675 358.475 842.975 N 0
18651 509.96 604.8 N 0 11713 451.011 851.209 N 0
18707 525.16 603.4 N 0 11738 359.728 225.426 N 0
18735 454.67 570.5 N 0 11747 499.772 800.718 N 0
18737 984.105 441.0 N 0 11778 22.542 422.771 N 0
18739 619.78 541.1 N 0 11782 359.275 384.971 N 0
18800 1004.53 403.2 N 0 11806 38.3389 755.036 N 0
18802 443.175 571.2 N 0 11817 211.938 517.589 N 0
18820 330.315 625.8 N 0 11836 438.871 172.1 N 0
18839 339.15 627.2 N 0 11840 207 151.807 N 0
18864 340.005 623.7 N 0 11844 375.852 615.314 N 0
18885 371.26 622.3 N 0 11863 377.639 486.298 N 0
18907 455.715 562.8 N 0 11896 351.718 824.526 N 0
18924 326.515 624.4 N 0 11912 172.826 307.033 N 0
18944 335.54 625.1 N 0 11939 412.446 867.712 N 0
18965 734.54 728.7 N 0 11947 499.725 692.272 N 0
18967 518.035 584.5 N 0 11957 109.171 203.719 N 0
18975 647.235 415.8 N 0 11964 507.773 526.711 N 0
18977 652.08 847.0 N 0 11970 89.4375 613.062 N 0
18979 348.84 905.1 N 0 11977 380.769 201.044 N 0
18981 618.165 753.2 N 0 11983 277.899 448.143 N 0
18983 631.75 753.9 N 0 12002 494.596 570.545 N 0
18985 891.1 1229.9 N 0 12014 354.396 579.109 N 0
18987 539.41 1046.5 N 0 12048 86.9655 79.1899 N 0
19057 443.08 717.5 N 0 12054 64.5504 345.659 N 0
19064 556.13 841.4 N 0 12058 175.781 89.4038 N 0
19066 858.895 1229.9 N 0 12119 385.816 797.562 N 0
19068 862.885 1204.7 N 0 12125 238.853 727.017 N 0
19070 852.815 940.8 N 0 12142 432.543 223.192 N 0
19072 883.215 1268.4 N 0 12154 31.5483 385.995 N 0
19074 285.38 633.5 N 0 12164 205.827 808.008 N 0
19099 369.455 698.6 N 0 12174 124.388 308.143 N 0
19140 308.845 777.7 N 0 12184 110.831 318.765 N 0
19232 294.12 667.1 N 0 12199 140.684 529.744 N 0
19274 544.16 629.3 N 0 12207 340.174 292.524 N 0
19279 597.645 718.9 N 0 12238 434.959 181.196 N 0
19326 540.74 606.2 N 0 12247 442.906 216.924 N 0
19357 553.09 606.9 N 0 12256 54.8567 271.005 N 0
19392 532.475 531.3 N 0 12262 180.785 783.751 N 0
19457 312.455 632.8 N 0 12275 464.958 741.191 N 0
19509 527.345 581.7 N 0 12285 434.731 867.968 N 0
19563 325.945 639.1 N 0 12309 1067.18 330.092 N 0
19664 807.025 496.3 N 0 12329 165.378 393.335 N 0
19666 459.04 637.0 N 0 12365 209.117 849.111 N 0
19736 574.085 588.7 N 0 12372 288.557 413.569 N 0
19800 1038.16 518.0 N 0 12388 183.849 23.3986 N 0
19802 690.745 574.7 N 0 12401 319.616 681.586 N 0
19923 668.42 728.0 N 0 12428 444.287 477.24 N 0
19929 617.215 631.4 N 0 12440 287.544 862.392 N 0
19943 421.325 634.2 N 0 12446 318.142 228.458 N 0
19977 449.825 632.8 N 0 12456 453.41 528.733 N 0
20000 386.175 688.1 N 0 12473 270.647 597.885 N 0
20016 390.165 635.6 N 0 12503 329.499 338.033 N 0
20039 685.235 599.9 N 0 12513 23.9678 524.051 N 0
20069 671.175 601.3 N 0 12523 15.7338 648.176 N 0
20107 666.14 612.5 N 0 12539 1015.41 531.59 N 0
20147 667.755 612.5 N 0 12545 172.391 500.649 N 0
20184 683.24 602.7 N 0 12559 265.876 856.038 N 0
20218 669.465 602.0 N 0 12570 108.779 668.941 N 0
20230 662.815 595.0 N 0 12597 392.255 832.681 N 0
20258 682.385 598.5 N 0 12605 176.38 577.835 N 0
20289 718.675 672.7 N 0 12614 450.526 257.253 N 0
20318 708.7 606.9 N 0 12624 322.955 282.877 N 0
20370 741.95 653.1 N 0 12639 259.68 682.753 N 0
20410 731.12 688.1 N 0 12649 135.76 216.954 N 0
20423 750.12 693.0 N 0 12656 188.748 586.284 N 0
20435 770.07 571.9 N 0 12667 176.333 404.355 N 0
20452 756.865 665.7 N 0 12688 561.341 535.112 N 0
20472 699.865 581.0 N 0 12696 289.729 465.336 N 0
20490 710.98 586.6 N 0 12737 81.3293 60.6465 N 0
20505 756.77 681.8 N 0 12744 306.856 683.218 N 0
20522 764.655 693.0 N 0 12757 361.224 798.056 N 0
20536 778.62 567.0 N 0 12769 195.107 389.343 N 0
20556 709.84 588.0 N 0 12816 164.043 796.047 N 0
20572 741.855 685.3 N 0 12821 444.434 573.133 N 0
20587 752.02 707.7 N 0 12838 232.76 676.575 N 0
20600 719.91 581.7 N 0 12856 396.899 522.918 N 0
20618 787.075 421.4 N 0 12880 147.17 430.698 N 0
20660 625.1 321.3 N 0 12895 233.57 300.439 N 0
20662 691.695 424.9 N 0 12909 283.729 384.219 N 0
20676 748.125 293.3 N 0 12925 402.289 487.794 N 0
20678 459.04 566.3 N 0 12942 156.164 824.435 N 0
20715 477.185 567.0 N 0 12951 55.7637 361.342 N 0
20748 455.145 567.0 N 0 12969 353.142 818.022 N 0
20778 499.89 480.9 N 0 12987 417.272 593.497 N 0
20819 514.33 476.7 N 0 12993 419.872 271.46 N 0
20859 823.08 335.3 N 0 13019 304.541 300.453 N 0
20861 720.765 345.1 N 0 13038 106.721 172.125 N 0
20910 829.35 306.6 N 0 13053 208.208 867.887 N 0
21032 800.375 1152.2 N 0 13063 333.657 518.131 N 0
21034 799.045 1101.8 N 0 13090 455.198 533.135 N 0
21036 943.825 973.7 N 0 13114 361.115 756.041 N 0
21038 914.565 1035.3 N 0 13122 260.584 798.341 N 0
21040 719.245 424.2 N 0 13136 435.607 555.044 N 0
21042 720.955 453.6 N 0 13145 264.966 436.949 N 0
21067 520.98 548.1 N 0 13200 388.493 617.264 N 0
21090 646.19 334.6 N 0 13240 464.359 780.241 N 0
21092 520.41 590.1 N 0 13259 359.978 160.759 N 0
21142 622.535 480.2 N 0 13278 436.835 783.447 N 0
21144 685.14 508.2 N 0 13289 351.72 452.867 N 0
21213 617.215 480.2 N 0 13307 985.204 615.332 N 0
21215 686.47 316.4 N 0 13320 402.321 759.988 N 0
21217 476.235 505.4 N 0 13328 138.804 138.638 N 0
21235 480.89 505.4 N 0 13341 205.297 486.151 N 0
21257 600.115 340.2 N 0 13365 179.997 292.986 N 0
21259 570.285 480.2 N 0 13380 418.745 704.598 N 0
21261 485.165 506.8 N 0 13394 328.496 317.966 N 0
21326 623.865 448.0 N 0 13417 389.904 343.6 N 0
21328 687.61 480.2 N 0 13439 25.3848 332.103 N 0
21330 427.595 946.4 N 0 13446 540.675 563.511 N 0
21570 836.0 496.3 N 0 13454 198.156 594.337 N 0
21677 454.67 570.5 N 0 13482 301.032 314.088 N 0
21726 984.105 441.0 N 0 13487 345.307 891.308 N 0
21819 1004.53 403.2 N 0 13497 164.663 232.403 N 0
21916 734.54 728.7 N 0 13506 226.659 803.884 N 0
22594 647.235 415.8 N 0 13512 330.439 534.726 N 0
22652 652.08 847.0 N 0 13568 101.557 491.919 N 0
22747 348.84 905.1 N 0 13578 492.259 481.686 N 0
22848 618.165 753.2 N 0 13604 44.9654 417.703 N 0
23049 631.75 753.9 N 0 13614 75.5989 300.192 N 0
23201 891.1 1229.9 N 0 13622 156.296 740.862 N 0
23331 556.13 841.4 N 0 13627 87.8062 705.765 N 0
23354 858.895 1229.9 N 0 13648 331.637 258.855 N 0
23416 862.885 1204.7 N 0 13675 363.237 388.01 N 0
23490 852.815 940.8 N 0 13679 104.701 268.519 N 0
23523 883.215 1268.4 N 0 13686 447.298 722.753 N 0
23585 807.025 496.3 N 0 13698 467.46 464.663 N 0
23685 1038.16 518.0 N 0 13710 32.0458 687.654 N 0
23739 625.1 321.3 N 0 13717 551.145 573.039 N 0
23849 748.125 293.3 N 0 13732 131.79 86.7483 N 0
23974 823.08 335.3 N 0 13743 386.725 858.035 N 0
24090 800.375 1152.2 N 0 13760 153.791 97.677 N 0
24234 799.045 1101.8 N 0 13787 507.58 479.017 N 0
24381 943.825 973.7 N 0 13801 355.983 810.179 N 0
24643 914.565 1035.3 N 0 13805 286.719 323.433 N 0
24860 719.245 424.2 N 0 13814 91.9252 34.8606 N 0
24981 646.19 334.6 N 0 13821 30.3176 403.075 N 0
25092 622.535 480.2 N 0 13832 30.3701 623.241 N 0
25159 617.215 480.2 N 0 13840 26.7026 467.042 N 0
25220 686.47 316.4 N 0 13850 57.0812 84.531 N 0
25344 600.115 340.2 N 0 13862 331.199 479.684 N 0
25489 570.285 480.2 N 0 13893 207.528 92.2183 N 0
25537 623.865 448.0 N 0 13932 71.9068 616.342 N 0
25585 687.61 480.2 N 0 13944 82.0354 628.928 N 0
13954 287.41 211.563 N 0
13971 152.747 288.127 N 0
13988 180.859 321.994 N 0
13996 459.222 466.108 N 0
14015 472.611 467.585 N 0
14042 162.705 630.701 N 0
14050 84.5217 112.079 N 0
14060 421.715 194.518 N 0
14069 80.1439 433.763 N 0
14079 266.349 437.593 N 0
14112 161.76 809.413 N 0
14118 420.118 722.359 N 0
14132 428.73 540.56 N 0
14156 214.85 129.143 N 0
14174 114.086 665.616 N 0
14194 175.748 629.233 N 0
14206 403.081 636.819 N 0
14211 511.546 592.581 N 0
14221 190.849 672.792 N 0
14228 393.551 183.171 N 0
14243 61.6327 498.368 N 0
14258 368.331 315.815 N 0
14271 270.766 335.693 N 0
14276 333.344 320.831 N 0
14290 129.317 213.305 N 0
14298 296.755 149.185 N 0
14309 24.5596 490.166 N 0
14318 437.109 680.836 N 0
14328 426.442 501.465 N 0
14342 397.196 452.602 N 0
14347 13.0208 569.899 N 0
14363 192.18 589.679 N 0
14397 137.858 174.376 N 0
14408 279.104 250.171 N 0
14449 140.491 44.8708 N 0
14461 233.805 548.05 N 0
14485 317.03 155.889 N 0
14497 134.142 620.166 N 0
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19876 535.515 882.14 N 0
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19900 635.322 739.34 N 0
CodeElements/Plc_client/test/ariane133/netlist.pb.txt
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Docs/OurProgress/README.md 0 → 100644
# **Our Progress: A Chronology**
## Table of Contents
- [Introduction](#introduction)
- [Our progress](#our-progress) and major milestones
- [Publicly available commercial SP&R flow](#June6)
- [Ariane133 macro placement using Circuit Training](#circuit-training-baseline-result-on-our-ariane133-nangate4551)
- [Replication of proxy cost](#August25)
- [NVDLA macro placement using Circuit Training](#circuit-training-baseline-result-on-our-nvdla-nangate4568)
- [Pinned questions](#pinned-to-bottom-question-list)
## **Introduction**
[MacroPlacement](../../) is an open, transparent effort to provide a public, baseline implementation of [Google Brain’s Circuit Training](https://github.com/google-research/circuit_training) (Morpheus) deep RL-based placement method. In this repo, we aim to achieve the following.
- We want to enable anyone to perform RL-based macro placement on their own design, starting from design RTL files.
- We want to enable anyone to train their own RL models based on their own designs in any design enablements, starting from design RTL files.
- We want to demystify important aspects of the Google Nature paper, including aspects unavailable in Circuit Training and aspects where the Nature paper and Circuit Training clearly diverge, in order to help researchers and users better understand the methodology.
- We want to apply learnings from the community’s collective experiences with the Google Brain team’s arXiv result, Nature paper and Circuit Training repo – and demonstrate how communication of research results might be improved in our community going forward. <span style="color:blue">A clear theme from the past months’ experience: “There is no substitute for source code.”</span>
In order to achieve the above goals, our initial focus has been on the following efforts.
- **Generating correct inputs and setup for Circuit Training.** Since Circuit Training uses protocol buffer format to represent designs, we must translate standard LEF/DEF representation to the protocol buffer format. We must also determine how to correctly feed all necessary design information into the [Google Brain’s Circuit Training](https://github.com/google-research/circuit_training) flow, e.g., halo width, canvas size, and constraints. If we accomplish this, then we can run [Google Brain’s Circuit Training](https://github.com/google-research/circuit_training) to train our own RL models or perform RL-based macro placement for our own designs.
- **Replicating important but missing parts of the [Google Nature paper](https://www.nature.com/articles/s41586-021-03544-w).** Several aspects of Circuit Training are not clearly documented in the Nature paper, nor in the code and scripts that are visible in Circuit Training. Over time, these have included hypergraph-to-graph conversion; gridding, grouping and clustering; force-directed placement; various hyperparameter settings; and more. As we keep moving forward, based on our experiments and continued Q&A and feedback from Google, we will summarize the miscorrelations between the Google Nature paper and [Google Brain’s Circuit Training](https://github.com/google-research/circuit_training), as well as corrective steps. In this way, the Circuit Training methodology and the results published in the Nature paper can be better understood by all.
## **Our Progress**
<a id="June6"></a>
**June 6 - Aug 5:** We have developed and made publicly available the SP&R [flow](../../Flows/) using commercial tools Cadence Genus and Innovus, and open-source tools Yosys and OpenROAD, for [Ariane](../../Testcases/ariane136/) (two variants – one with [136 SRAMs](../../Testcases/ariane136/) and another with [133 SRAMs](../../Testcases/ariane133/)), [MemPool tile](../../Testcases/mempool/) and [NVDLA](../../Testcases/nvdla/) designs on [NanGate45](../../Enablements/NanGate45/), [ASAP7](../../Enablements/ASAP7/) and [SKY130HD](../../Enablements/SKY130HD/) open enablement. <span style="color:red">We applaud and thank Cadence Design Systems for allowing their tool runscripts to be shared openly by researchers, enabling reproducibility of results obtained via use of Cadence tools</span>. This was an important milestone for the EDA research community. Please see Dr. David Junkin’s [presentation](https://open-source-eda-birds-of-a-feather.github.io/doc/slides/BOAF-Junkin-DAC-Presentation.pdf) at the recent DAC-2022 “Open-Source EDA and Benchmarking Summit” birds-of-a-feather [meeting](https://open-source-eda-birds-of-a-feather.github.io/).
The following describes our learning related to testcase generation and its implementation using different tools on different platforms.
1. The [Google Nature paper](https://www.nature.com/articles/s41586-021-03544-w) uses the Ariane testcase (contains 133 256x16-bit SRAMs) for their experiment. [Here](../../Testcases/ariane136/) we show that just instantiating 256x16 bit SRAMs results in 136 SRAMs in the synthesized netlist. Based on our investigations, we have provided the [detailed steps](../../Testcases/ariane133/) to convert the Ariane design with 136 SRAMs to a Ariane design with 133 SRAMs.
2. We provide the required SRAM lef, lib along with the description to reproduce the provided SRAMs or generate a new SRAM for each [enablement](../../Enablements/).
3. The SKY130HD enablement has only five metal layers, while SRAMs have routing up through the M4 layer. This causes P&R failure due to very high routing congestion. We therefore developed FakeStack-extended P&R enablement, where we replicate the first four metal layers to generate a nine metal layer enablement. We call this [SKY130HD-FakeStack](../../Enablements/SKY130HD/) and have used it to implement our testcases. We also provide a [script](../../Enablements/SKY130HD/lef/genTechLef.tcl) for researchers to generate FakeStack enablements with different configurations.
4. We provide power grid generation [scripts](../../Flows/util/pdn_flow.tcl) for Cadence Innovus. During the power grid (PG) generation process we made sure the routing resource used by the PG is in the range of ~20%, matching the guidance given in Circuit Training.
5. Also we provide an Innovus Tcl [script](../../Flows/util/extract_report.tcl) to extract the metrics reported in Table 1 of “[A graph placement methodology for fast chip design](https://www.nature.com/articles/s41586-021-03544-w)”, **at three stages of the post-floorplanning P&R flow, i.e., pre-CTS, post-CTSOpt, and post-RouteOpt (final)**. This [script](../../Flows/util/extract_report.tcl) is included in the P&R flow. The extracted metrics for all of our designs, on different enablements, are available [here](../../ExperimentalData/).
<a id="June10"></a>
**June 10:** [grouper.py](https://github.com/google-research/circuit_training/blob/main/circuit_training/grouping/grouper.py) was released in CircuitTraining. **This revealed that protobuf input to the hypergraph clustering into soft macros included the (x,y) locations of the nodes**. (A [grouper.py](https://github.com/google-research/circuit_training/blob/main/circuit_training/grouping/grouper.py) script had been shown to Prof. Kahng during a meeting at Google on May 19.) The use of (x,y) locations from a physical synthesis tool was very unexpected, since it is not mentioned in “Methods” or other descriptions given in the Nature paper. We raised [issue #25](https://github.com/google-research/circuit_training/issues/25#issue-1268683034) to get clarification about this. [**July 10**: The [README](https://github.com/google-research/circuit_training/blob/main/circuit_training/grouping/README.md#faq) added to [the grouping area](https://github.com/google-research/circuit_training/tree/main/circuit_training/grouping) of CircuitTraining confirmed that the input netlist has all of its nodes **already placed**.]
We currently use the physical synthesis tool **Cadence Genus iSpatial** to obtain (x,y) placed locations per instance as part of the input to Grouping. The Genus iSpatial post-physical-synthesis netlist is the starting point for how we produce the clustered netlist and the *.plc file which we provide as open inputs to CircuitTraining. From post-physical-synthesis netlist to clustered netlist generation can be divided into the following steps, which we have implemented as open-source in our CodeElements area:
1. **June 6**: [Gridding](../../CodeElements/Gridding/) determines a dissection of the layout canvas into some number of rows and some number of columns of gridcells.
2. **June 10**: [Grouping](../../CodeElements/Grouping/) groups closely-related logic with the corresponding hard macros and clumps of IOs.
3. **June 12**: [Clustering](../../CodeElements/Clustering/) clusters of millions of standard cells into a few thousand clusters (soft macros).
**June 22:** We added our [flow-scripts](../../CodeElements/CodeFlowIntegration/) that run our gridding, grouping and clustering implementations to generate a final clustered netlist in **protocol buffer format**. Google’s [netlist protocol buffer format](https://github.com/google-research/circuit_training/blob/main/docs/NETLIST_FORMAT.md) documentation available in the [CircuitTraining repo](https://github.com/google-research/circuit_training) was very helpful to our understanding of how to convert a placed netlist to protobuf format. Our scripts enable clustered netlists in protobuf format to be produced from placed netlists in either LEF/DEF or Bookshelf format.
**July 12:** As stated in the “What is your timeline?” FAQ response [see also note [5] [here](https://docs.google.com/document/d/1vkPRgJEiLIyT22AkQNAxO8JtIKiL95diVdJ_O4AFtJ8/edit?usp=sharing)], we presented progress to date in this [MacroPlacement talk](https://open-source-eda-birds-of-a-feather.github.io/doc/slides/MacroPlacement-SpecPart-DAC-BOF-v5.pdf) at the DAC-2022 “Open-Source EDA and Benchmarking Summit” birds-of-a-feather [meeting](https://open-source-eda-birds-of-a-feather.github.io/).
**July 26:** <span style="color:blue">Replication of the wirelength component of proxy cost</span>. The wirelength is similar to HPWL where given a netlist, we take the width and height and sum them up for each net. One caveat is that for soft macro pins, there could be a weight factor which implies the total connections between the source and sink pins. If not defined, the default value is 1. This weight factor needs to be multiplied with the sum of width and height to replicate Google’s API. We provide the following table as a comparison between [our implementations](../../CodeElements/Plc_client/) and Google’s API.
<table>
<thead>
<tr>
<th>Testcase</th>
<th>Notes</th>
<th>Canvas width/height</th>
<th>Grid col/row</th>
<th>Google</th>
<th>Our</th>
</tr>
</thead>
<tbody>
<tr>
<td>Ariane</td>
<td>Google’s Ariane</td>
<td>356.592 / 356.640</td>
<td>35 / 33</td>
<td>0.7500626080261634</td>
<td>0.7500626224300161</td>
</tr>
<tr>
<td>Ariane133</td>
<td>From MacroPlacement</td>
<td>1599.99 / 1598.8</td>
<td>50 / 50</td>
<td>0.6522555375409593</td>
<td>0.6522555172428797</td>
</tr>
</tbody>
</table>
**July 31:** The [netlist protocol buffer](https://github.com/google-research/circuit_training/blob/main/docs/NETLIST_FORMAT.md) format documentation also helped us to write this Innovus-based [tcl script](../../Flows/util/gen_pb.tcl) which converts physical synthesized netlist to protobuf format in Innovus. <span style="color:red">[This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.]</span> We use this post-physical-synthesis protobuf netlist as input to the grouping code to generate the clustered netlist. Fixes that we made while running Google’s grouping code resulted in [this [08/01/2022] pull request](https://github.com/google-research/circuit_training/pull/33). [08/05/2022: Google’s grouping code has been updated based on this [PR](https://github.com/google-research/circuit_training/pull/33).]
**July 22-August 4:** We shared with Google engineers our (flat) [post-physical-synthesis-protobuf netlist (ariane.pb.txt)](https://drive.google.com/file/d/1dVltyKwjWcCAPRRKlcN2CRSeaxuaScPI/view?usp=sharing) of [our Ariane design with 133 SRAMs on the NanGate45 platform](https://drive.google.com/file/d/1BvqqSngFiWXk5WNAFDO8KMPq3eqI5THf/view?usp=sharing), along with the corresponding [clustered netlist and the legalized.plc file (clustered netlist: netlist.pb.txt)](https://drive.google.com/file/d/1dVltyKwjWcCAPRRKlcN2CRSeaxuaScPI/view?usp=sharing) generated using the [CircuitTraining grouping code](https://github.com/google-research/circuit_training). The goal here was to verify our steps and setup up to this point. Also, we provide [scripts](../../Flows/util/) (using both our [CodeElements](../../CodeElements/) and [CT-grouping](https://github.com/google-research/circuit_training/tree/main/circuit_training/grouping)) to integrate the clustered netlist generation with the SP&R flow.
**August 5:** The following table compares the clustering results for [Ariane133-NG45](../../Flows/NanGate45/ariane133/) design generated by the Google engineer (internally to Google) and the clustering results generated by us using [CT grouping code](https://github.com/google-research/circuit_training/tree/main/circuit_training/grouping).
<table>
<thead>
<tr>
<th></th>
<th>Google Internal flow (from Google)</th>
<th>Our use of CT Grouping code </th>
</tr>
</thead>
<tbody>
<tr>
<td>Number of grid rows x columns</td>
<td>21 x 24</td>
<td>21 x 24</td>
</tr>
<tr>
<td>Number of soft macros</td>
<td>736</td>
<td>738</td>
</tr>
<tr>
<td>HPWL</td>
<td>4171594.811</td>
<td>4179069.884</td>
</tr>
<tr>
<td>Wirelength cost</td>
<td>0.072595</td>
<td>0.072197</td>
</tr>
<tr>
<td>Congestion cost</td>
<td>0.727798</td>
<td>0.72853</td>
</tr>
</tbody>
</table>
**August 11:** We received information from Google that when a standard cell has multiple outputs, it merges all of them in the protobuf netlist (example: a full adder cell would have its outputs merged). The possible vertices of a hyperedge are macro pins, ports, and standard cells. Our Innovus-based protobuf netlist generation [tcl script](../../Flows/util/gen_pb.tcl) takes care of this.
**August 15:** We received information from Google engineers that in the proxy cost function, the density weight is set to 0.5 for their internal runs.
**August 17:** The proxy wirelength cost which is usually a value between 0 and 1, is related to the HPWL we computed earlier. We deduce the formulation as the following:
<p align="center">
<img width="400" src="./images/image11.png" alg="wlCost">
</p>
|netlist| is the total number of nets and it takes into account the weight factor defined on soft macro pins. Here is [our proxy wirelength](../../CodeElements/Plc_client/) compared with Google’s API:
<table>
<thead>
<tr>
<th>Testcase</th>
<th>Notes</th>
<th>Canvas width/height</th>
<th>Google</th>
<th>Our</th>
</tr>
</thead>
<tbody>
<tr>
<td>Ariane</td>
<td>Google’s Ariane</td>
<td>356.592 / 356.640</td>
<td>0.05018661999974192</td>
<td>0.05018662006439473</td>
</tr>
<tr>
<td>Ariane133</td>
<td>From MacroPlacement</td>
<td>1599.99 / 1598.8</td>
<td>0.04456188308735019</td>
<td>0.04456188299072617</td>
</tr>
</tbody>
</table>
<span style="color:blue">Replication of the density component of proxy cost</span>. We now have a verified density cost computation. Density cost computation depends on gridcell density. Gridcell density is the ratio of the total area occupied by standard cells, soft macros and hard macros to the total area of the grid. If there are cell overlaps then it may result in grid density greater than one. To get the density cost, we take the average of the top 10% of the densest gridcells. Before outputting it, we multiply it by 0.5. Notice that this **0.5 is not the “weight” of this cost function**, but simply another factor applied besides the weight factor from the cost function.
<p align="center">
<img width="400" src="./images/image29.png" alg="DenCost">
</p>
<table>
<thead>
<tr>
<th>Testcase</th>
<th>Notes</th>
<th>Canvas width/height</th>
<th>Grid col/row</th>
<th>Google</th>
<th>Our</th>
</tr>
</thead>
<tbody>
<tr>
<td>Ariane</td>
<td>Google’s Ariane</td>
<td>356.592 / 356.640</td>
<td>35 / 33</td>
<td>0.7500626080261634</td>
<td>0.7500626224300161</td>
</tr>
<tr>
<td>Ariane133</td>
<td>From MacroPlacement</td>
<td>1599.99 / 1598.8</td>
<td>50 / 50</td>
<td>0.6522555375409593</td>
<td>0.6522555172428797</td>
</tr>
</tbody>
</table>
<a id="August18"></a>
**August 18:** The flat post-physical-synthesis protobuf netlist of [Ariane133-NanGate45](../../Flows/NanGate45/ariane133/) design is used as input to [CT grouping](https://github.com/google-research/circuit_training/tree/main/circuit_training/grouping) code to generate the clustered netlist. We then use this clustered netlist in Circuit Training. [Coordinate Descent](https://github.com/google-research/circuit_training/blob/main/circuit_training/environment/coordinate_descent_placer.py) is (by [default](https://github.com/google-research/circuit_training/blob/9e7097fa0c2a82030f43b298259941fc8ca6b7ae/circuit_training/learning/eval.py#L50-L52)) not applied to any macro placement solution. Here is the [link](https://tensorboard.dev/experiment/eCRHe29LQvi1sdAPD61Q6A/#scalars) to our tensorboard. We ran Innovus P&R starting from the macro placement generated using CT, through the end of detailed routing (RouteOpt) and collection of final PPA / “Table 1” metrics. Following are the metrics and screen shots of the P&R database. **Throughout the SP&R flow, the target clock period is 4ns**. The power grid overhead is 18.46% in the actual P&R setup, matching the 18% [mentioned](https://github.com/google-research/circuit_training/blob/9e7097fa0c2a82030f43b298259941fc8ca6b7ae/circuit_training/environment/placement_util.py#L183-L186) in the Circuit Training repo. **All results are for DRC-clean final routing produced by the Innovus tool**.
<span style="color:blue">[In the immediately-following content, we also show comparison results using other macro placement methods, collected since August 18.]
[As of August 24 onward, we refer to this testcase as “Our Ariane133-NanGate45_51” since it has 51% area utilization. A second testcase, “Our Ariane133-NanGate45_68”, has 68% area utilization which exactly matches that of the Ariane in Circuit Training.]</span>
### Circuit Training Baseline Result on “Our Ariane133-NanGate45_51”.
<a id="Ariane133_51_CT"></a>
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro placement generated by Circuit Training on Our Ariane-133 (NG45), with post-macro placement flow using Innovus21.1</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>2560080</td>
<td>214555</td>
<td>1018356</td>
<td>287.79</td>
<td>4343214</td>
<td>0.005</td>
<td>0</td>
<td>0.01%</td>
<td>0.02%</td>
</tr>
<tr>
<td>postCTS</td>
<td>2560080</td>
<td>216061</td>
<td>1018356</td>
<td>301.31</td>
<td>4345969</td>
<td>0.010</td>
<td>0</td>
<td>0.01%</td>
<td>0.02%</td>
</tr>
<tr>
<td>postRoute</td>
<td>2560080</td>
<td>216061</td>
<td>1018356</td>
<td>300.38</td>
<td>4463660</td>
<td>0.359</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image26.png" alg="Ariane133_51_CT_Place">
<img width="300" src="./images/image3.png" alg="Ariane133_51_CT_Route">
</p>
**Comparison 1: “Human Gridded”.** For comparison, a baseline “human, gridded” macro placement was generated by a human for the same canvas size, I/O placement and gridding, with results as follows.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro placement generated by a human on Our Ariane-133 (NG45), with post-macro placement flow using Innovus21.1</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>2560080</td>
<td>215188.9</td>
<td>1018356</td>
<td>285.96</td>
<td>4470832</td>
<td>-0.002</td>
<td>-0.005</td>
<td>0.00%</td>
<td>0.00%</td>
</tr>
<tr>
<td>postCTS</td>
<td>2560080</td>
<td>216322.9</td>
<td>1018356</td>
<td>299.62</td>
<td>4472866</td>
<td>0.001</td>
<td>0</td>
<td>0.00%</td>
<td>0.00%</td>
</tr>
<tr>
<td>postRoute</td>
<td>2560080</td>
<td>216322.9</td>
<td>1018356</td>
<td>298.60</td>
<td>4587141</td>
<td>0.284</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image4.png" alg="Ariane133_51_Human_Place">
</p>
**Comparison 2: RePlAce.** The standalone RePlAce placer was run on the same (flat) netlist with the same canvas size and I/O placement, with results as follows.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro placement generated by RePlAce (standalone, from <a href="https://github.com/mgwoo/RePlAce">HERE</a>) on Our Ariane-133 (NG45), with post-macro placement flow using Innovus21.1</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>2560080</td>
<td>214910.71</td>
<td>1018356</td>
<td>288.654</td>
<td>4178509</td>
<td>0.003</td>
<td>0</td>
<td>0.03%</td>
<td>0.07%</td>
</tr>
<tr>
<td>postCTS</td>
<td>2560080</td>
<td>216006.63</td>
<td>1018356</td>
<td>302.013</td>
<td>4184690</td>
<td>0.007</td>
<td>0</td>
<td>0.05%</td>
<td>0.08%</td>
</tr>
<tr>
<td>postRoute</td>
<td>2560080</td>
<td>216006.63</td>
<td>1018356</td>
<td>301.260</td>
<td>4315157</td>
<td>-0.207</td>
<td>-0.41</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image25.png" alg="Ariane133_51_RePlAce_Place">
<img width="300" src="./images/image30.png" alg="Ariane133_51_RePlAce_Route">
</p>
**Comparison 3: [RTL-MP](https://vlsicad.ucsd.edu/Publications/Conferences/389/c389.pdf).** The RTL-MP macro placer described in [this ISPD-2022 paper](https://vlsicad.ucsd.edu/Publications/Conferences/389/c389.pdf) and used as the default macro placer in OpenROAD was run on the same (flat) netlist with the same canvas size and I/O placement, with results as follows.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro placement generated using <a href="https://vlsicad.ucsd.edu/Publications/Conferences/389/c389.pdf">RTL-MP</a> on Our Ariane-133 (NG45), with post-macro placement flow using Innovus21.1</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>2560080</td>
<td>216420.26</td>
<td>1018356</td>
<td>289.435</td>
<td>5164199</td>
<td>0.020</td>
<td>0</td>
<td>0.04%</td>
<td>0.05%</td>
</tr>
<tr>
<td>postCTS</td>
<td>2560080</td>
<td>217938.32</td>
<td>1018356</td>
<td>303.757</td>
<td>5185004</td>
<td>0.001</td>
<td>0</td>
<td>0.05%</td>
<td>0.07%</td>
</tr>
<tr>
<td>postRoute</td>
<td>2560080</td>
<td>217938.32</td>
<td>1018356</td>
<td>302.844</td>
<td>5306735</td>
<td>0.104</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image39.png" alg="Ariane133_51_RTLMP_Place">
<img width="300" src="./images/image1.png" alg="Ariane133_51_RTLMP_Route">
</p>
**Comparison 4:** The Hier-RTLMP macro placer was run on the same (flat) netlist with the same canvas size and I/O placement, with results as follows. [The Hier-RTLMP paper is in submission as of August 2022; availability in OpenROAD and OpenROAD-flow-scripts is planned by end of September 2022. Please email [abk@eng.ucsd.edu](mailto:abk@eng.ucsd.edu) if you would like a preprint, not for further redistribution.]
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro placement generated using Hier-RTLMP on Our Ariane-133 (NG45), with post-macro placement flow using Innovus21.1</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>2560080</td>
<td>214783.83</td>
<td>1018356</td>
<td>288.356</td>
<td>4397005</td>
<td>0.005</td>
<td>0</td>
<td>0.02%</td>
<td>0.05%</td>
</tr>
<tr>
<td>postCTS</td>
<td>2560080</td>
<td>215911.67</td>
<td>1018356</td>
<td>302.176</td>
<td>4419305</td>
<td>0.009</td>
<td>0</td>
<td>0.04%</td>
<td>0.06%</td>
</tr>
<tr>
<td>postRoute</td>
<td>2560080</td>
<td>215911.67</td>
<td>1018356</td>
<td>301.468</td>
<td>4537458</td>
<td>0.311</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image16.png" alg="Ariane133_51_HierRTLMP_Place">
<img width="300" src="./images/image13.png" alg="Ariane133_51_HierRTLMP_Route">
</p>
<a id="August20"></a>
**August 20:** <span style="color:blue">Matching the area utilization</span>. We revisited the area utilization of Our Ariane133 and realized that it (51%) is lower than that of Google’s Ariane (68%). So that this would not devalue our study, we created a second variant, “**Our Ariane133-NanGate45_68**”, which matches the area utilization of Google’s Ariane. Results are as given below.
### **Circuit Training Baseline Result on “Our Ariane133-NanGate45**<span style="color:red">**_68**</span>**".**
<a id="Ariane133_68_CT"></a>
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated Using CT (Ariane 68% Utilization)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>215575.444</td>
<td>1018355.73</td>
<td>288.762</td>
<td>4170253</td>
<td>0.002</td>
<td>0</td>
<td>0.01%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>217114.520</td>
<td>1018355.73</td>
<td>302.607</td>
<td>4186888</td>
<td>0.001</td>
<td>0</td>
<td>0.00%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>217114.520</td>
<td>1018355.73</td>
<td>301.722</td>
<td>4295572</td>
<td>0.336</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image17.png" alg="Ariane133_68_CT_Place">
<img width="300" src="./images/image15.png" alg="Ariane133_68_CT_Route">
</p>
**Comparison 1: “Human Gridded”**. For comparison, a baseline “human, gridded” macro placement was generated by a human for the same canvas size, I/O placement and gridding.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated by human (Util: 68%)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>215779</td>
<td>1018355.73</td>
<td>289.999</td>
<td>4545632</td>
<td>-0.003</td>
<td>-0.004</td>
<td>0.09%</td>
<td>0.15%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>217192</td>
<td>1018355.73</td>
<td>303.786</td>
<td>4571293</td>
<td>0.001</td>
<td>0</td>
<td>0.13%</td>
<td>0.16%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>217192</td>
<td>1018355.73</td>
<td>302.725</td>
<td>4720776</td>
<td>0.206</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image10.png" alg="Ariane133_68_Human_Place">
<img width="300" src="./images/image21.png" alg="Ariane133_68_Human_Route">
</p>
**Comparison 2: RePlAce.** The standalone RePlAce placer was run on the same (flat) netlist with the same canvas size and I/O placement, with results as follows.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated Using RePlAce (Util: 68%)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>217246</td>
<td>1018355.73</td>
<td>292.803</td>
<td>4646408</td>
<td>-0.007</td>
<td>-0.011</td>
<td>0.07%</td>
<td>0.13%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>218359</td>
<td>1018355.73</td>
<td>306.145</td>
<td>4657174</td>
<td>0.001</td>
<td>0</td>
<td>0.07%</td>
<td>0.17%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>218359</td>
<td>1018355.73</td>
<td>305.032</td>
<td>4809950</td>
<td>0.082</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image35.png" alg="Ariane133_68_RePlAce_Place">
<img width="300" src="./images/image5.png" alg="Ariane133_68_RePlAce_Route">
</p>
**Comparison 3: [RTL-MP](https://vlsicad.ucsd.edu/Publications/Conferences/389/c389.pdf).** The RTL-MP macro placer was run on the same (flat) netlist with the same canvas size and I/O placement, with results as follows.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated Using RTL-MP (Util: 68%)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>217057</td>
<td>1018355.73</td>
<td>292.800</td>
<td>4598656</td>
<td>-0.001</td>
<td>-0.001</td>
<td>0.00%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>218045</td>
<td>1018355.73</td>
<td>306.475</td>
<td>4614827</td>
<td>0.007</td>
<td>0</td>
<td>0.00%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>218045</td>
<td>1018355.73</td>
<td>303.380</td>
<td>4745004</td>
<td>0.294</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image23.png" alg="Ariane133_68_RTLMP_Place">
<img width="300" src="./images/image31.png" alg="Ariane133_68_RTLMP_Route">
</p>
**Comparison 4:** The Hier-RTLMP macro placer was run on the same (flat) netlist with the same canvas size and I/O placement, using two setups, with results as follows.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated Using Hier-RTLMP (Util: 68%) [Setup 1]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>218096</td>
<td>1018355.73</td>
<td>294.035</td>
<td>4967286</td>
<td>0.003</td>
<td>0</td>
<td>0.10%</td>
<td>0.12%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>219150</td>
<td>1018355.73</td>
<td>308.130</td>
<td>4984385</td>
<td>0.001</td>
<td>0</td>
<td>0.13%</td>
<td>0.13%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>219150</td>
<td>1018355.73</td>
<td>307.103</td>
<td>5137430</td>
<td>0.387</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image20.png" alg="Ariane133_68_HierRTLMP1_Place">
<img width="300" src="./images/image19.png" alg="Ariane133_68_HierRTLMP1_Route">
</p>
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated Using Hier-RTLMP (Util: 68%) [Setup 2]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>216665</td>
<td>1018355.73</td>
<td>291.332</td>
<td>4917102</td>
<td>0.001</td>
<td>0</td>
<td>0.02%</td>
<td>0.06%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>217995</td>
<td>1018355.73</td>
<td>305.089</td>
<td>4931432</td>
<td>0.001</td>
<td>0</td>
<td>0.03%</td>
<td>0.05%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>217995</td>
<td>1018355.73</td>
<td>303.905</td>
<td>5048575</td>
<td>0.230</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image22.png" alg="Ariane133_68_HierRTLMP2_Place">
<img width="300" src="./images/image18.png" alg="Ariane133_68_HierRTLMP2_Route">
</p>
<a id="August25"></a>
**August 25:** <span style="color:blue">Replication of the congestion component of proxy cost</span>. Reverse-engineering from the plc client API is finally completed, as described [here](https://docs.google.com/document/d/1hM7UbmANkhoGB3-UfFBp8TRDvvVjpmio7cyyjK4a5bI/edit?usp=sharing). A review with Dr. Mustafa Yazgan was very helpful in confirming the case analysis and conventions identified during reverse-engineering. Replication results are shown below. With this, reproduction in open [source code](../../CodeElements/Plc_client/) of the Circuit Training proxy cost has been completed. Note that the description [here](https://docs.google.com/document/d/1hM7UbmANkhoGB3-UfFBp8TRDvvVjpmio7cyyjK4a5bI/edit?usp=sharing) illustrates how the Nature paper, Circuit Training, and Google engineers’ versions can have minor discrepancies. (These minor discrepancies are not currently viewed as substantive, i.e., meaningfully affecting our ongoing assessment.) For example, to calculate the congestion component, the H- and V-routing congestion cost lists are concatenated, and the ABU5 (average of top 5% of the concatenated list) metric of this list is the congestion cost. By contrast, the Nature paper indicates use of an ABU10 metric. Recall: “*There is no substitute for source code*.”
<table>
<thead>
<tr>
<th>Name</th>
<th>Description</th>
<th>Canvas Size</th>
<th>Col/Row</th>
<th>Congestion Smoothing</th>
<th>Google’s Congestion</th>
<th>Our Congestion</th>
</tr>
</thead>
<tbody>
<tr>
<td>Ariane</td>
<td>Google’s Ariane</td>
<td>356.592 / 356.640</td>
<td>35 / 33</td>
<td>0</td>
<td>3.385729893179586</td>
<td>3.3857299314069733</td>
</tr>
<tr>
<td>Ariane133</td>
<td>Our Ariane</td>
<td>1599.99 / 1600.06</td>
<td>24 / 21</td>
<td>0</td>
<td>1.132108622298701</td>
<td>1.1321086382282062</td>
</tr>
<tr>
<td>Ariane</td>
<td>Google’s Ariane</td>
<td>356.592 / 356.640</td>
<td>35 / 33</td>
<td>1</td>
<td>2.812822828059799</td>
<td>2.81282287498789</td>
</tr>
<tr>
<td>Ariane133</td>
<td>Our Ariane</td>
<td>1599.99 / 1600.06</td>
<td>24 / 21</td>
<td>1</td>
<td>1.116203573147857</td>
<td>1.1162035989647672</td>
</tr>
<tr>
<td>Ariane</td>
<td>Google’s Ariane</td>
<td>356.592 / 356.640</td>
<td>35 / 33</td>
<td>2</td>
<td>2.656602005772668</td>
<td>2.6566020148393146</td>
</tr>
<tr>
<td>Ariane133</td>
<td>Our Ariane</td>
<td>1599.99 / 1600.06</td>
<td>24 / 21</td>
<td>2</td>
<td>1.109241385529823</td>
<td>1.1092414113467333</td>
</tr>
</tbody>
</table>
**August 26:** <span style="color:blue">Moving on to understand benefits and limitations of the Circuit Training methodology itself</span>. This next stage of study is enabled by confidence in the technical solidity of what has been accomplished so far – again, with the help of Google engineers.
<a id="Question1"></a>
**<span style="color:blue">Question 1.</span>** How does having an initial set of placement locations (from physical synthesis) affect the (relative) quality of the CT result?
*A preliminary exercise has compared outcomes when the Genus iSpatial (x,y) coordinates are given, versus when vacuous (x,y) coordinates are given. The following CT result is for the “**Our Ariane133-NanGate45_68**” example where the input protobuf netlist to Circuit Training’s grouping code has all macro and standard cell locations set to (600, 600). This is just an exercise for now: other, carefully-designed experiments will be performed over the coming weeks and months.*
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated using CT (Util: 68%) with a vacuous set of input (x,y) coordinates. The input protobuf netlist to Circuit Training’s grouping code has all macro and standard cell locations set to (600, 600).</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>216069</td>
<td>1018355.73</td>
<td>290.0818</td>
<td>4615961</td>
<td>-0.004</td>
<td>-0.021</td>
<td>0.01%</td>
<td>0.03%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>217118</td>
<td>1018355.73</td>
<td>303.7199</td>
<td>4619727</td>
<td>0</td>
<td>0</td>
<td>0.01%</td>
<td>0.02%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>217118</td>
<td>1018355.73</td>
<td>302.4018</td>
<td>4738717</td>
<td>0.171</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image14.png" alg="Ariane133_68_CT_Vacuous1_Place">
<img width="300" src="./images/image36.png" alg="Ariane133_68_CT_Vacuous1_Route">
</p>
<a id="Question2"></a>
**<span style="color:blue">Update to Question 1 on September 9:</span>** Two additional vacuous placements were run through the CT flow.
- Place all macros and standard cells at the lower left corner i.e., (0, 0).
- Place all macros and standard cells at the upper right corner, i.e., (max_x, max_y), where max_x = 1347.1 and max_y = 1346.8.
- (0, 0) gives us the best (by a small amount) result among the three vacuous placements. It has been requested that we report variances and p values. We are unsure how to resource such a request. Note that the original baseline result here, using the (x,y) information from physical synthesis, achieves a final routed wirelength of 4295572, around 7% better than the (0, 0) result.
The following table and screenshots show results for the (0, 0) vacuous placement.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated using CT (Util: 68%) with a vacuous set of input (x,y) coordinates. The input protobuf netlist to Circuit Training’s grouping code has all macro and standard cell locations set to (0, 0).</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>215520</td>
<td>1018356</td>
<td>289.676</td>
<td>4489121</td>
<td>-0.006</td>
<td>-0.007</td>
<td>0.02%</td>
<td>0.09%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>216891</td>
<td>1018356</td>
<td>302.551</td>
<td>4495430</td>
<td>0.005</td>
<td>0</td>
<td>0.02%</td>
<td>0.10%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>216891</td>
<td>1018356</td>
<td>301.322</td>
<td>4606716</td>
<td>0.218</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image32.png" alg="Ariane133_68_CT_Vacuous2_Place">
<img width="300" src="./images/image38.png" alg="Ariane133_68_CT_Vacuous2_Route">
</p>
The following table and screenshots show results for (max_x, max_y), where max_x = 1347.1 and max_y = 1346.8.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated using CT (Util: 68%) with a vacuous set of input (x,y) coordinates. The input protobuf netlist to Circuit Training’s grouping code has all macro and standard cell locations set to (max_x, max_y) = (1347.1, 1346.8)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>214817</td>
<td>1018356</td>
<td>288.454</td>
<td>4530507</td>
<td>0.002</td>
<td>0</td>
<td>0.01%</td>
<td>0.04%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>215844</td>
<td>1018356</td>
<td>301.719</td>
<td>4532853</td>
<td>0.007</td>
<td>0</td>
<td>0.03%</td>
<td>0.05%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>215844</td>
<td>1018356</td>
<td>300.763</td>
<td>4646396</td>
<td>0.228</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image27.png" alg="Ariane133_68_CT_Vacuous3_Place">
<img width="300" src="./images/image33.png" alg="Ariane133_68_CT_Vacuous3_Route">
</p>
**<span style="color:blue">Question 2.</span>** How does utilization affect the (relative) performance of CT?
<a id="Question3"></a>
**<span style="color:blue">Question 3.</span>** Is a testcase such as Ariane-133 “probative”, or do we need better testcases?
*A preliminary exercise has examined Innovus P&R outcomes when the Circuit Training macro placement locations for Our Ariane133-NanGate45_68 are **randomly shuffled**. The results for four seed values used in the shuffle, and for the original Circuit Training result, are as follows.*
<table>
<thead>
<tr>
<th>Metric</th>
<th>CT_Shuffle_1</th>
<th>CT_Shuffle_2</th>
<th>CT_Shuffle_3</th>
<th>CT_Shuffle_4</th>
<th>CT_Result</th>
</tr>
</thead>
<tbody>
<tr>
<td>Core_area (um^2)</td>
<td>1814274.28</td>
<td>1814274.28</td>
<td>1814274.28</td>
<td>1814274.28</td>
<td>1814274.28</td>
</tr>
<tr>
<td>Macro_area (um^2)</td>
<td>1018355.73</td>
<td>1018355.73</td>
<td>1018355.73</td>
<td>1018355.73</td>
<td>1018355.73</td>
</tr>
<tr>
<td>preCTS_std_cell_area (um^2)</td>
<td>217124.89</td>
<td>217168.25</td>
<td>217157.88</td>
<td>217020.09</td>
<td>215575.44</td>
</tr>
<tr>
<td>postCTS_std_cell_area (um^2)</td>
<td>218215.23</td>
<td>218231.19</td>
<td>218328.81</td>
<td>218073.45</td>
<td>217114.52</td>
</tr>
<tr>
<td>postRoute_std_cell_area (um^2)</td>
<td>218215.23</td>
<td>218231.19</td>
<td>218328.81</td>
<td>218073.45</td>
<td>217114.52</td>
</tr>
<tr>
<td>preCTS_total_power (mW)</td>
<td>292.032</td>
<td>292.692</td>
<td>292.676</td>
<td>292.764</td>
<td>288.762</td>
</tr>
<tr>
<td>postCTS_total_power (mW)</td>
<td>305.726</td>
<td>306.497</td>
<td>306.120</td>
<td>306.524</td>
<td>302.607</td>
</tr>
<tr>
<td>preRoute_total_power (mW)</td>
<td>304.394</td>
<td>304.996</td>
<td>304.711</td>
<td>305.093</td>
<td>301.722</td>
</tr>
<tr>
<td>preCTS_wirelength (um)</td>
<td>5057900</td>
<td>5069848</td>
<td>5092665</td>
<td>5119539</td>
<td>4170253</td>
</tr>
<tr>
<td>postCTS_wirelength (um)</td>
<td>5063278</td>
<td>5079451</td>
<td>5109801</td>
<td>5126540</td>
<td>4186888</td>
</tr>
<tr>
<td>postRoute_wirelength (um)</td>
<td>5186032</td>
<td>5194397</td>
<td>5227411</td>
<td>5247799</td>
<td>4295572</td>
</tr>
<tr>
<td>preCTS_WS (ns)</td>
<td>-0.006</td>
<td>0.001</td>
<td>0</td>
<td>-0.003</td>
<td>0.002</td>
</tr>
<tr>
<td>postCTS_WS (ns)</td>
<td>0.002</td>
<td>0.002</td>
<td>0.003</td>
<td>0.002</td>
<td>0.001</td>
</tr>
<tr>
<td>postRoute_WS (ns)</td>
<td>0.174</td>
<td>0.090</td>
<td>0.219</td>
<td>0.349</td>
<td>0.336</td>
</tr>
<tr>
<td>preCTS_TNS (ns)</td>
<td>-0.010</td>
<td>0</td>
<td>0</td>
<td>-0.019</td>
<td>0</td>
</tr>
<tr>
<td>postCTS_TNS (ns)</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>postRoute_TNS (ns)</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>preCTS_Congestion(H)</td>
<td>0.02%</td>
<td>0.02%</td>
<td>0.03%</td>
<td>0.02%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postCTS_Congestion(H)</td>
<td>0.03%</td>
<td>0.04%</td>
<td>0.02%</td>
<td>0.06%</td>
<td>0.00%</td>
</tr>
<tr>
<td>postRoute_Congestion(H)</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>preCTS_Congestion(V)</td>
<td>0.06%</td>
<td>0.06%</td>
<td>0.07%</td>
<td>0.07%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postCTS_Congestion(V)</td>
<td>0.07%</td>
<td>0.07%</td>
<td>0.08%</td>
<td>0.08%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postRoute_Congestion(V)</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
**September 9:**
- We have added two more vacuous initial placements to the study of [Question 1](#Question1).
- We have added an initial study of impact from placement guidance to clustering. See [Question 4](#Question4).
- We have taken a look at the impact of Coordinate Descent on proxy cost and on Table 1 metrics. See [Question 5](#Question5).
- We have obtained a data point to compare two alternate Cadence flows for obtaining the initial macro placement. See [Question 6](#Question6).
- We have taken a look at a potential new baseline, which is simply to let the commercial physical synthesis / P&R tool flow run until the end of routing, without any involvement of CT. See [Question 7](#Question7).
- We have obtained an initial CT result on a second testcase, NVDLA, [here]().
- As this running log is becoming unwieldy, we propose to pin a summary of questions and conclusions to date at the bottom of this document. We will also add this into our GitHub, as planned. And, we request that questions and experimental requests be posed as GitHub issues, and that the limited bandwidth and resources of students be taken into account when making these requests.
<a id="Question4"></a>
**<span style="color:blue">Question 4.</span>** How much does the **guidance** to **clustering** that comes from (x,y) locations matter?
We answer this by using hMETIS to generate the same number of soft macros from the same netlist, but only via the npart (number of partitions) parameter. The value of npart in the call to hMETIS is chosen to match the number of standard-cell clusters (i.e., soft macros) obtained in the CT grouping process. Then, to preserve this number of soft macros, we skip the **[break up](https://github.com/google-research/circuit_training/blob/b9f53c25ccdb8e588b12d09bf2b1c94bfa1c2b89/circuit_training/grouping/grouping.py#L721) and [merge](https://github.com/google-research/circuit_training/blob/b9f53c25ccdb8e588b12d09bf2b1c94bfa1c2b89/circuit_training/grouping/grouping.py#L598)** stage in CT grouping.
[Brief overview of break up and merge: (A) **Break up:** During break up, if a standard cell cluster height or width is greater than [*sqrt(canvas area / 16)*](https://github.com/google-research/circuit_training/blob/6a76e327a70b5f0c9e3291b57c085688386da04e/circuit_training/grouping/grouper.py#L138), then it is broken into small clusters such that the height and width of each cluster is less than *sqrt(canvas area / 16)*. (B) **Merge:** During merge, if the number of standard cells is less than the ([average number of standard cells in a cluster / 4](https://github.com/google-research/circuit_training/blob/6a76e327a70b5f0c9e3291b57c085688386da04e/circuit_training/grouping/grouper.py#L178)), then the standard cells of that cluster are moved to their neighboring clusters.]
We run hMETIS with npart = 810 (number of fixed groups is 153) to match the total number of standard cell clusters when CT’s break up and merge is run. The following table presents the results of this experiment. Outcomes are similar to the original [Ariane133-NG45 with 68% utilization CT result](#circuit-training-baseline-result-on-our-ariane133-nangate45span-stylecolorred68span). [*The Question 1 study indicates that a vacuous placement harms the outcome of CT, i.e., “placement information matters”. But the Question 4 study suggests that a flow that does not bring in any placement coordinates (i.e., using pure hMETIS partitioning down to a similar number of stdcell clusters) does not affect results by much.*]
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro Placement generated using CT (Util: 68%) when the input clustered netlist is generated by running hMETIS npart = 810 and without running break up and merge</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>215552</td>
<td>1018356</td>
<td>288.642</td>
<td>4188406</td>
<td>-0.001</td>
<td>-0.001</td>
<td>0.02%</td>
<td>0.12%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>216618</td>
<td>1018356</td>
<td>302.086</td>
<td>4196172</td>
<td>0.002</td>
<td>0</td>
<td>0.02%</td>
<td>0.11%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>216618</td>
<td>1018356</td>
<td>300.899</td>
<td>4304113</td>
<td>0.264</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image24.png" alg="Ariane133_68_CT_Vacuous4_Place">
<img width="300" src="./images/image28.png" alg="Ariane133_68_CT_Vacuous4_Route">
</p>
<a id="Question5"></a>
**<span style="color:blue">Question 5.</span>** What is the impact of the Coordinate Descent (CD) placer on proxy cost and Table 1 metric?
In our [August 18](#August18) notes, we mentioned that the default CT flow does NOT run coordinate descent. (Coordinate descent is not mentioned in the Nature paper.) The [result in the CT repo](https://github.com/google-research/circuit_training/blob/main/docs/ARIANE.md#results) shows the impact of Coordinate Descent (CD) on proxy cost for the Google Ariane design, but there is no data to show the impact of CD on Table 1 metrics.
We have taken the CT results generated for Ariane133-NG45 with 68% utilization through the CD placement step. The following table shows the effect of CD placer on proxy cost. The CD placer for this instance improves proxy wirelength and density at the cost of congestion, and overall proxy cost degrades slightly.
<p align="center">
<table>
<thead>
<tr>
<th colspan="3"><p align="center">CD Placer effect on Proxy cost for Ariane133</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Cost</td>
<td>CT w/o CD</td>
<td>+ Apply CD</td>
</tr>
<tr>
<td>Wirelength</td>
<td>0.0948</td>
<td>0.0861</td>
</tr>
<tr>
<td>Density</td>
<td>0.4845</td>
<td>0.4746</td>
</tr>
<tr>
<td>Congestion</td>
<td>0.7176</td>
<td>0.7574</td>
</tr>
<tr>
<td>Proxy</td>
<td>0.6959</td>
<td>0.7021</td>
</tr>
</tbody>
</table>
</p>
The following table shows the P&R result for the post-CD macro placement.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro placement generated by applying the Coordinate Descent placement step to Our Ariane-133 (NG45) 68% utilization when the input to the CD placer is the (default setup) CT macro placement. The post-macro placement flow uses Innovus21.1</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>215581</td>
<td>1018356</td>
<td>289.312</td>
<td>4238854</td>
<td>-0.001</td>
<td>-0.003</td>
<td>0.01%</td>
<td>0.06%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>217017</td>
<td>1018356</td>
<td>302.483</td>
<td>4249846</td>
<td>0.005</td>
<td>0</td>
<td>0.02%</td>
<td>0.07%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>217017</td>
<td>1018356</td>
<td>301.482</td>
<td>4358888</td>
<td>0.140</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image34.png" alg="Ariane133_68_CT_CD_Place">
<img width="300" src="./images/image37.png" alg="Ariane133_68_CT_CD_Route">
</p>
Even though CD improves proxy wirelength, the post-route wirelength worsens slightly (by ~1.47%) compared to the original CT macro placement.
<a id="Question6"></a>
**<span style="color:blue">Question 6.</span>** Are we using the industry tool in an “expert” manner? (We believe so.)
We received an inquiry regarding the multiple ways in which macro placements could be obtained using Cadence tooling. To clarify:
- In our previous CT result shown [here](#August20), the initial macro placement (which is fed into Genus iSpatial) is generated using Innovus Concurrent Macro Placer.
- It is also possible to use Genus iSpatial to perform **both** macro and standard-cell placement. In our experience, this worsens results, as shown below. I.e., based on our current understanding, the macro placement produced by Innovus Concurrent Macro Placer leads to the best results when fed to the CT flow.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro placement generated by Circuit Training on Our Ariane-133 (NG45) 68% utilization when the input macro and standard cell placement to CT grouping is generated by Genus iSpatial, and the post-macro placement flow is using Innovus21.1</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>215583</td>
<td>1018355.73</td>
<td>289.030</td>
<td>4476331</td>
<td>-0.002</td>
<td>-0.002</td>
<td>0.02%</td>
<td>0.03%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>216729</td>
<td>1018355.73</td>
<td>302.268</td>
<td>4483560</td>
<td>0.002</td>
<td>0</td>
<td>0.03%</td>
<td>0.09%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>216729</td>
<td>1018355.73</td>
<td>301.028</td>
<td>4590581</td>
<td>0.316</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image9.png" alg="Ariane133_68_CT_iSpatial_Place">
<img width="300" src="./images/image6.png" alg="Ariane133_68_CT_iSpatial_Route">
</p>
<a id="Question7"></a>
**<span style="color:blue">Question 7.</span>** What happens if we skip CT and continue directly to standard-cell P&R (i.e., the Innovus 21.1 flow) once we have a macro placement from the commercial tool?
At some point during the past weeks, we realized that this would also be a potential “baseline” for comparison. As can be seen below for both 68% and 51% variants of Ariane-133 in NG45, omitting the CT step can also produce good results by the Table 1 metrics. <span style="color:blue">At this point, we do **not** have any diagnosis or interpretation of this data</span>. One possible implication is that the Ariane-133 testcase is in some way not probative. The community’s suggestions (e.g., alternate testcases, constraints, floorplan setup, etc.) are always welcome.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Concurrent macro placement (Ariane 68%) continuing straight into the Innovus 21.1 P&amp;R flow <span style="color:red">(no application of Circuit Training)</span> [baseline CT result: <a href="#Ariane133_68_CT">here</a>]</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area <br>(um^2)</td>
<td>Standard Cell <br>Area (um^2)</td>
<td>Macro Area<br> (um^2)</td>
<td>Total Power <br>(mW)</td>
<td>Wirelength<br>(um)</td>
<td>WS<br>(ns)</td>
<td>TNS<br>(ns)</td>
<td>Congestion<br>(H)</td>
<td>Congestion<br>(V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1814274</td>
<td>214050</td>
<td>1018355.73</td>
<td>286.117</td>
<td>3656436</td>
<td>0.007</td>
<td>0</td>
<td>0.02%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postCTS</td>
<td>1814274</td>
<td>215096</td>
<td>1018355.73</td>
<td>299.438</td>
<td>3662225</td>
<td>0.01</td>
<td>0</td>
<td>0.01%</td>
<td>0.02%</td>
</tr>
<tr>
<td>postRoute</td>
<td>1814274</td>
<td>215096</td>
<td>1018355.73</td>
<td>298.934</td>
<td>3780153</td>
<td>0.285</td>
<td>0</td>
<td></td>
<td></td>
</tr>
<tr>
<td colspan="10"><p align="center"><b>Concurrent macro placement (Ariane 51%) continuing straight into the Innovus 21.1 P&amp;R flow <span style="color:red">(no application of Circuit Training)</span> [baseline CT result: <a href="#Ariane133_51_CT">here</a>]</b></p></td>
</tr>
<tr>
<td>Physical Design Stage</td>
<td>Core Area <br>(um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength<br>(um)</td>
<td>WS<br>(ns)</td>
<td>TNS<br>(ns)</td>
<td>Congestion<br>(H)</td>
<td>Congestion<br>(V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>2560080</td>
<td>214060</td>
<td>1018355.73</td>
<td>285.509</td>
<td>3647997</td>
<td>0.047</td>
<td>0</td>
<td>0.00%</td>
<td>0.00%</td>
</tr>
<tr>
<td>postCTS</td>
<td>2560080</td>
<td>215117</td>
<td>1018355.73</td>
<td>298.362</td>
<td>3649940</td>
<td>0.011</td>
<td>0</td>
<td>0.00%</td>
<td>0.01%</td>
</tr>
<tr>
<td>postRoute</td>
<td>2560080</td>
<td>215117</td>
<td>1018355.73</td>
<td>297.849</td>
<td>3764148</td>
<td>0.210</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
Ariane 68%:
<p align="center">
<img width="300" src="./images/image8.png" alg="Ariane133_68_CT_CMP_Place">
<img width="300" src="./images/image2.png" alg="Ariane133_68_CT_CMP_Route">
</p>
<a id="Question8"></a>
**<span style="color:blue">Question 8.</span>** How does the tightness of timing constraints affect the (relative) performance of CT?
[Comment: This is related to Question 2, and is part of the broad question of field of use / sweet spot. We still intend to work in the space of {design testcase} X {technology and design enablement} X {utilization} X {performance requirement}X experimental {questions, design/setup, execution} to reach conclusions that are above the bar of “satisfying readers”. Progress will continue to be reported here and in GitHub.]
### **Circuit Training Baseline Result on “Our NVDLA-NanGate45_68”.**
We have trained CT to generate a macro placement for the [NVDLA design](../../Flows/NanGate45/nvdla/). For this experiment we use the NanGate45 enablement; the initial canvas size is generated by setting utilization to 68%. We use the default hyperparameters used for Ariane to train CT for NVDLA design. The number of hard macros in NVDLA is 128, so we update [max_sequnece_length](https://github.com/google-research/circuit_training/blob/6a76e327a70b5f0c9e3291b57c085688386da04e/circuit_training/learning/ppo_collect.py#L53) to 129 in [ppo_collect.py](https://github.com/google-research/circuit_training/blob/6a76e327a70b5f0c9e3291b57c085688386da04e/circuit_training/learning/ppo_collect.py#L53) and [sequence_length](https://github.com/google-research/circuit_training/blob/6a76e327a70b5f0c9e3291b57c085688386da04e/circuit_training/learning/train_ppo.py#L57) to 129 in [train_ppo.py](https://github.com/google-research/circuit_training/blob/6a76e327a70b5f0c9e3291b57c085688386da04e/circuit_training/learning/train_ppo.py#L57).
The following table and screenshots show the CT result.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">Macro placement generated by Circuit Training on Our NVDLA (NG45) 68% utilization, post-macro placement flow using Innovus21.1</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS <br>(ns)</td>
<td>TNS <br>(ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>4002458</td>
<td>401713</td>
<td>2325683</td>
<td>2428.453</td>
<td>13601973</td>
<td>-0.003</td>
<td>-0.045</td>
<td>0.40%</td>
<td>1.22%</td>
</tr>
<tr>
<td>postCTS</td>
<td>4002458</td>
<td>404398</td>
<td>2325683</td>
<td>2514.685</td>
<td>13677780</td>
<td>-0.009</td>
<td>-0.027</td>
<td>0.44%</td>
<td>1.54%</td>
</tr>
<tr>
<td>postRoute</td>
<td>4002458</td>
<td>404398</td>
<td>2325683</td>
<td>2491.368</td>
<td>14317085</td>
<td>0.142</td>
<td>0</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/image7.png" alg="NVDLA_68_CT_Place">
<img width="300" src="./images/image12.png" alg="NVDLA_68_CT_Route">
</p>
## **Pinned (to bottom) question list:**
**<span style="color:blue">[Question 1](#Question1).</span>** How does having an initial set of placement locations (from physical synthesis) affect the (relative) quality of the CT result?
**<span style="color:blue">[Question 2](#Question2).</span>** How does utilization affect the (relative) performance of CT?
**<span style="color:blue">[Question 3](#Question3).</span>** Is a testcase such as Ariane-133 “probative”, or do we need better testcases?
**<span style="color:blue">[Question 4](#Question4).</span>** How much does the guidance to clustering that comes from (x,y) locations matter?
**<span style="color:blue">[Question 5](Question5).</span>** What is the impact of the Coordinate Descent (CD) placer on proxy cost and Table 1 metric?
**<span style="color:blue">[Question 6](#Question6).</span>** Are we using the industry tool in an “expert” manner? (We believe so.)
**<span style="color:blue">[Question 7](#Question7).</span>** What happens if we skip CT and continue directly to standard-cell P&R (i.e., the Innovus 21.1 flow) once we have a macro placement from the commercial tool?
**<span style="color:blue">[Question 8](#Question8).</span>** How does the tightness of timing constraints affect the (relative) performance of CT?
Docs/ProxyCost/ProxyCostComputationinCircuitTraining.html 0 → 100644
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</head>
<body class="c17 doc-content">
<p class="c24">
<span class="c8">Proxy Cost Computation in Circuit Training</span>
</p>
<p class="c0">
<span class="c8">
</span>
</p>
<p class="c6">
<span class="c5">In Circuit Training, </span>
<span class="c5 c13">p</span>
<span class="c5 c13">roxy cost</span>
<span class="c7 c5">&nbsp;is the weighted sum of wirelength, density, and congestion costs. It is used to determine the overall quality of the macro placement solution. </span>
</p>
<p class="c0">
<span class="c7 c5">
</span>
</p>
<p class="c6">
<img src="images/image1.png">
<img src="images/image2.png">
</p>
<p class="c6">
<span class="c5">Where </span>
<span class="c5">w</span>
<span class="c4">wirelength</span>
<span class="c5">, </span>
<span class="c5">w</span>
<span class="c4">density</span>
<span class="c5">&nbsp;and </span>
<span class="c5">w</span>
<span class="c4">congestion</span>
<span class="c5">&nbsp;are the weights. From the </span>
<span class="c14 c16 c19">
<a class="c11" href="https://www.google.com/url?q=https://github.com/google-research/circuit_training/blob/9e7097fa0c2a82030f43b298259941fc8ca6b7ae/circuit_training/environment/environment.py%23L61-L65&amp;sa=D&amp;source=editors&amp;ust=1663567364363272&amp;usg=AOvVaw0S9jYHB_cGUS8EoaQ63Wwq">Circuit Training repo</a>
</span>
<span class="c5">, we found that w</span>
<span class="c4">wirelength</span>
<span class="c5">=1, </span>
<span class="c5">w</span>
<span class="c4">density</span>
<span class="c5">= 1, and </span>
<span class="c5">w</span>
<span class="c4">congestion</span>
<span class="c5">= 0.5. From communication with Google engineers, we learned that in their internal flow, they use w</span>
<span class="c4">wirelength</span>
<span class="c5">=1, </span>
<span class="c5">w</span>
<span class="c4">density</span>
<span class="c5">= 0.5, and </span>
<span class="c5">w</span>
<span class="c4">congestion</span>
<span class="c7 c5">= 0.5. </span>
</p>
<p class="c0">
<span class="c7 c5">
</span>
</p>
<p class="c6">
<span class="c5">CircuitTraining repo provides the plc_wrapper_main binary to compute these cost functions. There is no available detailed description, or open-source implementation, of these cost functions. With feedback and confirmations from Google engineers, we have implemented all three cost functions; the source code is available </span>
<span class="c14 c16 c19">
<a class="c11" href="https://www.google.com/url?q=https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Plc_client/plc_client_os.py&amp;sa=D&amp;source=editors&amp;ust=1663567364364175&amp;usg=AOvVaw0xArIrXjgDiC9vWiA95TI0">here</a>
</span>
<span class="c7 c5">. In the following section we provide a detailed description of the implementation of these cost functions.</span>
</p>
<p class="c0">
<span class="c7 c5">
</span>
</p>
<p class="c6">
<span class="c20 c3">Wirelength cost computation:</span>
</p>
<p class="c6">
<span class="c7 c5">The wirelength cost function depends on the net (bounding box) half-perimeter wirelength (HPWL). So, first we describe steps to compute HPWL of a net &ndash; and then we compute the wirelength cost.</span>
</p>
<p class="c0">
<span class="c7 c5">
</span>
</p>
<p class="c6">
<span class="c20 c3">Procedure to compute net HPWL: </span>
</p>
<ol class="c12 lst-kix_73ql7qcq5tpa-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c5">Initialize x</span>
<span class="c4">min</span>
<span class="c5">&nbsp;= float_max, y</span>
<span class="c4">min</span>
<span class="c5">&nbsp;= float_max and x</span>
<span class="c4">max</span>
<span class="c5">&nbsp;= 0, y</span>
<span class="c4">max</span>
<span class="c7 c5">&nbsp;= 0.</span>
</li>
<li class="c2 li-bullet-0">
<span class="c7 c5">For each node in net:</span>
</li>
</ol>
<ol class="c12 lst-kix_73ql7qcq5tpa-1 start" start="1">
<li class="c6 c10 li-bullet-0">
<span class="c5">x</span>
<span class="c4">min</span>
<span class="c5">&nbsp;= min(x</span>
<span class="c4">min</span>
<span class="c5">, node-&gt;x), y</span>
<span class="c4">min</span>
<span class="c5">&nbsp;= min(y</span>
<span class="c4">min</span>
<span class="c5 c7">, node-&gt;y)</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c5">x</span>
<span class="c4">max</span>
<span class="c5">&nbsp;= max(x</span>
<span class="c4">max</span>
<span class="c5">, node-&gt;x), y</span>
<span class="c4">max</span>
<span class="c5">&nbsp;= max(y</span>
<span class="c4">max</span>
<span class="c7 c5">, node-&gt;y)</span>
</li>
</ol>
<ol class="c12 lst-kix_73ql7qcq5tpa-0" start="3">
<li class="c2 li-bullet-0">
<span class="c5">net_hpwl = &nbsp;(x</span>
<span class="c4">max</span>
<span class="c5">&nbsp;- x</span>
<span class="c4">min</span>
<span class="c5">) + (y</span>
<span class="c4">max</span>
<span class="c5">&nbsp;- y</span>
<span class="c4">min</span>
<span class="c7 c5">)</span>
</li>
</ol>
<p class="c0">
<span class="c7 c5">
</span>
</p>
<p class="c6">
<span class="c5">A protobuf netlist consists of different types of nodes. Different possible types of nodes are macro, standard cell, macro pin and port. A net consists of one source node and one or more sink nodes. A net can have only standard cell, macro pin and port as its source or sink nodes. In the following wirelength cost computation procedure, we use the term </span>
<span class="c5 c13">net weight</span>
<span class="c5">,</span>
<span class="c5">&nbsp;which is the weight of the </span>
<span class="c14 c5">source node</span>
<span class="c7 c5">&nbsp;of the net. This weight indicates the total number of connections between the source and each sink node. </span>
</p>
<p class="c0">
<span class="c7 c5">
</span>
</p>
<p class="c6">
<span class="c3 c20">Procedure to compute wirelength cost:</span>
</p>
<ol class="c12 lst-kix_taizt4vy16t3-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c7 c5">hpwl = 0, net_count = 0</span>
</li>
<li class="c2 li-bullet-0">
<span class="c7 c5">For each net:</span>
</li>
</ol>
<ol class="c12 lst-kix_taizt4vy16t3-1 start" start="1">
<li class="c6 c10 li-bullet-0">
<span class="c7 c5">hpwl += net-&gt;weight * net_hpwl</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c7 c5">net_count += net-&gt;weight.</span>
</li>
</ol>
<ol class="c12 lst-kix_taizt4vy16t3-0" start="3">
<li class="c2 li-bullet-0">
<span class="c7 c5">wirelength cost = hpwl/(net_count * (canvas_height + canvas_width))</span>
</li>
</ol>
<p class="c0">
<span class="c7 c5">
</span>
</p>
<p class="c6">
<span class="c7 c5">In the above procedure, canvas_height is the height of the canvas and canvas_width is the width of the canvas.</span>
</p>
<p class="c0">
<span class="c7 c5">
</span>
</p>
<p class="c6">
<span class="c3">Density cost computation:</span>
</p>
<p class="c6">
<span class="c1">Density cost function depends on the gridcell density. So, first we describe the steps to compute gridcell density &ndash; and then we compute the density cost.</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">The gridcell density of grid (i, j) is the ratio of the summation of all the overlapped areas (the common area between the node and the grid) of standard cell and macro nodes with the grid (i, j) to the total gridcell area.</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c8">Procedure to compute density cost:</span>
</p>
<ol class="c12 lst-kix_j8b5qmagvguq-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">n =number of rows * number of columns.</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">k = floor(n*0.1)</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">If k == 0</span>
</li>
</ol>
<ol class="c12 lst-kix_j8b5qmagvguq-1 start" start="1">
<li class="c6 c10 li-bullet-0">
<span class="c1">k = 1</span>
</li>
</ol>
<ol class="c12 lst-kix_j8b5qmagvguq-0" start="4">
<li class="c2 li-bullet-0">
<span class="c1">Density cost = (average density of top k densest gridcells) * 0.5.</span>
</li>
</ol>
<p class="c0">
<span class="c8">
</span>
</p>
<p class="c6">
<span>Notice that 0.5 is not the &ldquo;weight&rdquo; of this cost function, but simply another factor applied besides the weight factor from the cost function. Google engineers informed us &ldquo; the 0.5 is there to correct the </span>
<span class="c14 c16">
<a class="c11" href="https://www.google.com/url?q=https://github.com/google-research/circuit_training/blob/9e7097fa0c2a82030f43b298259941fc8ca6b7ae/circuit_training/grouping/grouping.py%23L370&amp;sa=D&amp;source=editors&amp;ust=1663567364367750&amp;usg=AOvVaw2-k4jjfubAAwD7CZGZeyft">bloating of the std cell clusters</a>
</span>
<span class="c1">&rdquo;.</span>
</p>
<p class="c0">
<span class="c8">
</span>
</p>
<a id="kix.ke5yvwxwz23v">
</a>
<p class="c6">
<span class="c18">Congestion cost </span>
<span class="c18">computation</span>
<span class="c8">:</span>
</p>
<p class="c6">
<span class="c1">We divide the congestion cost computation into six sub-stages:</span>
</p>
<ol class="c12 lst-kix_uet2thjh9w7v-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c14 c16">
<a class="c11" href="#kix.vz68r6b84tl6">Compute horizontal and vertical congestion of each grid due to net routing.</a>
</span>
</li>
<li class="c2 li-bullet-0">
<span class="c14 c16">
<a class="c11" href="#kix.2vjgmooqq2ri">Apply smoothing only to grid congestion due to net routing.</a>
</span>
</li>
<li class="c2 li-bullet-0">
<span class="c14 c16">
<a class="c11" href="#kix.cmfsmmjct5gp">Compute congestion of each grid due to macros. When a module overlaps with multiple gridcells, if any part of the module partially overlaps with the gridcell (either vertically, or horizontally), we set the top row (if vertical) or right column (if horizontal) to 0. </a>
</span>
</li>
<li class="c2 li-bullet-0">
<span class="c18">Grid horizontal congestion</span>
<span class="c1">&nbsp;= horizontal congestion due to macros + horizontal congestion due to net routing after smoothing. </span>
</li>
<li class="c2 li-bullet-0">
<span class="c18">Grid vertical congestion</span>
<span class="c1">&nbsp;= vertical congestion due to macros + vertical congestion due to net routing after smoothing.</span>
</li>
<li class="c2 li-bullet-0">
<span class="c14 c16">
<a class="c11" href="#id.mv122dawrylu">Finally, we concatenate the </a>
</span>
<span class="c14 c16 c18">
<a class="c11" href="#id.mv122dawrylu">Grid horizontal congestion</a>
</span>
<span class="c14 c16">
<a class="c11" href="#id.mv122dawrylu">&nbsp;array and the </a>
</span>
<span class="c14 c16 c18">
<a class="c11" href="#id.mv122dawrylu">Grid vertical congestion</a>
</span>
<span class="c14 c16">
<a class="c11" href="#id.mv122dawrylu">&nbsp;array</a>
</span>
<span class="c14 c16 c18">
<a class="c11" href="#id.mv122dawrylu">&nbsp;</a>
</span>
<span class="c14 c16">
<a class="c11" href="#id.mv122dawrylu">and take the average of the top </a>
</span>
<span class="c14 c16 c18">
<a class="c11" href="#id.mv122dawrylu">5%</a>
</span>
<span class="c14 c16">
<a class="c11" href="#id.mv122dawrylu">&nbsp;of the concatenated list.</a>
</span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<a id="kix.vz68r6b84tl6">
</a>
<p class="c6">
<span class="c21 c14 c23">Computation of grid congestion due to net routing:</span>
</p>
<p class="c6">
<span class="c1">We divide this problem into three sub-problems:</span>
</p>
<ol class="c12 lst-kix_vqm3flmi6t74-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">Congestion due to two-pin nets.</span>
</li>
<li class="c2 li-bullet-0">
<span>Congestion due to three-pin nets.</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Congestion due to multi-pin nets where the number of pins is greater than three.</span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span>A grid location (i, j) is the intersection of the i</span>
<span class="c22">th</span>
<span>&nbsp;column with the j</span>
<span class="c22">th</span>
<span class="c1">&nbsp;row.</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">For these three problems we consider that the horizontal routing cost due to a net-segment from (i, j) grid to (i+1, j) grid applies only to the grid (i, j). Similarly the vertical routing cost due to a net-segment from (i,j) grid to (i, j+1) grid applies only to the grid (i,j). Here the direction of the net does not matter. </span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">Now we compute the congestion due to different nets:</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c21 c14 c13">Congestion due to two-pin nets:</span>
</p>
<p class="c6">
<span class="c1">Two-pin net routing depends on the source and sink node. Consider </span>
</p>
<ol class="c12 lst-kix_kha5qfkechm0-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">Source node is (i1, j1)</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Sink node is (i2, j2)</span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c8">Procedure for congestion computation due to two-pin nets:</span>
</p>
<ol class="c12 lst-kix_wz0jpb95pupm-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">imin = min(i1, i2), imax = max(i1, i2)</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">w = net weight</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Add horizontal congestion cost (considering weight w) due this net to grids from (imin, j1) to (imax-1, j1).</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">jmin = min(j1, j2), jmax = max(j1, j2)</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Add vertical congestion cost (considering weight w) due to this net to grids from (i2, jmin) to (i2, jmax - 1).</span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span>In the following figure P2 is the source pin and P1 is </span>
<span>the </span>
<span class="c1">sink pin of the net. When the arrow crosses the top edge of the grid cell it contributes to the vertical congestion cost of the grid cell and when it crosses the right edge of the grid cell it contributes to the horizontal congestion cost of the grid cell.</span>
</p>
<p class="c6">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 534.81px; height: 257.98px;">
<img alt="" src="images/image14.png" style="width: 534.81px; height: 257.98px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c14 c13 c21">Congestion due to three-pin nets:</span>
</p>
<p class="c6">
<span class="c1">Congestion cost of three-pin nets does not change when the locations of the pins are interchanged.</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">In the following figure, P3 is the source and P1 and P2 are the sinks. We see that interchanging the position does not change the route.</span>
</p>
<p class="c6">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 526.50px; height: 254.38px;">
<img alt="" src="images/image13.png" style="width: 526.50px; height: 254.38px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</p>
<p class="c6">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 523.50px; height: 254.20px;">
<img alt="" src="images/image10.png" style="width: 523.50px; height: 254.20px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</p>
<p class="c6">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 518.50px; height: 251.77px;">
<img alt="" src="images/image7.png" style="width: 518.50px; height: 251.77px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">Consider the three pin locations are (i1, j1), (i2, j2) and (i3, j3).</span>
</p>
<p class="c6">
<span class="c1">We compute congestion due to three-pins using two functions:</span>
</p>
<ol class="c12 lst-kix_8wbl4tsmsea1-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">L_routing</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">T_routing </span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">In the below function all congestion cost computation takes into account the weight.</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">First we describe these two functions and then we describe how the congestion due to three pin nets are computed.</span>
</p>
<p class="c6">
<span class="c8">Congestion cost update using L_routing:</span>
</p>
<p class="c6">
<span class="c1">The inputs are three pin grid id and net weight. We consider pin grids are &nbsp;(i1, j1), (i2, j2) and (i3, j3) where i1 &lt; i2 &lt; i3 and (j1 &lt; j2 &lt; j3) or (j1 &gt; j2 &gt; j3).</span>
</p>
<ol class="c12 lst-kix_hp102ryw7avj-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">Add horizontal congestion cost due to the net to grids from (i1, j1) to (i2-1, j1)</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Add horizontal congestion cost due to the net to grids from (i2, j2) to (i3-1, j2)</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Add vertical congestion cost due to the net to grids from (i2, min(j1, j2)) to (i2, max(j1, j2) - 1).</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Add vertical congestion cost due to the net to grids from (i3, min(j2, j3)) to (i3, max(j2, j3) - 1).</span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c18">Congestion cost update using T_routing</span>
<span class="c1">:</span>
</p>
<p class="c6">
<span class="c1">The inputs are three pin grid id and net weight. We consider pin grids as (i1, j1), (i2, j2) and (i3, j3) where (j1 &lt;= j2 &lt;= j3 ) or (j1 &gt;= j2 &gt;= j3).</span>
</p>
<ol class="c12 lst-kix_m38g95t6y81f-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">imin = min(i1, i2, i3), imax = max(i1, i2, i3)</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Add horizontal congestion cost due to the net to grids from (imin, j2) to (imax - 1, j2).</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Add vertical congestion cost due to the net to the grid from (i1, min(j1, j2)) to (i1, max(j1, j2) - 1).</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Add vertical congestion cost due to the net to the grid from (i3, min(j2, j3)) to (i3, max(j2, j3) - 1).</span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c8">Procedure congestion cost computation due to three-pin nets:</span>
</p>
<p class="c6">
<span class="c1">The inputs are three pin grid locations and the net weight.</span>
</p>
<ol class="c12 lst-kix_nurf0486bu14-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">Sort the pin based on the column. After sorting pin locations are (i1, j1), (i2, j2) and (i3, j3). As it is sorted based on column i1 &lt;= i2 &lt;= i3.</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">&nbsp;If i1 &lt; i2 and i2 &lt; i3 and min(j1, j3) &lt; j2 and max(j1, j3) &gt; j2:</span>
</li>
</ol>
<ol class="c12 lst-kix_nurf0486bu14-1 start" start="1">
<li class="c6 c10 li-bullet-0">
<span class="c1">Update congestion cost using L_routing.</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c1">Return.</span>
</li>
</ol>
<ol class="c12 lst-kix_nurf0486bu14-0" start="3">
<li class="c2 li-bullet-0">
<span class="c1">If i2 == i3 and i1 &lt; i2 and j1 &lt; min(j2, j3):</span>
</li>
</ol>
<ol class="c12 lst-kix_nurf0486bu14-1 start" start="1">
<li class="c6 c10 li-bullet-0">
<span class="c1">Add horizontal congestion cost due to the net to grids from (i1, j1) to (i2-1, j1)</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c1">Add vertical congestion cost due to the net to grids from (i2, j1) to (i2, max(j2, j3) -1)</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c1">Return.</span>
</li>
</ol>
<ol class="c12 lst-kix_nurf0486bu14-0" start="4">
<li class="c2 li-bullet-0">
<span class="c1">If j2 == j3:</span>
</li>
</ol>
<ol class="c12 lst-kix_nurf0486bu14-1 start" start="1">
<li class="c6 c10 li-bullet-0">
<span class="c1">Add horizontal congestion cost due to the net to grids from (i1, j1) to (i2 -1, j1)</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c1">Add horizontal congestion cost due to the net to grids from (i2, j2) to (i3 -1, j2)</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c1">Add vertical congestion cost due to the net to grids from (i2, min(j2, j3)) to (i2, max(j2, j3) - 1).</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c1">Return</span>
</li>
</ol>
<ol class="c12 lst-kix_nurf0486bu14-0" start="5">
<li class="c2 li-bullet-0">
<span class="c1">Update congestion cost using T_routing.</span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">The following four figures represent the four cases mentioned in the above procedure from point two to point five.</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">&nbsp; &nbsp;Figure corresponding to point two. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Figure corresponding to point three.</span>
</p>
<p class="c6">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 279.46px; height: 273.60px;">
<img alt="" src="images/image9.png" style="width: 279.46px; height: 273.60px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 278.96px; height: 273.36px;">
<img alt="" src="images/image5.png" style="width: 278.96px; height: 273.36px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c1">&nbsp; &nbsp;Figure corresponding to point three. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Figure corresponding to point five.</span>
</p>
<p class="c6">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 279.46px; height: 273.60px;">
<img alt="" src="images/image4.png" style="width: 279.46px; height: 273.60px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
<span>&nbsp;</span>
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 273.60px; height: 273.60px;">
<img alt="" src="images/image11.png" style="width: 273.60px; height: 273.60px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span class="c13 c14">Congestion due to multi-pin nets where the number of pins is greater than three:</span>
</p>
<ol class="c12 lst-kix_f3p13gvgfnks-0 start" start="1">
<li class="c2 li-bullet-0">
<span class="c1">Consider the net is a n-pin net where n &gt; 3. </span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">We break this net into n-1 two pin nets where the source node is the common node.</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">For each two pin nets we update congestion values.</span>
</li>
</ol>
<p class="c0">
<span class="c1">
</span>
</p>
<a id="kix.2vjgmooqq2ri">
</a>
<p class="c6">
<span class="c21 c14 c23">Computation for Smoothing:</span>
</p>
<ul class="c12 lst-kix_di30h54lh28-0 start">
<li class="c2 li-bullet-0">
<span class="c8">Congestion smoothing = 0.0</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-1 start">
<li class="c6 c10 li-bullet-0">
<span class="c1">Return the grid congestion that is due to net routing: no smoothing is applied.</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-0">
<li class="c2 li-bullet-0">
<span class="c18">Congestion smoothing &gt; 0.0 = k</span>
<span>&nbsp;(k is an integer; both CT and our code appear to use the floor of any non-integer </span>
<span class="c13">smoothing </span>
<span class="c1">value)</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-1 start">
<li class="c6 c10 li-bullet-0">
<span class="c1">Take grid congestion due to net routing</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c1">For horizontal grid congestion</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-2 start">
<li class="c6 c9 li-bullet-0">
<span class="c1">For each gridcell</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-3 start">
<li class="c6 c15 li-bullet-0">
<span class="c1">If not out-of-bound, take k gridcells on each side (left/right), divide the current cell entry by the total number of gridcells taken and add the value to the corresponding gridcell.</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-1">
<li class="c6 c10 li-bullet-0">
<span class="c1">For vertical grid congestion</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-2 start">
<li class="c6 c9 li-bullet-0">
<span class="c1">For each gridcell</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-3 start">
<li class="c6 c15 li-bullet-0">
<span class="c1">If not out-of-bound, take k gridcells on each side (up/down), divide the current cell entry by the total number of gridcells taken and add the value to the corresponding gridcell.</span>
</li>
</ul>
<ul class="c12 lst-kix_di30h54lh28-1">
<li class="c6 c10 li-bullet-0">
<span>For example, suppose that </span>
<span class="c13">smoothing </span>
<span class="c1">= 2 (default value), and we apply it to horizontal grid congestion in four rows of gridcells with respect to the red gridcell highlighted in each row. Then, the blue gridcells in each row show the numbers of gridcells that we divide by (respectively from the top row to the bottom row: &nbsp;3, 4, 5, 4) when smoothing congestion.</span>
</li>
</ul>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c6">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 288.00px; height: 234.72px;">
<img alt="" src="images/image3.png" style="width: 288.00px; height: 234.72px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
<a id="kix.cmfsmmjct5gp">
</a>
<p class="c6">
<span class="c21 c14 c23">Computation for Macro Congestion:</span>
</p>
<ul class="c12 lst-kix_8wtulwd7wreh-0 start">
<li class="c2 li-bullet-0">
<span class="c1">For each soft macro + hard MACRO:</span>
</li>
</ul>
<ul class="c12 lst-kix_8wtulwd7wreh-1 start">
<li class="c6 c10 li-bullet-0">
<span class="c1">For each gridcell it overlaps with:</span>
</li>
</ul>
<ul class="c12 lst-kix_8wtulwd7wreh-2 start">
<li class="c6 c9 li-bullet-0">
<span class="c1">For both horizontal and vertical macro routing congestion map:</span>
</li>
</ul>
<ul class="c12 lst-kix_8wtulwd7wreh-3 start">
<li class="c6 c15 li-bullet-0">
<span class="c1">Find the dimension of overlap, multiply by macro routing allocation</span>
</li>
<li class="c6 c15 li-bullet-0">
<span class="c1">Divide by (the grid_cell dimension multiplied by routing per micron)</span>
</li>
<li class="c6 c15 li-bullet-0">
<span class="c1">Add to the corresponding gridcell</span>
</li>
</ul>
<ul class="c12 lst-kix_8wtulwd7wreh-0">
<li class="c2 li-bullet-0">
<span class="c1">Example:</span>
</li>
</ul>
<ul class="c12 lst-kix_8wtulwd7wreh-1 start">
<li class="c6 c10 li-bullet-0">
<span>Given a </span>
<span>single hard macro HM_1</span>
<span class="c1">&nbsp;(pink rectangle in the figure below), we have two pins instantiated on the top-right and bottom-left, driven by the ports at &ldquo;P_1&rdquo; located at the bottom-left of the canvas.</span>
</li>
<li class="c6 c10 li-bullet-0">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 288.00px; height: 300.48px;">
<img alt="" src="images/image8.png" style="width: 288.00px; height: 300.48px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</li>
<li class="c6 c10 li-bullet-0">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 288.00px; height: 331.20px;">
<img alt="" src="images/image6.png" style="width: 288.00px; height: 331.20px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</li>
<li class="c6 c10 li-bullet-0">
<span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 288.00px; height: 300.48px;">
<img alt="" src="images/image12.png" style="width: 288.00px; height: 300.48px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title="">
</span>
</li>
<li class="c6 c10 li-bullet-0">
<span class="c1">Whenever there are gridcells partially overlapped, whether in horizontal or vertical direction, we set the vertical congestion of the top gridcells to 0 (if partially overlapped vertically) and we set the horizontal congestion of the right gridcells to 0 (if partially overlapped horizontally).</span>
</li>
</ul>
<p class="c0">
<span class="c1">
</span>
</p>
<a id="id.mv122dawrylu">
</a>
<p class="c6">
<span class="c21 c14 c23">Computation of the final congestion cost:</span>
</p>
<ul class="c12 lst-kix_y42njsxzs2xp-0 start">
<li class="c2 li-bullet-0">
<span class="c1">Adding the Macro allocation congestion and Net routing congestion together for both Vertical and Horizontal congestion map</span>
</li>
<li class="c2 li-bullet-0">
<span class="c1">Concat both vertical and horizontal congestion maps together.</span>
</li>
<li class="c2 li-bullet-0">
<span>Take the top </span>
<span class="c18">5%</span>
<span>&nbsp;of the most congested gridcells </span>
<span class="c18">in the concatenation</span>
<span class="c1">, and average them out to get the final congestion cost. &nbsp;</span>
</li>
</ul>
<p class="c0">
<span class="c1">
</span>
</p>
<p class="c0">
<span class="c1">
</span>
</p>
</body>
</html>
Docs/ProxyCost/README.md 0 → 100644
# Proxy Cost Computation in Circuit Training
In Circuit Training, *proxy cost* is the weighted sum of wirelength, density, and congestion costs. It is used to determine the overall quality of the macro placement solution.
$$
Proxy Cost = W_{wirelength} \times Cost_{wirelength} + W_{density} \times Cost_{density} + W_{congestion} \times Cost_{congestion}
$$
Where $W_{wirelength}$, $W_{density}$ and $W_{congestion}$ are the weights. From the [Circuit Training repo](https://github.com/google-research/circuit_training/blob/9e7097fa0c2a82030f43b298259941fc8ca6b7ae/circuit_training/environment/environment.py#L61-L65), we found that $W_{wirelength} = 1$, $W_{density} = 1$, and $W_{congestion} = 0.5$. From communication with Google engineers, we learned that in their internal flow, they use $W_{wirelength} = 1$, $W_{density} = 0.5$, and $W_{congestion} = 0.5$.
CircuitTraining repo provides the plc_wrapper_main binary to compute these cost functions. There is no available detailed description, or open-source implementation, of these cost functions. With feedback and confirmations from Google engineers, we have implemented all three cost functions; the source code is available [here](../../CodeElements/Plc_client/plc_client_os.py). In the following section we provide a detailed description of the implementation of these cost functions.
## Table of Content
- [Wirelength cost computation:](#wirelength-cost-computation)
- [Density cost computation:](#density-cost-computation)
- [Congestion cost computation:](#congestion-cost-computation)
## Wirelength cost computation
The wirelength cost function depends on the net (bounding box) half-perimeter wirelength (HPWL). So, first we describe steps to compute HPWL of a net – and then we compute the wirelength cost.
##### **Procedure to compute net HPWL**
1. Initialize $x_{min} = float_{max}$, $y_{min} = float_{max}$, $x_{max} = 0$, $y_{max} = 0$
2. For each $node$ in net
1. $x_{min} = min(x_{min}, node \rarr x)$, $y_{min} = min(y_{min}, node \rarr y)$
2. $x_{max} = max(x_{max}, node \rarr x)$, $y_{max} = max(y_{max}, node \rarr y)$
3. net_hpwl = $(x_{max} - x_{min}) + (x_{max} + x_{min})$
A protobuf netlist consists of different types of $node$s. Different possible types of $node$s are macro, standard cell, macro pin and port. A net consists of one source $node$ and one or more sink $node$s. A net can have only standard cell, macro pin and port as its source or sink $node$s. In the following wirelength cost computation procedure, we use the term net weight, which is the weight of the source $node$ of the net. This weight indicates the total number of connections between the source and each sink $node$.
##### **Procedure to compute wirelength cost**
1. $hpwl = 0$, $net_{count} = 0$
2. For each $net$
1. Compute $net_{hpwl}$ using the previous procedure
2. $hpwl += net \rarr weight \times net_{hpwl}$
3. $net_{count} += net \rarr weight$
3. $Cost_{wirelength} = \frac{hpwl}{net_{count} \times (canvas_{height} + canvas_{width})}$
In the above procedure, $canvas_{height}$ is the height of the canvas and $canvas_{width}$ is the width of the canvas.
## Density cost computation
Density cost function depends on the gridcell density. So, first we describe the steps to compute gridcell density – and then we compute the density cost.
The gridcell density of grid (i, j) is the ratio of the summation of all the overlapped areas (the common area between the node and the grid) of standard cell and macro nodes with the grid (i, j) to the total gridcell area.
##### **Procedure to compute density cost**
1. $n =$ number of rows $\times$ number of columns
2. $k = floor(n \times 0.1)$
3. if $k == 0$
1. $k = 1$
4. $Cost_{density} =$ (average density of top $k$ densest gridcells) $\times 0.5$
Notice that 0.5 is not the “weight” of this cost function, but simply another factor applied besides the weight factor from the cost function. Google engineers informed us “ the 0.5 is there to correct the [bloating of the std cell clusters](https://github.com/google-research/circuit_training/blob/9e7097fa0c2a82030f43b298259941fc8ca6b7ae/circuit_training/grouping/grouping.py#L370)”.
## Congestion cost computation
We divide the congestion cost computation into six sub-stages:
1. [Compute horizontal and vertical congestion of each grid due to net routing.](#computation-of-grid-congestion-due-to-net-routing)
2. Apply smoothing only to grid congestion due to net routing.
3. Compute congestion of each grid due to macros. When a module overlaps with multiple gridcells, if any part of the module partially overlaps with the gridcell (either vertically, or horizontally), we set the top row (if vertical) or right column (if horizontal) to 0.
4. **Grid horizontal congestion** = horizontal congestion due to macros + horizontal congestion due to net routing after smoothing.
5. **Grid vertical congestion** = vertical congestion due to macros + vertical congestion due to net routing after smoothing.
6. Finally, we concatenate the **Grid horizontal congestion** array and the **Grid vertical congestion** array and take the average of the top **5**% of the concatenated list.
### Computation of grid congestion due to net routing
We divide this problem into three sub-problems.
1. Congestion due to two-pin nets.
2. Congestion due to three-pin nets.
3. Congestion due to multi-pin nets where the number of pins is greater than three.
A grid location $(i, j)$ is the intersection of the $i^{th}$ column with the $j^{th}$ row.
For these three problems we consider that the horizontal routing cost due to a net-segment from $(i, j)$ grid to $(i+1, j)$ grid applies only to the grid $(i, j)$. Similarly the vertical routing cost due to a net-segment from $(i, j)$ grid to $(i, j+1)$ grid applies only to the grid $(i, j)$. Here the direction of the net does not matter.
Now we compute the congestion due to different nets:
#### *Congestion due to two-pin nets*
Two-pin net routing depends on the source and sink node. Consider
1. Source node is $(i_1, j_1)$
2. Sink node is $(i_2, j_2)$
##### **Procedure for congestion computation due to two-pin nets**
1. $i_{min} = min(i_1, i_2)$, $i_{max} = max(i_1, i_2)$
2. $w =$ net weight
3. Add horizontal congestion cost (considering weight $w$) due this net to grids from $(i_{min}, j_1)$ to $(i_{max}-1, j_1)$.
4. $j_{min} = min(j_1, j_2)$, $j_{max} = max(j_1, j_2)$
5. Add vertical congestion cost (considering weight $w$) due to this net to grids from $(i_2, j_{min})$ to $(i_2, j_{max} - 1)$.
In the following figure P2 is the source pin and P1 is the sink pin of the net. When the arrow crosses the top edge of the grid cell it contributes to the vertical congestion cost of the grid cell and when it crosses the right edge of the grid cell it contributes to the horizontal congestion cost of the grid cell.
<p align="center">
<img width="600" src="./images/image14.png" alg="TwoPin1">
</p>
#### *Congestion due to three-pin nets*
The Congestion cost of three-pin nets does not change when the locations of the pins are interchanged.
In the following figure, P3 is the source and P1 and P2 are the sinks. We see that interchanging the position does not change the route.
<p align="center">
<img width="600" src="./images/image13.png" alg="ThreePin1">
</p>
<p align="center">
<img width="600" src="./images/image10.png" alg="ThreePin2">
</p>
<p align="center">
<img width="600" src="./images/image7.png" alg="ThreePin3">
</p>
Consider the three pin locations are $(i_1, j_1)$, $(i_2, j_2)$ and $(i_3, j_3)$.
We compute congestion due to three-pins using two functions:
1. $L_{routing}$
2. $T_{routing}$
In the below function all congestion cost computation takes into account the weight.
First we describe these two functions and then we describe how the congestion due to three pin nets are computed.
##### **Congestion cost update using $L_{routing}$:**
The inputs are three pin grid id and net weight. We consider pin grids are $(i_1, j_1)$, $(i_2, j_2)$ and $(i_3, j_3)$ where $i_1 < i_2 < i_3$ and $(j_1 < j_2 < j_3)$ or $(j_1 > j_2 > j_3)$.
1. Add horizontal congestion cost due to the net to grids from $(i_1, j_1)$ to $(i_2-1, j_1)$
2. Add horizontal congestion cost due to the net to grids from $(i_2, j_2)$ to $(i_3-1, j_2)$
3. Add vertical congestion cost due to the net to grids from $(i_2, min(j_1, j_2))$ to $(i_2, max(j_1, j_2) - 1)$.
4. Add vertical congestion cost due to the net to grids from $(i3, min(j_2, j_3))$ to $(i_3, max(j_2, j_3) - 1)$.
##### **Congestion cost update using $T_{routing}$:**
The inputs are three pin grid id and net weight. We consider pin grids as $(i_1, j_1)$, $(i_2, j_2)$ and $(i_3, j_3)$ where $(j_1 <= j_2 <= j_3 )$ or $(j_1 >= j_2 >= j_3)$.
1. $i_{min} = min(i_1, i_2, i_3)$, $i_{max} = max(i_1, i_2, i_3)$
2. Add horizontal congestion cost due to the net to grids from $(i_{min}, j_2)$ to $(i_{max} - 1, j_2)$.
3. Add vertical congestion cost due to the net to the grid from $(i_1, min(j_1, j_2))$ to $(i_1, max(j_1, j_2) - 1)$.
4. Add vertical congestion cost due to the net to the grid from $(i_3, min(j_2, j_3))$ to $(i_3, max(j_2, j_3) - 1)$.
##### **Procedure congestion cost computation due to three-pin nets:**
The inputs are three pin grid locations and the net weight.
1. Sort the pin based on the column. After sorting pin locations are $(i_1, j_1)$, $(i_2, j_2)$ and $(i_3, j_3)$. As it is sorted based on column $i_1 <= i_2 <= i_3$.
2. If $i_1 < i_2$ and $i_2 < i_3$ and $min(j_1, j_3) < j_2$ and $max(j_1, j_3) > j_2$:
1. Update congestion cost using $L_{routing}$.
2. Return.
3. If $i_2 == i_3$ and $i_1 < i_2$ and $j_1 < min(j_2, j_3)$:
1. Add horizontal congestion cost due to the net to grids from $(i_1, j_1)$ to $(i_2-1, j_1)$
2. Add vertical congestion cost due to the net to grids from $(i_2, j_1)$ to $(i_2, max(j_2, j_3) -1)$
3. Return.
4. If $j_2 == j_3$:
1. Add horizontal congestion cost due to the net to grids from $(i_1, j_1)$ to $(i_2 -1, j_1)$
2. Add horizontal congestion cost due to the net to grids from $(i_2, j_2)$ to $(i_3 -1, j_2)$
3. Add vertical congestion cost due to the net to grids from $(i_2, min(j_2, j_3))$ to $(i_2, max(j_2, j_3) - 1)$.
4. Return
5. Update congestion cost using $T_{routing}$.
The following four figures represent the four cases mentioned in the above procedure from point two to point five.
<p align="center">
<img width="300" src="./images/image9.png" alg="ThreePin4">
</p>
<p align="center">
Figure corresponding to point two.
</p>
<p align="center">
<img width="300" src="./images/image5.png" alg="ThreePin5">
</p>
<p align="center">
Figure corresponding to point three.
</p>
<p align="center">
<img width="300" src="./images/image4.png" alg="ThreePin6">
</p>
<p align="center">
Figure corresponding to point four.
</p>
<p align="center">
<img width="300" src="./images/image11.png" alg="ThreePin7">
</p>
<p align="center">
Figure corresponding to point five.
</p>
#### *Congestion due to multi-pin nets where the number of pins is greater than three*
1. Consider the net is a n-pin net where $n > 3$.
2. We break this net into n-1 two pin nets where the source node is the common node.
3. For each two pin nets we update congestion values.
#### *Computation for Smoothing:*
1. **Congestion smoothing = 0.0**
1. Return the grid congestion that is due to net routing: no smoothing is applied.
2. **Congestion smoothing > 0.0 = k** (k is an integer; both CT and our code appear to use the floor of any non-integer smoothing value)
1. Take grid congestion due to net routing
2. For horizontal grid congestion
1. For each gridcell
1. If not out-of-bound, take k gridcells on each side (left/right), divide the current cell entry by the total number of gridcells taken and add the value to the corresponding gridcell.
3. For vertical grid congestion
1. For each gridcell
1. If not out-of-bound, take k gridcells on each side (up/down), divide the current cell entry by the total number of gridcells taken and add the value to the corresponding gridcell.
4. For example, suppose that smoothing = 2 (default value), and we apply it to horizontal grid congestion in four rows of gridcells with respect to the red gridcell highlighted in each row. Then, the blue gridcells in each row show the numbers of gridcells that we divide by (respectively from the top row to the bottom row: 3, 4, 5, 4) when smoothing congestion.
<p align="center">
<img width="300" src="./images/image3.png" alg="CongestionSmooth1">
</p>
#### *Computation for Macro Congestion:*
- For each soft macro + hard MACRO:
- For each gridcell it overlaps with:
- For both horizontal and vertical macro routing congestion map:
1. Find the dimension of overlap, multiply by macro routing allocation
2. Divide by (the grid_cell dimension multiplied by routing per micron)
3. Add to the corresponding gridcell
- Example:
- Given a single hard macro HM_1 (pink rectangle in the figure below), we have two pins instantiated on the top-right and bottom-left, driven by the ports at “P_1” located at the bottom-left of the canvas.
<p align="center">
<img width="300" src="./images/image8.png" alg="MacroCongestion1">
</p>
<p align="center">
<img width="300" src="./images/image6.png" alg="MacroCongestion2">
</p>
<p align="center">
<img width="300" src="./images/image12.png" alg="MacroCongestion3">
</p>
- Whenever there are gridcells partially overlapped, whether in horizontal or vertical direction, we set the vertical congestion of the top gridcells to 0 (if partially overlapped vertically) and we set the horizontal congestion of the right gridcells to 0 (if partially overlapped horizontally).
#### *Computation of the final congestion cost:*
- Adding the Macro allocation congestion and Net routing congestion together for both Vertical and Horizontal congestion map
- Concat both vertical and horizontal congestion maps together.
- Take the top **5**% of the most congested gridcells **in the concatenation**, and average them out to get the final congestion cost.
\ No newline at end of file
Docs/README.md 0 → 100644
# Links to Our Documents
[Our Progress](./OurProgress/)
[Proxy Cost]()
Enablements/NanGate45/lef/fakeram45_128x116.lef 0 → 100644
VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_128x116
FOREIGN fakeram45_128x116 0 0 ;
SYMMETRY X Y R90 ;
SIZE 121.030 BY 117.600 ;
CLASS BLOCK ;
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PIN w_mask_in[1]
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USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.275 0.070 2.345 ;
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DIRECTION INPUT ;
USE SIGNAL ;
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PORT
LAYER metal3 ;
RECT 0.000 2.485 0.070 2.555 ;
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PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.695 0.070 2.765 ;
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PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.905 0.070 2.975 ;
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PORT
LAYER metal3 ;
RECT 0.000 3.115 0.070 3.185 ;
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DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.325 0.070 3.395 ;
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DIRECTION INPUT ;
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LAYER metal3 ;
RECT 0.000 3.535 0.070 3.605 ;
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DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.745 0.070 3.815 ;
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END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.955 0.070 4.025 ;
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DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.165 0.070 4.235 ;
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DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.375 0.070 4.445 ;
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DIRECTION INPUT ;
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LAYER metal3 ;
RECT 0.000 4.585 0.070 4.655 ;
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DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.795 0.070 4.865 ;
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PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.005 0.070 5.075 ;
END
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PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.215 0.070 5.285 ;
END
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PIN w_mask_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.425 0.070 5.495 ;
END
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PIN w_mask_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.635 0.070 5.705 ;
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PIN w_mask_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.845 0.070 5.915 ;
END
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PIN w_mask_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.055 0.070 6.125 ;
END
END w_mask_in[19]
PIN w_mask_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.265 0.070 6.335 ;
END
END w_mask_in[20]
PIN w_mask_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.475 0.070 6.545 ;
END
END w_mask_in[21]
PIN w_mask_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.685 0.070 6.755 ;
END
END w_mask_in[22]
PIN w_mask_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.895 0.070 6.965 ;
END
END w_mask_in[23]
PIN w_mask_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.105 0.070 7.175 ;
END
END w_mask_in[24]
PIN w_mask_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.315 0.070 7.385 ;
END
END w_mask_in[25]
PIN w_mask_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.525 0.070 7.595 ;
END
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PIN w_mask_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.735 0.070 7.805 ;
END
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DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.945 0.070 8.015 ;
END
END w_mask_in[28]
PIN w_mask_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.155 0.070 8.225 ;
END
END w_mask_in[29]
PIN w_mask_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.365 0.070 8.435 ;
END
END w_mask_in[30]
PIN w_mask_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.575 0.070 8.645 ;
END
END w_mask_in[31]
PIN w_mask_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.785 0.070 8.855 ;
END
END w_mask_in[32]
PIN w_mask_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.995 0.070 9.065 ;
END
END w_mask_in[33]
PIN w_mask_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.205 0.070 9.275 ;
END
END w_mask_in[34]
PIN w_mask_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.415 0.070 9.485 ;
END
END w_mask_in[35]
PIN w_mask_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.625 0.070 9.695 ;
END
END w_mask_in[36]
PIN w_mask_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.835 0.070 9.905 ;
END
END w_mask_in[37]
PIN w_mask_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.045 0.070 10.115 ;
END
END w_mask_in[38]
PIN w_mask_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.255 0.070 10.325 ;
END
END w_mask_in[39]
PIN w_mask_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.465 0.070 10.535 ;
END
END w_mask_in[40]
PIN w_mask_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.675 0.070 10.745 ;
END
END w_mask_in[41]
PIN w_mask_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.885 0.070 10.955 ;
END
END w_mask_in[42]
PIN w_mask_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.095 0.070 11.165 ;
END
END w_mask_in[43]
PIN w_mask_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.305 0.070 11.375 ;
END
END w_mask_in[44]
PIN w_mask_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.515 0.070 11.585 ;
END
END w_mask_in[45]
PIN w_mask_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.725 0.070 11.795 ;
END
END w_mask_in[46]
PIN w_mask_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.935 0.070 12.005 ;
END
END w_mask_in[47]
PIN w_mask_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.145 0.070 12.215 ;
END
END w_mask_in[48]
PIN w_mask_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.355 0.070 12.425 ;
END
END w_mask_in[49]
PIN w_mask_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.565 0.070 12.635 ;
END
END w_mask_in[50]
PIN w_mask_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.775 0.070 12.845 ;
END
END w_mask_in[51]
PIN w_mask_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.985 0.070 13.055 ;
END
END w_mask_in[52]
PIN w_mask_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.195 0.070 13.265 ;
END
END w_mask_in[53]
PIN w_mask_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.405 0.070 13.475 ;
END
END w_mask_in[54]
PIN w_mask_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.615 0.070 13.685 ;
END
END w_mask_in[55]
PIN w_mask_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.825 0.070 13.895 ;
END
END w_mask_in[56]
PIN w_mask_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.035 0.070 14.105 ;
END
END w_mask_in[57]
PIN w_mask_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.245 0.070 14.315 ;
END
END w_mask_in[58]
PIN w_mask_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.455 0.070 14.525 ;
END
END w_mask_in[59]
PIN w_mask_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.665 0.070 14.735 ;
END
END w_mask_in[60]
PIN w_mask_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.875 0.070 14.945 ;
END
END w_mask_in[61]
PIN w_mask_in[62]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.085 0.070 15.155 ;
END
END w_mask_in[62]
PIN w_mask_in[63]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.295 0.070 15.365 ;
END
END w_mask_in[63]
PIN w_mask_in[64]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.505 0.070 15.575 ;
END
END w_mask_in[64]
PIN w_mask_in[65]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.715 0.070 15.785 ;
END
END w_mask_in[65]
PIN w_mask_in[66]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.925 0.070 15.995 ;
END
END w_mask_in[66]
PIN w_mask_in[67]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.135 0.070 16.205 ;
END
END w_mask_in[67]
PIN w_mask_in[68]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.345 0.070 16.415 ;
END
END w_mask_in[68]
PIN w_mask_in[69]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.555 0.070 16.625 ;
END
END w_mask_in[69]
PIN w_mask_in[70]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.765 0.070 16.835 ;
END
END w_mask_in[70]
PIN w_mask_in[71]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.975 0.070 17.045 ;
END
END w_mask_in[71]
PIN w_mask_in[72]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.185 0.070 17.255 ;
END
END w_mask_in[72]
PIN w_mask_in[73]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.395 0.070 17.465 ;
END
END w_mask_in[73]
PIN w_mask_in[74]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.605 0.070 17.675 ;
END
END w_mask_in[74]
PIN w_mask_in[75]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.815 0.070 17.885 ;
END
END w_mask_in[75]
PIN w_mask_in[76]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.025 0.070 18.095 ;
END
END w_mask_in[76]
PIN w_mask_in[77]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.235 0.070 18.305 ;
END
END w_mask_in[77]
PIN w_mask_in[78]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.445 0.070 18.515 ;
END
END w_mask_in[78]
PIN w_mask_in[79]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.655 0.070 18.725 ;
END
END w_mask_in[79]
PIN w_mask_in[80]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.865 0.070 18.935 ;
END
END w_mask_in[80]
PIN w_mask_in[81]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.075 0.070 19.145 ;
END
END w_mask_in[81]
PIN w_mask_in[82]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.285 0.070 19.355 ;
END
END w_mask_in[82]
PIN w_mask_in[83]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.495 0.070 19.565 ;
END
END w_mask_in[83]
PIN w_mask_in[84]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.705 0.070 19.775 ;
END
END w_mask_in[84]
PIN w_mask_in[85]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.915 0.070 19.985 ;
END
END w_mask_in[85]
PIN w_mask_in[86]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.125 0.070 20.195 ;
END
END w_mask_in[86]
PIN w_mask_in[87]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.335 0.070 20.405 ;
END
END w_mask_in[87]
PIN w_mask_in[88]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.545 0.070 20.615 ;
END
END w_mask_in[88]
PIN w_mask_in[89]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.755 0.070 20.825 ;
END
END w_mask_in[89]
PIN w_mask_in[90]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.965 0.070 21.035 ;
END
END w_mask_in[90]
PIN w_mask_in[91]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.175 0.070 21.245 ;
END
END w_mask_in[91]
PIN w_mask_in[92]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.385 0.070 21.455 ;
END
END w_mask_in[92]
PIN w_mask_in[93]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.595 0.070 21.665 ;
END
END w_mask_in[93]
PIN w_mask_in[94]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.805 0.070 21.875 ;
END
END w_mask_in[94]
PIN w_mask_in[95]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.015 0.070 22.085 ;
END
END w_mask_in[95]
PIN w_mask_in[96]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.225 0.070 22.295 ;
END
END w_mask_in[96]
PIN w_mask_in[97]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.435 0.070 22.505 ;
END
END w_mask_in[97]
PIN w_mask_in[98]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.645 0.070 22.715 ;
END
END w_mask_in[98]
PIN w_mask_in[99]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.855 0.070 22.925 ;
END
END w_mask_in[99]
PIN w_mask_in[100]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.065 0.070 23.135 ;
END
END w_mask_in[100]
PIN w_mask_in[101]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.275 0.070 23.345 ;
END
END w_mask_in[101]
PIN w_mask_in[102]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.485 0.070 23.555 ;
END
END w_mask_in[102]
PIN w_mask_in[103]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.695 0.070 23.765 ;
END
END w_mask_in[103]
PIN w_mask_in[104]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.905 0.070 23.975 ;
END
END w_mask_in[104]
PIN w_mask_in[105]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.115 0.070 24.185 ;
END
END w_mask_in[105]
PIN w_mask_in[106]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.325 0.070 24.395 ;
END
END w_mask_in[106]
PIN w_mask_in[107]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.535 0.070 24.605 ;
END
END w_mask_in[107]
PIN w_mask_in[108]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.745 0.070 24.815 ;
END
END w_mask_in[108]
PIN w_mask_in[109]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.955 0.070 25.025 ;
END
END w_mask_in[109]
PIN w_mask_in[110]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.165 0.070 25.235 ;
END
END w_mask_in[110]
PIN w_mask_in[111]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.375 0.070 25.445 ;
END
END w_mask_in[111]
PIN w_mask_in[112]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.585 0.070 25.655 ;
END
END w_mask_in[112]
PIN w_mask_in[113]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.795 0.070 25.865 ;
END
END w_mask_in[113]
PIN w_mask_in[114]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.005 0.070 26.075 ;
END
END w_mask_in[114]
PIN w_mask_in[115]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.215 0.070 26.285 ;
END
END w_mask_in[115]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 35.665 0.070 35.735 ;
END
END rd_out[0]
PIN rd_out[1]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 35.875 0.070 35.945 ;
END
END rd_out[1]
PIN rd_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.085 0.070 36.155 ;
END
END rd_out[2]
PIN rd_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.295 0.070 36.365 ;
END
END rd_out[3]
PIN rd_out[4]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.505 0.070 36.575 ;
END
END rd_out[4]
PIN rd_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.715 0.070 36.785 ;
END
END rd_out[5]
PIN rd_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.925 0.070 36.995 ;
END
END rd_out[6]
PIN rd_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.135 0.070 37.205 ;
END
END rd_out[7]
PIN rd_out[8]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.345 0.070 37.415 ;
END
END rd_out[8]
PIN rd_out[9]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.555 0.070 37.625 ;
END
END rd_out[9]
PIN rd_out[10]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.765 0.070 37.835 ;
END
END rd_out[10]
PIN rd_out[11]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.975 0.070 38.045 ;
END
END rd_out[11]
PIN rd_out[12]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.185 0.070 38.255 ;
END
END rd_out[12]
PIN rd_out[13]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.395 0.070 38.465 ;
END
END rd_out[13]
PIN rd_out[14]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.605 0.070 38.675 ;
END
END rd_out[14]
PIN rd_out[15]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.815 0.070 38.885 ;
END
END rd_out[15]
PIN rd_out[16]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.025 0.070 39.095 ;
END
END rd_out[16]
PIN rd_out[17]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.235 0.070 39.305 ;
END
END rd_out[17]
PIN rd_out[18]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.445 0.070 39.515 ;
END
END rd_out[18]
PIN rd_out[19]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.655 0.070 39.725 ;
END
END rd_out[19]
PIN rd_out[20]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.865 0.070 39.935 ;
END
END rd_out[20]
PIN rd_out[21]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.075 0.070 40.145 ;
END
END rd_out[21]
PIN rd_out[22]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.285 0.070 40.355 ;
END
END rd_out[22]
PIN rd_out[23]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.495 0.070 40.565 ;
END
END rd_out[23]
PIN rd_out[24]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.705 0.070 40.775 ;
END
END rd_out[24]
PIN rd_out[25]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.915 0.070 40.985 ;
END
END rd_out[25]
PIN rd_out[26]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.125 0.070 41.195 ;
END
END rd_out[26]
PIN rd_out[27]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.335 0.070 41.405 ;
END
END rd_out[27]
PIN rd_out[28]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.545 0.070 41.615 ;
END
END rd_out[28]
PIN rd_out[29]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.755 0.070 41.825 ;
END
END rd_out[29]
PIN rd_out[30]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.965 0.070 42.035 ;
END
END rd_out[30]
PIN rd_out[31]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.175 0.070 42.245 ;
END
END rd_out[31]
PIN rd_out[32]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.385 0.070 42.455 ;
END
END rd_out[32]
PIN rd_out[33]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.595 0.070 42.665 ;
END
END rd_out[33]
PIN rd_out[34]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.805 0.070 42.875 ;
END
END rd_out[34]
PIN rd_out[35]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.015 0.070 43.085 ;
END
END rd_out[35]
PIN rd_out[36]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.225 0.070 43.295 ;
END
END rd_out[36]
PIN rd_out[37]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.435 0.070 43.505 ;
END
END rd_out[37]
PIN rd_out[38]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.645 0.070 43.715 ;
END
END rd_out[38]
PIN rd_out[39]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.855 0.070 43.925 ;
END
END rd_out[39]
PIN rd_out[40]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.065 0.070 44.135 ;
END
END rd_out[40]
PIN rd_out[41]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.275 0.070 44.345 ;
END
END rd_out[41]
PIN rd_out[42]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.485 0.070 44.555 ;
END
END rd_out[42]
PIN rd_out[43]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.695 0.070 44.765 ;
END
END rd_out[43]
PIN rd_out[44]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.905 0.070 44.975 ;
END
END rd_out[44]
PIN rd_out[45]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.115 0.070 45.185 ;
END
END rd_out[45]
PIN rd_out[46]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.325 0.070 45.395 ;
END
END rd_out[46]
PIN rd_out[47]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.535 0.070 45.605 ;
END
END rd_out[47]
PIN rd_out[48]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.745 0.070 45.815 ;
END
END rd_out[48]
PIN rd_out[49]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.955 0.070 46.025 ;
END
END rd_out[49]
PIN rd_out[50]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.165 0.070 46.235 ;
END
END rd_out[50]
PIN rd_out[51]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.375 0.070 46.445 ;
END
END rd_out[51]
PIN rd_out[52]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.585 0.070 46.655 ;
END
END rd_out[52]
PIN rd_out[53]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.795 0.070 46.865 ;
END
END rd_out[53]
PIN rd_out[54]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.005 0.070 47.075 ;
END
END rd_out[54]
PIN rd_out[55]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.215 0.070 47.285 ;
END
END rd_out[55]
PIN rd_out[56]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.425 0.070 47.495 ;
END
END rd_out[56]
PIN rd_out[57]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.635 0.070 47.705 ;
END
END rd_out[57]
PIN rd_out[58]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.845 0.070 47.915 ;
END
END rd_out[58]
PIN rd_out[59]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.055 0.070 48.125 ;
END
END rd_out[59]
PIN rd_out[60]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.265 0.070 48.335 ;
END
END rd_out[60]
PIN rd_out[61]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.475 0.070 48.545 ;
END
END rd_out[61]
PIN rd_out[62]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.685 0.070 48.755 ;
END
END rd_out[62]
PIN rd_out[63]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.895 0.070 48.965 ;
END
END rd_out[63]
PIN rd_out[64]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.105 0.070 49.175 ;
END
END rd_out[64]
PIN rd_out[65]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.315 0.070 49.385 ;
END
END rd_out[65]
PIN rd_out[66]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.525 0.070 49.595 ;
END
END rd_out[66]
PIN rd_out[67]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.735 0.070 49.805 ;
END
END rd_out[67]
PIN rd_out[68]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.945 0.070 50.015 ;
END
END rd_out[68]
PIN rd_out[69]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.155 0.070 50.225 ;
END
END rd_out[69]
PIN rd_out[70]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.365 0.070 50.435 ;
END
END rd_out[70]
PIN rd_out[71]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.575 0.070 50.645 ;
END
END rd_out[71]
PIN rd_out[72]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.785 0.070 50.855 ;
END
END rd_out[72]
PIN rd_out[73]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.995 0.070 51.065 ;
END
END rd_out[73]
PIN rd_out[74]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.205 0.070 51.275 ;
END
END rd_out[74]
PIN rd_out[75]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.415 0.070 51.485 ;
END
END rd_out[75]
PIN rd_out[76]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.625 0.070 51.695 ;
END
END rd_out[76]
PIN rd_out[77]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.835 0.070 51.905 ;
END
END rd_out[77]
PIN rd_out[78]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.045 0.070 52.115 ;
END
END rd_out[78]
PIN rd_out[79]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.255 0.070 52.325 ;
END
END rd_out[79]
PIN rd_out[80]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.465 0.070 52.535 ;
END
END rd_out[80]
PIN rd_out[81]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.675 0.070 52.745 ;
END
END rd_out[81]
PIN rd_out[82]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.885 0.070 52.955 ;
END
END rd_out[82]
PIN rd_out[83]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.095 0.070 53.165 ;
END
END rd_out[83]
PIN rd_out[84]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.305 0.070 53.375 ;
END
END rd_out[84]
PIN rd_out[85]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.515 0.070 53.585 ;
END
END rd_out[85]
PIN rd_out[86]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.725 0.070 53.795 ;
END
END rd_out[86]
PIN rd_out[87]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.935 0.070 54.005 ;
END
END rd_out[87]
PIN rd_out[88]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.145 0.070 54.215 ;
END
END rd_out[88]
PIN rd_out[89]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.355 0.070 54.425 ;
END
END rd_out[89]
PIN rd_out[90]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.565 0.070 54.635 ;
END
END rd_out[90]
PIN rd_out[91]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.775 0.070 54.845 ;
END
END rd_out[91]
PIN rd_out[92]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.985 0.070 55.055 ;
END
END rd_out[92]
PIN rd_out[93]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.195 0.070 55.265 ;
END
END rd_out[93]
PIN rd_out[94]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.405 0.070 55.475 ;
END
END rd_out[94]
PIN rd_out[95]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.615 0.070 55.685 ;
END
END rd_out[95]
PIN rd_out[96]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.825 0.070 55.895 ;
END
END rd_out[96]
PIN rd_out[97]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.035 0.070 56.105 ;
END
END rd_out[97]
PIN rd_out[98]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.245 0.070 56.315 ;
END
END rd_out[98]
PIN rd_out[99]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.455 0.070 56.525 ;
END
END rd_out[99]
PIN rd_out[100]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.665 0.070 56.735 ;
END
END rd_out[100]
PIN rd_out[101]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.875 0.070 56.945 ;
END
END rd_out[101]
PIN rd_out[102]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.085 0.070 57.155 ;
END
END rd_out[102]
PIN rd_out[103]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.295 0.070 57.365 ;
END
END rd_out[103]
PIN rd_out[104]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.505 0.070 57.575 ;
END
END rd_out[104]
PIN rd_out[105]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.715 0.070 57.785 ;
END
END rd_out[105]
PIN rd_out[106]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.925 0.070 57.995 ;
END
END rd_out[106]
PIN rd_out[107]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.135 0.070 58.205 ;
END
END rd_out[107]
PIN rd_out[108]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.345 0.070 58.415 ;
END
END rd_out[108]
PIN rd_out[109]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.555 0.070 58.625 ;
END
END rd_out[109]
PIN rd_out[110]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.765 0.070 58.835 ;
END
END rd_out[110]
PIN rd_out[111]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.975 0.070 59.045 ;
END
END rd_out[111]
PIN rd_out[112]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.185 0.070 59.255 ;
END
END rd_out[112]
PIN rd_out[113]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.395 0.070 59.465 ;
END
END rd_out[113]
PIN rd_out[114]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.605 0.070 59.675 ;
END
END rd_out[114]
PIN rd_out[115]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.815 0.070 59.885 ;
END
END rd_out[115]
PIN wd_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.265 0.070 69.335 ;
END
END wd_in[0]
PIN wd_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.475 0.070 69.545 ;
END
END wd_in[1]
PIN wd_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.685 0.070 69.755 ;
END
END wd_in[2]
PIN wd_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.895 0.070 69.965 ;
END
END wd_in[3]
PIN wd_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.105 0.070 70.175 ;
END
END wd_in[4]
PIN wd_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.315 0.070 70.385 ;
END
END wd_in[5]
PIN wd_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.525 0.070 70.595 ;
END
END wd_in[6]
PIN wd_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.735 0.070 70.805 ;
END
END wd_in[7]
PIN wd_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.945 0.070 71.015 ;
END
END wd_in[8]
PIN wd_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.155 0.070 71.225 ;
END
END wd_in[9]
PIN wd_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.365 0.070 71.435 ;
END
END wd_in[10]
PIN wd_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.575 0.070 71.645 ;
END
END wd_in[11]
PIN wd_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.785 0.070 71.855 ;
END
END wd_in[12]
PIN wd_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.995 0.070 72.065 ;
END
END wd_in[13]
PIN wd_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.205 0.070 72.275 ;
END
END wd_in[14]
PIN wd_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.415 0.070 72.485 ;
END
END wd_in[15]
PIN wd_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.625 0.070 72.695 ;
END
END wd_in[16]
PIN wd_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.835 0.070 72.905 ;
END
END wd_in[17]
PIN wd_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.045 0.070 73.115 ;
END
END wd_in[18]
PIN wd_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.255 0.070 73.325 ;
END
END wd_in[19]
PIN wd_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.465 0.070 73.535 ;
END
END wd_in[20]
PIN wd_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.675 0.070 73.745 ;
END
END wd_in[21]
PIN wd_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.885 0.070 73.955 ;
END
END wd_in[22]
PIN wd_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.095 0.070 74.165 ;
END
END wd_in[23]
PIN wd_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.305 0.070 74.375 ;
END
END wd_in[24]
PIN wd_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.515 0.070 74.585 ;
END
END wd_in[25]
PIN wd_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.725 0.070 74.795 ;
END
END wd_in[26]
PIN wd_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.935 0.070 75.005 ;
END
END wd_in[27]
PIN wd_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.145 0.070 75.215 ;
END
END wd_in[28]
PIN wd_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.355 0.070 75.425 ;
END
END wd_in[29]
PIN wd_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.565 0.070 75.635 ;
END
END wd_in[30]
PIN wd_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.775 0.070 75.845 ;
END
END wd_in[31]
PIN wd_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.985 0.070 76.055 ;
END
END wd_in[32]
PIN wd_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.195 0.070 76.265 ;
END
END wd_in[33]
PIN wd_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.405 0.070 76.475 ;
END
END wd_in[34]
PIN wd_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.615 0.070 76.685 ;
END
END wd_in[35]
PIN wd_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.825 0.070 76.895 ;
END
END wd_in[36]
PIN wd_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.035 0.070 77.105 ;
END
END wd_in[37]
PIN wd_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.245 0.070 77.315 ;
END
END wd_in[38]
PIN wd_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.455 0.070 77.525 ;
END
END wd_in[39]
PIN wd_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.665 0.070 77.735 ;
END
END wd_in[40]
PIN wd_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.875 0.070 77.945 ;
END
END wd_in[41]
PIN wd_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.085 0.070 78.155 ;
END
END wd_in[42]
PIN wd_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.295 0.070 78.365 ;
END
END wd_in[43]
PIN wd_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.505 0.070 78.575 ;
END
END wd_in[44]
PIN wd_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.715 0.070 78.785 ;
END
END wd_in[45]
PIN wd_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.925 0.070 78.995 ;
END
END wd_in[46]
PIN wd_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.135 0.070 79.205 ;
END
END wd_in[47]
PIN wd_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.345 0.070 79.415 ;
END
END wd_in[48]
PIN wd_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.555 0.070 79.625 ;
END
END wd_in[49]
PIN wd_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.765 0.070 79.835 ;
END
END wd_in[50]
PIN wd_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.975 0.070 80.045 ;
END
END wd_in[51]
PIN wd_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.185 0.070 80.255 ;
END
END wd_in[52]
PIN wd_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.395 0.070 80.465 ;
END
END wd_in[53]
PIN wd_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.605 0.070 80.675 ;
END
END wd_in[54]
PIN wd_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.815 0.070 80.885 ;
END
END wd_in[55]
PIN wd_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.025 0.070 81.095 ;
END
END wd_in[56]
PIN wd_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.235 0.070 81.305 ;
END
END wd_in[57]
PIN wd_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.445 0.070 81.515 ;
END
END wd_in[58]
PIN wd_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.655 0.070 81.725 ;
END
END wd_in[59]
PIN wd_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.865 0.070 81.935 ;
END
END wd_in[60]
PIN wd_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.075 0.070 82.145 ;
END
END wd_in[61]
PIN wd_in[62]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.285 0.070 82.355 ;
END
END wd_in[62]
PIN wd_in[63]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.495 0.070 82.565 ;
END
END wd_in[63]
PIN wd_in[64]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.705 0.070 82.775 ;
END
END wd_in[64]
PIN wd_in[65]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.915 0.070 82.985 ;
END
END wd_in[65]
PIN wd_in[66]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.125 0.070 83.195 ;
END
END wd_in[66]
PIN wd_in[67]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.335 0.070 83.405 ;
END
END wd_in[67]
PIN wd_in[68]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.545 0.070 83.615 ;
END
END wd_in[68]
PIN wd_in[69]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.755 0.070 83.825 ;
END
END wd_in[69]
PIN wd_in[70]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.965 0.070 84.035 ;
END
END wd_in[70]
PIN wd_in[71]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.175 0.070 84.245 ;
END
END wd_in[71]
PIN wd_in[72]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.385 0.070 84.455 ;
END
END wd_in[72]
PIN wd_in[73]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.595 0.070 84.665 ;
END
END wd_in[73]
PIN wd_in[74]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.805 0.070 84.875 ;
END
END wd_in[74]
PIN wd_in[75]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.015 0.070 85.085 ;
END
END wd_in[75]
PIN wd_in[76]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.225 0.070 85.295 ;
END
END wd_in[76]
PIN wd_in[77]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.435 0.070 85.505 ;
END
END wd_in[77]
PIN wd_in[78]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.645 0.070 85.715 ;
END
END wd_in[78]
PIN wd_in[79]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.855 0.070 85.925 ;
END
END wd_in[79]
PIN wd_in[80]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.065 0.070 86.135 ;
END
END wd_in[80]
PIN wd_in[81]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.275 0.070 86.345 ;
END
END wd_in[81]
PIN wd_in[82]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.485 0.070 86.555 ;
END
END wd_in[82]
PIN wd_in[83]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.695 0.070 86.765 ;
END
END wd_in[83]
PIN wd_in[84]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.905 0.070 86.975 ;
END
END wd_in[84]
PIN wd_in[85]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.115 0.070 87.185 ;
END
END wd_in[85]
PIN wd_in[86]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.325 0.070 87.395 ;
END
END wd_in[86]
PIN wd_in[87]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.535 0.070 87.605 ;
END
END wd_in[87]
PIN wd_in[88]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.745 0.070 87.815 ;
END
END wd_in[88]
PIN wd_in[89]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.955 0.070 88.025 ;
END
END wd_in[89]
PIN wd_in[90]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.165 0.070 88.235 ;
END
END wd_in[90]
PIN wd_in[91]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.375 0.070 88.445 ;
END
END wd_in[91]
PIN wd_in[92]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.585 0.070 88.655 ;
END
END wd_in[92]
PIN wd_in[93]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.795 0.070 88.865 ;
END
END wd_in[93]
PIN wd_in[94]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.005 0.070 89.075 ;
END
END wd_in[94]
PIN wd_in[95]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.215 0.070 89.285 ;
END
END wd_in[95]
PIN wd_in[96]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.425 0.070 89.495 ;
END
END wd_in[96]
PIN wd_in[97]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.635 0.070 89.705 ;
END
END wd_in[97]
PIN wd_in[98]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.845 0.070 89.915 ;
END
END wd_in[98]
PIN wd_in[99]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.055 0.070 90.125 ;
END
END wd_in[99]
PIN wd_in[100]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.265 0.070 90.335 ;
END
END wd_in[100]
PIN wd_in[101]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.475 0.070 90.545 ;
END
END wd_in[101]
PIN wd_in[102]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.685 0.070 90.755 ;
END
END wd_in[102]
PIN wd_in[103]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.895 0.070 90.965 ;
END
END wd_in[103]
PIN wd_in[104]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.105 0.070 91.175 ;
END
END wd_in[104]
PIN wd_in[105]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.315 0.070 91.385 ;
END
END wd_in[105]
PIN wd_in[106]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.525 0.070 91.595 ;
END
END wd_in[106]
PIN wd_in[107]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.735 0.070 91.805 ;
END
END wd_in[107]
PIN wd_in[108]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.945 0.070 92.015 ;
END
END wd_in[108]
PIN wd_in[109]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.155 0.070 92.225 ;
END
END wd_in[109]
PIN wd_in[110]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.365 0.070 92.435 ;
END
END wd_in[110]
PIN wd_in[111]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.575 0.070 92.645 ;
END
END wd_in[111]
PIN wd_in[112]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.785 0.070 92.855 ;
END
END wd_in[112]
PIN wd_in[113]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.995 0.070 93.065 ;
END
END wd_in[113]
PIN wd_in[114]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 93.205 0.070 93.275 ;
END
END wd_in[114]
PIN wd_in[115]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 93.415 0.070 93.485 ;
END
END wd_in[115]
PIN addr_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 102.865 0.070 102.935 ;
END
END addr_in[0]
PIN addr_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.075 0.070 103.145 ;
END
END addr_in[1]
PIN addr_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.285 0.070 103.355 ;
END
END addr_in[2]
PIN addr_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.495 0.070 103.565 ;
END
END addr_in[3]
PIN addr_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.705 0.070 103.775 ;
END
END addr_in[4]
PIN addr_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.915 0.070 103.985 ;
END
END addr_in[5]
PIN addr_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 104.125 0.070 104.195 ;
END
END addr_in[6]
PIN we_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 113.575 0.070 113.645 ;
END
END we_in
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 113.785 0.070 113.855 ;
END
END ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 113.995 0.070 114.065 ;
END
END clk
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER metal4 ;
RECT 1.960 2.100 2.240 115.500 ;
RECT 5.320 2.100 5.600 115.500 ;
RECT 8.680 2.100 8.960 115.500 ;
RECT 12.040 2.100 12.320 115.500 ;
RECT 15.400 2.100 15.680 115.500 ;
RECT 18.760 2.100 19.040 115.500 ;
RECT 22.120 2.100 22.400 115.500 ;
RECT 25.480 2.100 25.760 115.500 ;
RECT 28.840 2.100 29.120 115.500 ;
RECT 32.200 2.100 32.480 115.500 ;
RECT 35.560 2.100 35.840 115.500 ;
RECT 38.920 2.100 39.200 115.500 ;
RECT 42.280 2.100 42.560 115.500 ;
RECT 45.640 2.100 45.920 115.500 ;
RECT 49.000 2.100 49.280 115.500 ;
RECT 52.360 2.100 52.640 115.500 ;
RECT 55.720 2.100 56.000 115.500 ;
RECT 59.080 2.100 59.360 115.500 ;
RECT 62.440 2.100 62.720 115.500 ;
RECT 65.800 2.100 66.080 115.500 ;
RECT 69.160 2.100 69.440 115.500 ;
RECT 72.520 2.100 72.800 115.500 ;
RECT 75.880 2.100 76.160 115.500 ;
RECT 79.240 2.100 79.520 115.500 ;
RECT 82.600 2.100 82.880 115.500 ;
RECT 85.960 2.100 86.240 115.500 ;
RECT 89.320 2.100 89.600 115.500 ;
RECT 92.680 2.100 92.960 115.500 ;
RECT 96.040 2.100 96.320 115.500 ;
RECT 99.400 2.100 99.680 115.500 ;
RECT 102.760 2.100 103.040 115.500 ;
RECT 106.120 2.100 106.400 115.500 ;
RECT 109.480 2.100 109.760 115.500 ;
RECT 112.840 2.100 113.120 115.500 ;
RECT 116.200 2.100 116.480 115.500 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER metal4 ;
RECT 3.640 2.100 3.920 115.500 ;
RECT 7.000 2.100 7.280 115.500 ;
RECT 10.360 2.100 10.640 115.500 ;
RECT 13.720 2.100 14.000 115.500 ;
RECT 17.080 2.100 17.360 115.500 ;
RECT 20.440 2.100 20.720 115.500 ;
RECT 23.800 2.100 24.080 115.500 ;
RECT 27.160 2.100 27.440 115.500 ;
RECT 30.520 2.100 30.800 115.500 ;
RECT 33.880 2.100 34.160 115.500 ;
RECT 37.240 2.100 37.520 115.500 ;
RECT 40.600 2.100 40.880 115.500 ;
RECT 43.960 2.100 44.240 115.500 ;
RECT 47.320 2.100 47.600 115.500 ;
RECT 50.680 2.100 50.960 115.500 ;
RECT 54.040 2.100 54.320 115.500 ;
RECT 57.400 2.100 57.680 115.500 ;
RECT 60.760 2.100 61.040 115.500 ;
RECT 64.120 2.100 64.400 115.500 ;
RECT 67.480 2.100 67.760 115.500 ;
RECT 70.840 2.100 71.120 115.500 ;
RECT 74.200 2.100 74.480 115.500 ;
RECT 77.560 2.100 77.840 115.500 ;
RECT 80.920 2.100 81.200 115.500 ;
RECT 84.280 2.100 84.560 115.500 ;
RECT 87.640 2.100 87.920 115.500 ;
RECT 91.000 2.100 91.280 115.500 ;
RECT 94.360 2.100 94.640 115.500 ;
RECT 97.720 2.100 98.000 115.500 ;
RECT 101.080 2.100 101.360 115.500 ;
RECT 104.440 2.100 104.720 115.500 ;
RECT 107.800 2.100 108.080 115.500 ;
RECT 111.160 2.100 111.440 115.500 ;
RECT 114.520 2.100 114.800 115.500 ;
RECT 117.880 2.100 118.160 115.500 ;
END
END VDD
OBS
LAYER metal1 ;
RECT 0 0 121.030 117.600 ;
LAYER metal2 ;
RECT 0 0 121.030 117.600 ;
LAYER metal3 ;
RECT 0.070 0 121.030 117.600 ;
RECT 0 0.000 0.070 2.065 ;
RECT 0 2.135 0.070 2.275 ;
RECT 0 2.345 0.070 2.485 ;
RECT 0 2.555 0.070 2.695 ;
RECT 0 2.765 0.070 2.905 ;
RECT 0 2.975 0.070 3.115 ;
RECT 0 3.185 0.070 3.325 ;
RECT 0 3.395 0.070 3.535 ;
RECT 0 3.605 0.070 3.745 ;
RECT 0 3.815 0.070 3.955 ;
RECT 0 4.025 0.070 4.165 ;
RECT 0 4.235 0.070 4.375 ;
RECT 0 4.445 0.070 4.585 ;
RECT 0 4.655 0.070 4.795 ;
RECT 0 4.865 0.070 5.005 ;
RECT 0 5.075 0.070 5.215 ;
RECT 0 5.285 0.070 5.425 ;
RECT 0 5.495 0.070 5.635 ;
RECT 0 5.705 0.070 5.845 ;
RECT 0 5.915 0.070 6.055 ;
RECT 0 6.125 0.070 6.265 ;
RECT 0 6.335 0.070 6.475 ;
RECT 0 6.545 0.070 6.685 ;
RECT 0 6.755 0.070 6.895 ;
RECT 0 6.965 0.070 7.105 ;
RECT 0 7.175 0.070 7.315 ;
RECT 0 7.385 0.070 7.525 ;
RECT 0 7.595 0.070 7.735 ;
RECT 0 7.805 0.070 7.945 ;
RECT 0 8.015 0.070 8.155 ;
RECT 0 8.225 0.070 8.365 ;
RECT 0 8.435 0.070 8.575 ;
RECT 0 8.645 0.070 8.785 ;
RECT 0 8.855 0.070 8.995 ;
RECT 0 9.065 0.070 9.205 ;
RECT 0 9.275 0.070 9.415 ;
RECT 0 9.485 0.070 9.625 ;
RECT 0 9.695 0.070 9.835 ;
RECT 0 9.905 0.070 10.045 ;
RECT 0 10.115 0.070 10.255 ;
RECT 0 10.325 0.070 10.465 ;
RECT 0 10.535 0.070 10.675 ;
RECT 0 10.745 0.070 10.885 ;
RECT 0 10.955 0.070 11.095 ;
RECT 0 11.165 0.070 11.305 ;
RECT 0 11.375 0.070 11.515 ;
RECT 0 11.585 0.070 11.725 ;
RECT 0 11.795 0.070 11.935 ;
RECT 0 12.005 0.070 12.145 ;
RECT 0 12.215 0.070 12.355 ;
RECT 0 12.425 0.070 12.565 ;
RECT 0 12.635 0.070 12.775 ;
RECT 0 12.845 0.070 12.985 ;
RECT 0 13.055 0.070 13.195 ;
RECT 0 13.265 0.070 13.405 ;
RECT 0 13.475 0.070 13.615 ;
RECT 0 13.685 0.070 13.825 ;
RECT 0 13.895 0.070 14.035 ;
RECT 0 14.105 0.070 14.245 ;
RECT 0 14.315 0.070 14.455 ;
RECT 0 14.525 0.070 14.665 ;
RECT 0 14.735 0.070 14.875 ;
RECT 0 14.945 0.070 15.085 ;
RECT 0 15.155 0.070 15.295 ;
RECT 0 15.365 0.070 15.505 ;
RECT 0 15.575 0.070 15.715 ;
RECT 0 15.785 0.070 15.925 ;
RECT 0 15.995 0.070 16.135 ;
RECT 0 16.205 0.070 16.345 ;
RECT 0 16.415 0.070 16.555 ;
RECT 0 16.625 0.070 16.765 ;
RECT 0 16.835 0.070 16.975 ;
RECT 0 17.045 0.070 17.185 ;
RECT 0 17.255 0.070 17.395 ;
RECT 0 17.465 0.070 17.605 ;
RECT 0 17.675 0.070 17.815 ;
RECT 0 17.885 0.070 18.025 ;
RECT 0 18.095 0.070 18.235 ;
RECT 0 18.305 0.070 18.445 ;
RECT 0 18.515 0.070 18.655 ;
RECT 0 18.725 0.070 18.865 ;
RECT 0 18.935 0.070 19.075 ;
RECT 0 19.145 0.070 19.285 ;
RECT 0 19.355 0.070 19.495 ;
RECT 0 19.565 0.070 19.705 ;
RECT 0 19.775 0.070 19.915 ;
RECT 0 19.985 0.070 20.125 ;
RECT 0 20.195 0.070 20.335 ;
RECT 0 20.405 0.070 20.545 ;
RECT 0 20.615 0.070 20.755 ;
RECT 0 20.825 0.070 20.965 ;
RECT 0 21.035 0.070 21.175 ;
RECT 0 21.245 0.070 21.385 ;
RECT 0 21.455 0.070 21.595 ;
RECT 0 21.665 0.070 21.805 ;
RECT 0 21.875 0.070 22.015 ;
RECT 0 22.085 0.070 22.225 ;
RECT 0 22.295 0.070 22.435 ;
RECT 0 22.505 0.070 22.645 ;
RECT 0 22.715 0.070 22.855 ;
RECT 0 22.925 0.070 23.065 ;
RECT 0 23.135 0.070 23.275 ;
RECT 0 23.345 0.070 23.485 ;
RECT 0 23.555 0.070 23.695 ;
RECT 0 23.765 0.070 23.905 ;
RECT 0 23.975 0.070 24.115 ;
RECT 0 24.185 0.070 24.325 ;
RECT 0 24.395 0.070 24.535 ;
RECT 0 24.605 0.070 24.745 ;
RECT 0 24.815 0.070 24.955 ;
RECT 0 25.025 0.070 25.165 ;
RECT 0 25.235 0.070 25.375 ;
RECT 0 25.445 0.070 25.585 ;
RECT 0 25.655 0.070 25.795 ;
RECT 0 25.865 0.070 26.005 ;
RECT 0 26.075 0.070 26.215 ;
RECT 0 26.285 0.070 35.665 ;
RECT 0 35.735 0.070 35.875 ;
RECT 0 35.945 0.070 36.085 ;
RECT 0 36.155 0.070 36.295 ;
RECT 0 36.365 0.070 36.505 ;
RECT 0 36.575 0.070 36.715 ;
RECT 0 36.785 0.070 36.925 ;
RECT 0 36.995 0.070 37.135 ;
RECT 0 37.205 0.070 37.345 ;
RECT 0 37.415 0.070 37.555 ;
RECT 0 37.625 0.070 37.765 ;
RECT 0 37.835 0.070 37.975 ;
RECT 0 38.045 0.070 38.185 ;
RECT 0 38.255 0.070 38.395 ;
RECT 0 38.465 0.070 38.605 ;
RECT 0 38.675 0.070 38.815 ;
RECT 0 38.885 0.070 39.025 ;
RECT 0 39.095 0.070 39.235 ;
RECT 0 39.305 0.070 39.445 ;
RECT 0 39.515 0.070 39.655 ;
RECT 0 39.725 0.070 39.865 ;
RECT 0 39.935 0.070 40.075 ;
RECT 0 40.145 0.070 40.285 ;
RECT 0 40.355 0.070 40.495 ;
RECT 0 40.565 0.070 40.705 ;
RECT 0 40.775 0.070 40.915 ;
RECT 0 40.985 0.070 41.125 ;
RECT 0 41.195 0.070 41.335 ;
RECT 0 41.405 0.070 41.545 ;
RECT 0 41.615 0.070 41.755 ;
RECT 0 41.825 0.070 41.965 ;
RECT 0 42.035 0.070 42.175 ;
RECT 0 42.245 0.070 42.385 ;
RECT 0 42.455 0.070 42.595 ;
RECT 0 42.665 0.070 42.805 ;
RECT 0 42.875 0.070 43.015 ;
RECT 0 43.085 0.070 43.225 ;
RECT 0 43.295 0.070 43.435 ;
RECT 0 43.505 0.070 43.645 ;
RECT 0 43.715 0.070 43.855 ;
RECT 0 43.925 0.070 44.065 ;
RECT 0 44.135 0.070 44.275 ;
RECT 0 44.345 0.070 44.485 ;
RECT 0 44.555 0.070 44.695 ;
RECT 0 44.765 0.070 44.905 ;
RECT 0 44.975 0.070 45.115 ;
RECT 0 45.185 0.070 45.325 ;
RECT 0 45.395 0.070 45.535 ;
RECT 0 45.605 0.070 45.745 ;
RECT 0 45.815 0.070 45.955 ;
RECT 0 46.025 0.070 46.165 ;
RECT 0 46.235 0.070 46.375 ;
RECT 0 46.445 0.070 46.585 ;
RECT 0 46.655 0.070 46.795 ;
RECT 0 46.865 0.070 47.005 ;
RECT 0 47.075 0.070 47.215 ;
RECT 0 47.285 0.070 47.425 ;
RECT 0 47.495 0.070 47.635 ;
RECT 0 47.705 0.070 47.845 ;
RECT 0 47.915 0.070 48.055 ;
RECT 0 48.125 0.070 48.265 ;
RECT 0 48.335 0.070 48.475 ;
RECT 0 48.545 0.070 48.685 ;
RECT 0 48.755 0.070 48.895 ;
RECT 0 48.965 0.070 49.105 ;
RECT 0 49.175 0.070 49.315 ;
RECT 0 49.385 0.070 49.525 ;
RECT 0 49.595 0.070 49.735 ;
RECT 0 49.805 0.070 49.945 ;
RECT 0 50.015 0.070 50.155 ;
RECT 0 50.225 0.070 50.365 ;
RECT 0 50.435 0.070 50.575 ;
RECT 0 50.645 0.070 50.785 ;
RECT 0 50.855 0.070 50.995 ;
RECT 0 51.065 0.070 51.205 ;
RECT 0 51.275 0.070 51.415 ;
RECT 0 51.485 0.070 51.625 ;
RECT 0 51.695 0.070 51.835 ;
RECT 0 51.905 0.070 52.045 ;
RECT 0 52.115 0.070 52.255 ;
RECT 0 52.325 0.070 52.465 ;
RECT 0 52.535 0.070 52.675 ;
RECT 0 52.745 0.070 52.885 ;
RECT 0 52.955 0.070 53.095 ;
RECT 0 53.165 0.070 53.305 ;
RECT 0 53.375 0.070 53.515 ;
RECT 0 53.585 0.070 53.725 ;
RECT 0 53.795 0.070 53.935 ;
RECT 0 54.005 0.070 54.145 ;
RECT 0 54.215 0.070 54.355 ;
RECT 0 54.425 0.070 54.565 ;
RECT 0 54.635 0.070 54.775 ;
RECT 0 54.845 0.070 54.985 ;
RECT 0 55.055 0.070 55.195 ;
RECT 0 55.265 0.070 55.405 ;
RECT 0 55.475 0.070 55.615 ;
RECT 0 55.685 0.070 55.825 ;
RECT 0 55.895 0.070 56.035 ;
RECT 0 56.105 0.070 56.245 ;
RECT 0 56.315 0.070 56.455 ;
RECT 0 56.525 0.070 56.665 ;
RECT 0 56.735 0.070 56.875 ;
RECT 0 56.945 0.070 57.085 ;
RECT 0 57.155 0.070 57.295 ;
RECT 0 57.365 0.070 57.505 ;
RECT 0 57.575 0.070 57.715 ;
RECT 0 57.785 0.070 57.925 ;
RECT 0 57.995 0.070 58.135 ;
RECT 0 58.205 0.070 58.345 ;
RECT 0 58.415 0.070 58.555 ;
RECT 0 58.625 0.070 58.765 ;
RECT 0 58.835 0.070 58.975 ;
RECT 0 59.045 0.070 59.185 ;
RECT 0 59.255 0.070 59.395 ;
RECT 0 59.465 0.070 59.605 ;
RECT 0 59.675 0.070 59.815 ;
RECT 0 59.885 0.070 69.265 ;
RECT 0 69.335 0.070 69.475 ;
RECT 0 69.545 0.070 69.685 ;
RECT 0 69.755 0.070 69.895 ;
RECT 0 69.965 0.070 70.105 ;
RECT 0 70.175 0.070 70.315 ;
RECT 0 70.385 0.070 70.525 ;
RECT 0 70.595 0.070 70.735 ;
RECT 0 70.805 0.070 70.945 ;
RECT 0 71.015 0.070 71.155 ;
RECT 0 71.225 0.070 71.365 ;
RECT 0 71.435 0.070 71.575 ;
RECT 0 71.645 0.070 71.785 ;
RECT 0 71.855 0.070 71.995 ;
RECT 0 72.065 0.070 72.205 ;
RECT 0 72.275 0.070 72.415 ;
RECT 0 72.485 0.070 72.625 ;
RECT 0 72.695 0.070 72.835 ;
RECT 0 72.905 0.070 73.045 ;
RECT 0 73.115 0.070 73.255 ;
RECT 0 73.325 0.070 73.465 ;
RECT 0 73.535 0.070 73.675 ;
RECT 0 73.745 0.070 73.885 ;
RECT 0 73.955 0.070 74.095 ;
RECT 0 74.165 0.070 74.305 ;
RECT 0 74.375 0.070 74.515 ;
RECT 0 74.585 0.070 74.725 ;
RECT 0 74.795 0.070 74.935 ;
RECT 0 75.005 0.070 75.145 ;
RECT 0 75.215 0.070 75.355 ;
RECT 0 75.425 0.070 75.565 ;
RECT 0 75.635 0.070 75.775 ;
RECT 0 75.845 0.070 75.985 ;
RECT 0 76.055 0.070 76.195 ;
RECT 0 76.265 0.070 76.405 ;
RECT 0 76.475 0.070 76.615 ;
RECT 0 76.685 0.070 76.825 ;
RECT 0 76.895 0.070 77.035 ;
RECT 0 77.105 0.070 77.245 ;
RECT 0 77.315 0.070 77.455 ;
RECT 0 77.525 0.070 77.665 ;
RECT 0 77.735 0.070 77.875 ;
RECT 0 77.945 0.070 78.085 ;
RECT 0 78.155 0.070 78.295 ;
RECT 0 78.365 0.070 78.505 ;
RECT 0 78.575 0.070 78.715 ;
RECT 0 78.785 0.070 78.925 ;
RECT 0 78.995 0.070 79.135 ;
RECT 0 79.205 0.070 79.345 ;
RECT 0 79.415 0.070 79.555 ;
RECT 0 79.625 0.070 79.765 ;
RECT 0 79.835 0.070 79.975 ;
RECT 0 80.045 0.070 80.185 ;
RECT 0 80.255 0.070 80.395 ;
RECT 0 80.465 0.070 80.605 ;
RECT 0 80.675 0.070 80.815 ;
RECT 0 80.885 0.070 81.025 ;
RECT 0 81.095 0.070 81.235 ;
RECT 0 81.305 0.070 81.445 ;
RECT 0 81.515 0.070 81.655 ;
RECT 0 81.725 0.070 81.865 ;
RECT 0 81.935 0.070 82.075 ;
RECT 0 82.145 0.070 82.285 ;
RECT 0 82.355 0.070 82.495 ;
RECT 0 82.565 0.070 82.705 ;
RECT 0 82.775 0.070 82.915 ;
RECT 0 82.985 0.070 83.125 ;
RECT 0 83.195 0.070 83.335 ;
RECT 0 83.405 0.070 83.545 ;
RECT 0 83.615 0.070 83.755 ;
RECT 0 83.825 0.070 83.965 ;
RECT 0 84.035 0.070 84.175 ;
RECT 0 84.245 0.070 84.385 ;
RECT 0 84.455 0.070 84.595 ;
RECT 0 84.665 0.070 84.805 ;
RECT 0 84.875 0.070 85.015 ;
RECT 0 85.085 0.070 85.225 ;
RECT 0 85.295 0.070 85.435 ;
RECT 0 85.505 0.070 85.645 ;
RECT 0 85.715 0.070 85.855 ;
RECT 0 85.925 0.070 86.065 ;
RECT 0 86.135 0.070 86.275 ;
RECT 0 86.345 0.070 86.485 ;
RECT 0 86.555 0.070 86.695 ;
RECT 0 86.765 0.070 86.905 ;
RECT 0 86.975 0.070 87.115 ;
RECT 0 87.185 0.070 87.325 ;
RECT 0 87.395 0.070 87.535 ;
RECT 0 87.605 0.070 87.745 ;
RECT 0 87.815 0.070 87.955 ;
RECT 0 88.025 0.070 88.165 ;
RECT 0 88.235 0.070 88.375 ;
RECT 0 88.445 0.070 88.585 ;
RECT 0 88.655 0.070 88.795 ;
RECT 0 88.865 0.070 89.005 ;
RECT 0 89.075 0.070 89.215 ;
RECT 0 89.285 0.070 89.425 ;
RECT 0 89.495 0.070 89.635 ;
RECT 0 89.705 0.070 89.845 ;
RECT 0 89.915 0.070 90.055 ;
RECT 0 90.125 0.070 90.265 ;
RECT 0 90.335 0.070 90.475 ;
RECT 0 90.545 0.070 90.685 ;
RECT 0 90.755 0.070 90.895 ;
RECT 0 90.965 0.070 91.105 ;
RECT 0 91.175 0.070 91.315 ;
RECT 0 91.385 0.070 91.525 ;
RECT 0 91.595 0.070 91.735 ;
RECT 0 91.805 0.070 91.945 ;
RECT 0 92.015 0.070 92.155 ;
RECT 0 92.225 0.070 92.365 ;
RECT 0 92.435 0.070 92.575 ;
RECT 0 92.645 0.070 92.785 ;
RECT 0 92.855 0.070 92.995 ;
RECT 0 93.065 0.070 93.205 ;
RECT 0 93.275 0.070 93.415 ;
RECT 0 93.485 0.070 102.865 ;
RECT 0 102.935 0.070 103.075 ;
RECT 0 103.145 0.070 103.285 ;
RECT 0 103.355 0.070 103.495 ;
RECT 0 103.565 0.070 103.705 ;
RECT 0 103.775 0.070 103.915 ;
RECT 0 103.985 0.070 104.125 ;
RECT 0 104.195 0.070 113.575 ;
RECT 0 113.645 0.070 113.785 ;
RECT 0 113.855 0.070 113.995 ;
RECT 0 114.065 0.070 117.600 ;
LAYER metal4 ;
RECT 0 0 121.030 2.100 ;
RECT 0 115.500 121.030 117.600 ;
RECT 0.000 2.100 1.960 115.500 ;
RECT 2.240 2.100 3.640 115.500 ;
RECT 3.920 2.100 5.320 115.500 ;
RECT 5.600 2.100 7.000 115.500 ;
RECT 7.280 2.100 8.680 115.500 ;
RECT 8.960 2.100 10.360 115.500 ;
RECT 10.640 2.100 12.040 115.500 ;
RECT 12.320 2.100 13.720 115.500 ;
RECT 14.000 2.100 15.400 115.500 ;
RECT 15.680 2.100 17.080 115.500 ;
RECT 17.360 2.100 18.760 115.500 ;
RECT 19.040 2.100 20.440 115.500 ;
RECT 20.720 2.100 22.120 115.500 ;
RECT 22.400 2.100 23.800 115.500 ;
RECT 24.080 2.100 25.480 115.500 ;
RECT 25.760 2.100 27.160 115.500 ;
RECT 27.440 2.100 28.840 115.500 ;
RECT 29.120 2.100 30.520 115.500 ;
RECT 30.800 2.100 32.200 115.500 ;
RECT 32.480 2.100 33.880 115.500 ;
RECT 34.160 2.100 35.560 115.500 ;
RECT 35.840 2.100 37.240 115.500 ;
RECT 37.520 2.100 38.920 115.500 ;
RECT 39.200 2.100 40.600 115.500 ;
RECT 40.880 2.100 42.280 115.500 ;
RECT 42.560 2.100 43.960 115.500 ;
RECT 44.240 2.100 45.640 115.500 ;
RECT 45.920 2.100 47.320 115.500 ;
RECT 47.600 2.100 49.000 115.500 ;
RECT 49.280 2.100 50.680 115.500 ;
RECT 50.960 2.100 52.360 115.500 ;
RECT 52.640 2.100 54.040 115.500 ;
RECT 54.320 2.100 55.720 115.500 ;
RECT 56.000 2.100 57.400 115.500 ;
RECT 57.680 2.100 59.080 115.500 ;
RECT 59.360 2.100 60.760 115.500 ;
RECT 61.040 2.100 62.440 115.500 ;
RECT 62.720 2.100 64.120 115.500 ;
RECT 64.400 2.100 65.800 115.500 ;
RECT 66.080 2.100 67.480 115.500 ;
RECT 67.760 2.100 69.160 115.500 ;
RECT 69.440 2.100 70.840 115.500 ;
RECT 71.120 2.100 72.520 115.500 ;
RECT 72.800 2.100 74.200 115.500 ;
RECT 74.480 2.100 75.880 115.500 ;
RECT 76.160 2.100 77.560 115.500 ;
RECT 77.840 2.100 79.240 115.500 ;
RECT 79.520 2.100 80.920 115.500 ;
RECT 81.200 2.100 82.600 115.500 ;
RECT 82.880 2.100 84.280 115.500 ;
RECT 84.560 2.100 85.960 115.500 ;
RECT 86.240 2.100 87.640 115.500 ;
RECT 87.920 2.100 89.320 115.500 ;
RECT 89.600 2.100 91.000 115.500 ;
RECT 91.280 2.100 92.680 115.500 ;
RECT 92.960 2.100 94.360 115.500 ;
RECT 94.640 2.100 96.040 115.500 ;
RECT 96.320 2.100 97.720 115.500 ;
RECT 98.000 2.100 99.400 115.500 ;
RECT 99.680 2.100 101.080 115.500 ;
RECT 101.360 2.100 102.760 115.500 ;
RECT 103.040 2.100 104.440 115.500 ;
RECT 104.720 2.100 106.120 115.500 ;
RECT 106.400 2.100 107.800 115.500 ;
RECT 108.080 2.100 109.480 115.500 ;
RECT 109.760 2.100 111.160 115.500 ;
RECT 111.440 2.100 112.840 115.500 ;
RECT 113.120 2.100 114.520 115.500 ;
RECT 114.800 2.100 116.200 115.500 ;
RECT 116.480 2.100 117.880 115.500 ;
RECT 118.160 2.100 121.030 115.500 ;
LAYER OVERLAP ;
RECT 0 0 121.030 117.600 ;
END
END fakeram45_128x116
END LIBRARY
Enablements/NanGate45/lef/fakeram45_256x48.lef 0 → 100644
VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_256x48
FOREIGN fakeram45_256x48 0 0 ;
SYMMETRY X Y R90 ;
SIZE 64.030 BY 207.200 ;
CLASS BLOCK ;
PIN w_mask_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.065 0.070 2.135 ;
END
END w_mask_in[0]
PIN w_mask_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.325 0.070 3.395 ;
END
END w_mask_in[1]
PIN w_mask_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.585 0.070 4.655 ;
END
END w_mask_in[2]
PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.845 0.070 5.915 ;
END
END w_mask_in[3]
PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.105 0.070 7.175 ;
END
END w_mask_in[4]
PIN w_mask_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.365 0.070 8.435 ;
END
END w_mask_in[5]
PIN w_mask_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.625 0.070 9.695 ;
END
END w_mask_in[6]
PIN w_mask_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.885 0.070 10.955 ;
END
END w_mask_in[7]
PIN w_mask_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.145 0.070 12.215 ;
END
END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.405 0.070 13.475 ;
END
END w_mask_in[9]
PIN w_mask_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.665 0.070 14.735 ;
END
END w_mask_in[10]
PIN w_mask_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.925 0.070 15.995 ;
END
END w_mask_in[11]
PIN w_mask_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.185 0.070 17.255 ;
END
END w_mask_in[12]
PIN w_mask_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.445 0.070 18.515 ;
END
END w_mask_in[13]
PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.705 0.070 19.775 ;
END
END w_mask_in[14]
PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.965 0.070 21.035 ;
END
END w_mask_in[15]
PIN w_mask_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.225 0.070 22.295 ;
END
END w_mask_in[16]
PIN w_mask_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.485 0.070 23.555 ;
END
END w_mask_in[17]
PIN w_mask_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.745 0.070 24.815 ;
END
END w_mask_in[18]
PIN w_mask_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.005 0.070 26.075 ;
END
END w_mask_in[19]
PIN w_mask_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.265 0.070 27.335 ;
END
END w_mask_in[20]
PIN w_mask_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 28.525 0.070 28.595 ;
END
END w_mask_in[21]
PIN w_mask_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 29.785 0.070 29.855 ;
END
END w_mask_in[22]
PIN w_mask_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 31.045 0.070 31.115 ;
END
END w_mask_in[23]
PIN w_mask_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 32.305 0.070 32.375 ;
END
END w_mask_in[24]
PIN w_mask_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 33.565 0.070 33.635 ;
END
END w_mask_in[25]
PIN w_mask_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 34.825 0.070 34.895 ;
END
END w_mask_in[26]
PIN w_mask_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.085 0.070 36.155 ;
END
END w_mask_in[27]
PIN w_mask_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.345 0.070 37.415 ;
END
END w_mask_in[28]
PIN w_mask_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.605 0.070 38.675 ;
END
END w_mask_in[29]
PIN w_mask_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.865 0.070 39.935 ;
END
END w_mask_in[30]
PIN w_mask_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.125 0.070 41.195 ;
END
END w_mask_in[31]
PIN w_mask_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.385 0.070 42.455 ;
END
END w_mask_in[32]
PIN w_mask_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.645 0.070 43.715 ;
END
END w_mask_in[33]
PIN w_mask_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.905 0.070 44.975 ;
END
END w_mask_in[34]
PIN w_mask_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.165 0.070 46.235 ;
END
END w_mask_in[35]
PIN w_mask_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.425 0.070 47.495 ;
END
END w_mask_in[36]
PIN w_mask_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.685 0.070 48.755 ;
END
END w_mask_in[37]
PIN w_mask_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.945 0.070 50.015 ;
END
END w_mask_in[38]
PIN w_mask_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.205 0.070 51.275 ;
END
END w_mask_in[39]
PIN w_mask_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.465 0.070 52.535 ;
END
END w_mask_in[40]
PIN w_mask_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.725 0.070 53.795 ;
END
END w_mask_in[41]
PIN w_mask_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.985 0.070 55.055 ;
END
END w_mask_in[42]
PIN w_mask_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.245 0.070 56.315 ;
END
END w_mask_in[43]
PIN w_mask_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.505 0.070 57.575 ;
END
END w_mask_in[44]
PIN w_mask_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.765 0.070 58.835 ;
END
END w_mask_in[45]
PIN w_mask_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 60.025 0.070 60.095 ;
END
END w_mask_in[46]
PIN w_mask_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.285 0.070 61.355 ;
END
END w_mask_in[47]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 63.175 0.070 63.245 ;
END
END rd_out[0]
PIN rd_out[1]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 64.435 0.070 64.505 ;
END
END rd_out[1]
PIN rd_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 65.695 0.070 65.765 ;
END
END rd_out[2]
PIN rd_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 66.955 0.070 67.025 ;
END
END rd_out[3]
PIN rd_out[4]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 68.215 0.070 68.285 ;
END
END rd_out[4]
PIN rd_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.475 0.070 69.545 ;
END
END rd_out[5]
PIN rd_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.735 0.070 70.805 ;
END
END rd_out[6]
PIN rd_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.995 0.070 72.065 ;
END
END rd_out[7]
PIN rd_out[8]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.255 0.070 73.325 ;
END
END rd_out[8]
PIN rd_out[9]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.515 0.070 74.585 ;
END
END rd_out[9]
PIN rd_out[10]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.775 0.070 75.845 ;
END
END rd_out[10]
PIN rd_out[11]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.035 0.070 77.105 ;
END
END rd_out[11]
PIN rd_out[12]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.295 0.070 78.365 ;
END
END rd_out[12]
PIN rd_out[13]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.555 0.070 79.625 ;
END
END rd_out[13]
PIN rd_out[14]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.815 0.070 80.885 ;
END
END rd_out[14]
PIN rd_out[15]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.075 0.070 82.145 ;
END
END rd_out[15]
PIN rd_out[16]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.335 0.070 83.405 ;
END
END rd_out[16]
PIN rd_out[17]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.595 0.070 84.665 ;
END
END rd_out[17]
PIN rd_out[18]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.855 0.070 85.925 ;
END
END rd_out[18]
PIN rd_out[19]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.115 0.070 87.185 ;
END
END rd_out[19]
PIN rd_out[20]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.375 0.070 88.445 ;
END
END rd_out[20]
PIN rd_out[21]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.635 0.070 89.705 ;
END
END rd_out[21]
PIN rd_out[22]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.895 0.070 90.965 ;
END
END rd_out[22]
PIN rd_out[23]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.155 0.070 92.225 ;
END
END rd_out[23]
PIN rd_out[24]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 93.415 0.070 93.485 ;
END
END rd_out[24]
PIN rd_out[25]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.675 0.070 94.745 ;
END
END rd_out[25]
PIN rd_out[26]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 95.935 0.070 96.005 ;
END
END rd_out[26]
PIN rd_out[27]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 97.195 0.070 97.265 ;
END
END rd_out[27]
PIN rd_out[28]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 98.455 0.070 98.525 ;
END
END rd_out[28]
PIN rd_out[29]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 99.715 0.070 99.785 ;
END
END rd_out[29]
PIN rd_out[30]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 100.975 0.070 101.045 ;
END
END rd_out[30]
PIN rd_out[31]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 102.235 0.070 102.305 ;
END
END rd_out[31]
PIN rd_out[32]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.495 0.070 103.565 ;
END
END rd_out[32]
PIN rd_out[33]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 104.755 0.070 104.825 ;
END
END rd_out[33]
PIN rd_out[34]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 106.015 0.070 106.085 ;
END
END rd_out[34]
PIN rd_out[35]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 107.275 0.070 107.345 ;
END
END rd_out[35]
PIN rd_out[36]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 108.535 0.070 108.605 ;
END
END rd_out[36]
PIN rd_out[37]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 109.795 0.070 109.865 ;
END
END rd_out[37]
PIN rd_out[38]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 111.055 0.070 111.125 ;
END
END rd_out[38]
PIN rd_out[39]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 112.315 0.070 112.385 ;
END
END rd_out[39]
PIN rd_out[40]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 113.575 0.070 113.645 ;
END
END rd_out[40]
PIN rd_out[41]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 114.835 0.070 114.905 ;
END
END rd_out[41]
PIN rd_out[42]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 116.095 0.070 116.165 ;
END
END rd_out[42]
PIN rd_out[43]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 117.355 0.070 117.425 ;
END
END rd_out[43]
PIN rd_out[44]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 118.615 0.070 118.685 ;
END
END rd_out[44]
PIN rd_out[45]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 119.875 0.070 119.945 ;
END
END rd_out[45]
PIN rd_out[46]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 121.135 0.070 121.205 ;
END
END rd_out[46]
PIN rd_out[47]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 122.395 0.070 122.465 ;
END
END rd_out[47]
PIN wd_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 124.285 0.070 124.355 ;
END
END wd_in[0]
PIN wd_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 125.545 0.070 125.615 ;
END
END wd_in[1]
PIN wd_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 126.805 0.070 126.875 ;
END
END wd_in[2]
PIN wd_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 128.065 0.070 128.135 ;
END
END wd_in[3]
PIN wd_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 129.325 0.070 129.395 ;
END
END wd_in[4]
PIN wd_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 130.585 0.070 130.655 ;
END
END wd_in[5]
PIN wd_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 131.845 0.070 131.915 ;
END
END wd_in[6]
PIN wd_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 133.105 0.070 133.175 ;
END
END wd_in[7]
PIN wd_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 134.365 0.070 134.435 ;
END
END wd_in[8]
PIN wd_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 135.625 0.070 135.695 ;
END
END wd_in[9]
PIN wd_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 136.885 0.070 136.955 ;
END
END wd_in[10]
PIN wd_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 138.145 0.070 138.215 ;
END
END wd_in[11]
PIN wd_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 139.405 0.070 139.475 ;
END
END wd_in[12]
PIN wd_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 140.665 0.070 140.735 ;
END
END wd_in[13]
PIN wd_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 141.925 0.070 141.995 ;
END
END wd_in[14]
PIN wd_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 143.185 0.070 143.255 ;
END
END wd_in[15]
PIN wd_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 144.445 0.070 144.515 ;
END
END wd_in[16]
PIN wd_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 145.705 0.070 145.775 ;
END
END wd_in[17]
PIN wd_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 146.965 0.070 147.035 ;
END
END wd_in[18]
PIN wd_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 148.225 0.070 148.295 ;
END
END wd_in[19]
PIN wd_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 149.485 0.070 149.555 ;
END
END wd_in[20]
PIN wd_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 150.745 0.070 150.815 ;
END
END wd_in[21]
PIN wd_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 152.005 0.070 152.075 ;
END
END wd_in[22]
PIN wd_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 153.265 0.070 153.335 ;
END
END wd_in[23]
PIN wd_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 154.525 0.070 154.595 ;
END
END wd_in[24]
PIN wd_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 155.785 0.070 155.855 ;
END
END wd_in[25]
PIN wd_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 157.045 0.070 157.115 ;
END
END wd_in[26]
PIN wd_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 158.305 0.070 158.375 ;
END
END wd_in[27]
PIN wd_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 159.565 0.070 159.635 ;
END
END wd_in[28]
PIN wd_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 160.825 0.070 160.895 ;
END
END wd_in[29]
PIN wd_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 162.085 0.070 162.155 ;
END
END wd_in[30]
PIN wd_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 163.345 0.070 163.415 ;
END
END wd_in[31]
PIN wd_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 164.605 0.070 164.675 ;
END
END wd_in[32]
PIN wd_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 165.865 0.070 165.935 ;
END
END wd_in[33]
PIN wd_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 167.125 0.070 167.195 ;
END
END wd_in[34]
PIN wd_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 168.385 0.070 168.455 ;
END
END wd_in[35]
PIN wd_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 169.645 0.070 169.715 ;
END
END wd_in[36]
PIN wd_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 170.905 0.070 170.975 ;
END
END wd_in[37]
PIN wd_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 172.165 0.070 172.235 ;
END
END wd_in[38]
PIN wd_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 173.425 0.070 173.495 ;
END
END wd_in[39]
PIN wd_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 174.685 0.070 174.755 ;
END
END wd_in[40]
PIN wd_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 175.945 0.070 176.015 ;
END
END wd_in[41]
PIN wd_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 177.205 0.070 177.275 ;
END
END wd_in[42]
PIN wd_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 178.465 0.070 178.535 ;
END
END wd_in[43]
PIN wd_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 179.725 0.070 179.795 ;
END
END wd_in[44]
PIN wd_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 180.985 0.070 181.055 ;
END
END wd_in[45]
PIN wd_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 182.245 0.070 182.315 ;
END
END wd_in[46]
PIN wd_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 183.505 0.070 183.575 ;
END
END wd_in[47]
PIN addr_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 185.395 0.070 185.465 ;
END
END addr_in[0]
PIN addr_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 186.655 0.070 186.725 ;
END
END addr_in[1]
PIN addr_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 187.915 0.070 187.985 ;
END
END addr_in[2]
PIN addr_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 189.175 0.070 189.245 ;
END
END addr_in[3]
PIN addr_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 190.435 0.070 190.505 ;
END
END addr_in[4]
PIN addr_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 191.695 0.070 191.765 ;
END
END addr_in[5]
PIN addr_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 192.955 0.070 193.025 ;
END
END addr_in[6]
PIN addr_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 194.215 0.070 194.285 ;
END
END addr_in[7]
PIN we_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 196.105 0.070 196.175 ;
END
END we_in
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 197.365 0.070 197.435 ;
END
END ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 198.625 0.070 198.695 ;
END
END clk
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER metal4 ;
RECT 1.960 2.100 2.240 205.100 ;
RECT 5.320 2.100 5.600 205.100 ;
RECT 8.680 2.100 8.960 205.100 ;
RECT 12.040 2.100 12.320 205.100 ;
RECT 15.400 2.100 15.680 205.100 ;
RECT 18.760 2.100 19.040 205.100 ;
RECT 22.120 2.100 22.400 205.100 ;
RECT 25.480 2.100 25.760 205.100 ;
RECT 28.840 2.100 29.120 205.100 ;
RECT 32.200 2.100 32.480 205.100 ;
RECT 35.560 2.100 35.840 205.100 ;
RECT 38.920 2.100 39.200 205.100 ;
RECT 42.280 2.100 42.560 205.100 ;
RECT 45.640 2.100 45.920 205.100 ;
RECT 49.000 2.100 49.280 205.100 ;
RECT 52.360 2.100 52.640 205.100 ;
RECT 55.720 2.100 56.000 205.100 ;
RECT 59.080 2.100 59.360 205.100 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER metal4 ;
RECT 3.640 2.100 3.920 205.100 ;
RECT 7.000 2.100 7.280 205.100 ;
RECT 10.360 2.100 10.640 205.100 ;
RECT 13.720 2.100 14.000 205.100 ;
RECT 17.080 2.100 17.360 205.100 ;
RECT 20.440 2.100 20.720 205.100 ;
RECT 23.800 2.100 24.080 205.100 ;
RECT 27.160 2.100 27.440 205.100 ;
RECT 30.520 2.100 30.800 205.100 ;
RECT 33.880 2.100 34.160 205.100 ;
RECT 37.240 2.100 37.520 205.100 ;
RECT 40.600 2.100 40.880 205.100 ;
RECT 43.960 2.100 44.240 205.100 ;
RECT 47.320 2.100 47.600 205.100 ;
RECT 50.680 2.100 50.960 205.100 ;
RECT 54.040 2.100 54.320 205.100 ;
RECT 57.400 2.100 57.680 205.100 ;
RECT 60.760 2.100 61.040 205.100 ;
END
END VDD
OBS
LAYER metal1 ;
RECT 0 0 64.030 207.200 ;
LAYER metal2 ;
RECT 0 0 64.030 207.200 ;
LAYER metal3 ;
RECT 0.070 0 64.030 207.200 ;
RECT 0 0.000 0.070 2.065 ;
RECT 0 2.135 0.070 3.325 ;
RECT 0 3.395 0.070 4.585 ;
RECT 0 4.655 0.070 5.845 ;
RECT 0 5.915 0.070 7.105 ;
RECT 0 7.175 0.070 8.365 ;
RECT 0 8.435 0.070 9.625 ;
RECT 0 9.695 0.070 10.885 ;
RECT 0 10.955 0.070 12.145 ;
RECT 0 12.215 0.070 13.405 ;
RECT 0 13.475 0.070 14.665 ;
RECT 0 14.735 0.070 15.925 ;
RECT 0 15.995 0.070 17.185 ;
RECT 0 17.255 0.070 18.445 ;
RECT 0 18.515 0.070 19.705 ;
RECT 0 19.775 0.070 20.965 ;
RECT 0 21.035 0.070 22.225 ;
RECT 0 22.295 0.070 23.485 ;
RECT 0 23.555 0.070 24.745 ;
RECT 0 24.815 0.070 26.005 ;
RECT 0 26.075 0.070 27.265 ;
RECT 0 27.335 0.070 28.525 ;
RECT 0 28.595 0.070 29.785 ;
RECT 0 29.855 0.070 31.045 ;
RECT 0 31.115 0.070 32.305 ;
RECT 0 32.375 0.070 33.565 ;
RECT 0 33.635 0.070 34.825 ;
RECT 0 34.895 0.070 36.085 ;
RECT 0 36.155 0.070 37.345 ;
RECT 0 37.415 0.070 38.605 ;
RECT 0 38.675 0.070 39.865 ;
RECT 0 39.935 0.070 41.125 ;
RECT 0 41.195 0.070 42.385 ;
RECT 0 42.455 0.070 43.645 ;
RECT 0 43.715 0.070 44.905 ;
RECT 0 44.975 0.070 46.165 ;
RECT 0 46.235 0.070 47.425 ;
RECT 0 47.495 0.070 48.685 ;
RECT 0 48.755 0.070 49.945 ;
RECT 0 50.015 0.070 51.205 ;
RECT 0 51.275 0.070 52.465 ;
RECT 0 52.535 0.070 53.725 ;
RECT 0 53.795 0.070 54.985 ;
RECT 0 55.055 0.070 56.245 ;
RECT 0 56.315 0.070 57.505 ;
RECT 0 57.575 0.070 58.765 ;
RECT 0 58.835 0.070 60.025 ;
RECT 0 60.095 0.070 61.285 ;
RECT 0 61.355 0.070 63.175 ;
RECT 0 63.245 0.070 64.435 ;
RECT 0 64.505 0.070 65.695 ;
RECT 0 65.765 0.070 66.955 ;
RECT 0 67.025 0.070 68.215 ;
RECT 0 68.285 0.070 69.475 ;
RECT 0 69.545 0.070 70.735 ;
RECT 0 70.805 0.070 71.995 ;
RECT 0 72.065 0.070 73.255 ;
RECT 0 73.325 0.070 74.515 ;
RECT 0 74.585 0.070 75.775 ;
RECT 0 75.845 0.070 77.035 ;
RECT 0 77.105 0.070 78.295 ;
RECT 0 78.365 0.070 79.555 ;
RECT 0 79.625 0.070 80.815 ;
RECT 0 80.885 0.070 82.075 ;
RECT 0 82.145 0.070 83.335 ;
RECT 0 83.405 0.070 84.595 ;
RECT 0 84.665 0.070 85.855 ;
RECT 0 85.925 0.070 87.115 ;
RECT 0 87.185 0.070 88.375 ;
RECT 0 88.445 0.070 89.635 ;
RECT 0 89.705 0.070 90.895 ;
RECT 0 90.965 0.070 92.155 ;
RECT 0 92.225 0.070 93.415 ;
RECT 0 93.485 0.070 94.675 ;
RECT 0 94.745 0.070 95.935 ;
RECT 0 96.005 0.070 97.195 ;
RECT 0 97.265 0.070 98.455 ;
RECT 0 98.525 0.070 99.715 ;
RECT 0 99.785 0.070 100.975 ;
RECT 0 101.045 0.070 102.235 ;
RECT 0 102.305 0.070 103.495 ;
RECT 0 103.565 0.070 104.755 ;
RECT 0 104.825 0.070 106.015 ;
RECT 0 106.085 0.070 107.275 ;
RECT 0 107.345 0.070 108.535 ;
RECT 0 108.605 0.070 109.795 ;
RECT 0 109.865 0.070 111.055 ;
RECT 0 111.125 0.070 112.315 ;
RECT 0 112.385 0.070 113.575 ;
RECT 0 113.645 0.070 114.835 ;
RECT 0 114.905 0.070 116.095 ;
RECT 0 116.165 0.070 117.355 ;
RECT 0 117.425 0.070 118.615 ;
RECT 0 118.685 0.070 119.875 ;
RECT 0 119.945 0.070 121.135 ;
RECT 0 121.205 0.070 122.395 ;
RECT 0 122.465 0.070 124.285 ;
RECT 0 124.355 0.070 125.545 ;
RECT 0 125.615 0.070 126.805 ;
RECT 0 126.875 0.070 128.065 ;
RECT 0 128.135 0.070 129.325 ;
RECT 0 129.395 0.070 130.585 ;
RECT 0 130.655 0.070 131.845 ;
RECT 0 131.915 0.070 133.105 ;
RECT 0 133.175 0.070 134.365 ;
RECT 0 134.435 0.070 135.625 ;
RECT 0 135.695 0.070 136.885 ;
RECT 0 136.955 0.070 138.145 ;
RECT 0 138.215 0.070 139.405 ;
RECT 0 139.475 0.070 140.665 ;
RECT 0 140.735 0.070 141.925 ;
RECT 0 141.995 0.070 143.185 ;
RECT 0 143.255 0.070 144.445 ;
RECT 0 144.515 0.070 145.705 ;
RECT 0 145.775 0.070 146.965 ;
RECT 0 147.035 0.070 148.225 ;
RECT 0 148.295 0.070 149.485 ;
RECT 0 149.555 0.070 150.745 ;
RECT 0 150.815 0.070 152.005 ;
RECT 0 152.075 0.070 153.265 ;
RECT 0 153.335 0.070 154.525 ;
RECT 0 154.595 0.070 155.785 ;
RECT 0 155.855 0.070 157.045 ;
RECT 0 157.115 0.070 158.305 ;
RECT 0 158.375 0.070 159.565 ;
RECT 0 159.635 0.070 160.825 ;
RECT 0 160.895 0.070 162.085 ;
RECT 0 162.155 0.070 163.345 ;
RECT 0 163.415 0.070 164.605 ;
RECT 0 164.675 0.070 165.865 ;
RECT 0 165.935 0.070 167.125 ;
RECT 0 167.195 0.070 168.385 ;
RECT 0 168.455 0.070 169.645 ;
RECT 0 169.715 0.070 170.905 ;
RECT 0 170.975 0.070 172.165 ;
RECT 0 172.235 0.070 173.425 ;
RECT 0 173.495 0.070 174.685 ;
RECT 0 174.755 0.070 175.945 ;
RECT 0 176.015 0.070 177.205 ;
RECT 0 177.275 0.070 178.465 ;
RECT 0 178.535 0.070 179.725 ;
RECT 0 179.795 0.070 180.985 ;
RECT 0 181.055 0.070 182.245 ;
RECT 0 182.315 0.070 183.505 ;
RECT 0 183.575 0.070 185.395 ;
RECT 0 185.465 0.070 186.655 ;
RECT 0 186.725 0.070 187.915 ;
RECT 0 187.985 0.070 189.175 ;
RECT 0 189.245 0.070 190.435 ;
RECT 0 190.505 0.070 191.695 ;
RECT 0 191.765 0.070 192.955 ;
RECT 0 193.025 0.070 194.215 ;
RECT 0 194.285 0.070 196.105 ;
RECT 0 196.175 0.070 197.365 ;
RECT 0 197.435 0.070 198.625 ;
RECT 0 198.695 0.070 207.200 ;
LAYER metal4 ;
RECT 0 0 64.030 2.100 ;
RECT 0 205.100 64.030 207.200 ;
RECT 0.000 2.100 1.960 205.100 ;
RECT 2.240 2.100 3.640 205.100 ;
RECT 3.920 2.100 5.320 205.100 ;
RECT 5.600 2.100 7.000 205.100 ;
RECT 7.280 2.100 8.680 205.100 ;
RECT 8.960 2.100 10.360 205.100 ;
RECT 10.640 2.100 12.040 205.100 ;
RECT 12.320 2.100 13.720 205.100 ;
RECT 14.000 2.100 15.400 205.100 ;
RECT 15.680 2.100 17.080 205.100 ;
RECT 17.360 2.100 18.760 205.100 ;
RECT 19.040 2.100 20.440 205.100 ;
RECT 20.720 2.100 22.120 205.100 ;
RECT 22.400 2.100 23.800 205.100 ;
RECT 24.080 2.100 25.480 205.100 ;
RECT 25.760 2.100 27.160 205.100 ;
RECT 27.440 2.100 28.840 205.100 ;
RECT 29.120 2.100 30.520 205.100 ;
RECT 30.800 2.100 32.200 205.100 ;
RECT 32.480 2.100 33.880 205.100 ;
RECT 34.160 2.100 35.560 205.100 ;
RECT 35.840 2.100 37.240 205.100 ;
RECT 37.520 2.100 38.920 205.100 ;
RECT 39.200 2.100 40.600 205.100 ;
RECT 40.880 2.100 42.280 205.100 ;
RECT 42.560 2.100 43.960 205.100 ;
RECT 44.240 2.100 45.640 205.100 ;
RECT 45.920 2.100 47.320 205.100 ;
RECT 47.600 2.100 49.000 205.100 ;
RECT 49.280 2.100 50.680 205.100 ;
RECT 50.960 2.100 52.360 205.100 ;
RECT 52.640 2.100 54.040 205.100 ;
RECT 54.320 2.100 55.720 205.100 ;
RECT 56.000 2.100 57.400 205.100 ;
RECT 57.680 2.100 59.080 205.100 ;
RECT 59.360 2.100 60.760 205.100 ;
RECT 61.040 2.100 64.030 205.100 ;
LAYER OVERLAP ;
RECT 0 0 64.030 207.200 ;
END
END fakeram45_256x48
END LIBRARY
Enablements/NanGate45/lef/fakeram45_32x32.lef 0 → 100644
VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_32x32
FOREIGN fakeram45_32x32 0 0 ;
SYMMETRY X Y R90 ;
SIZE 55.100 BY 33.600 ;
CLASS BLOCK ;
PIN w_mask_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.065 0.070 2.135 ;
END
END w_mask_in[0]
PIN w_mask_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.275 0.070 2.345 ;
END
END w_mask_in[1]
PIN w_mask_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.485 0.070 2.555 ;
END
END w_mask_in[2]
PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.695 0.070 2.765 ;
END
END w_mask_in[3]
PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.905 0.070 2.975 ;
END
END w_mask_in[4]
PIN w_mask_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.115 0.070 3.185 ;
END
END w_mask_in[5]
PIN w_mask_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.325 0.070 3.395 ;
END
END w_mask_in[6]
PIN w_mask_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.535 0.070 3.605 ;
END
END w_mask_in[7]
PIN w_mask_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.745 0.070 3.815 ;
END
END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.955 0.070 4.025 ;
END
END w_mask_in[9]
PIN w_mask_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.165 0.070 4.235 ;
END
END w_mask_in[10]
PIN w_mask_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.375 0.070 4.445 ;
END
END w_mask_in[11]
PIN w_mask_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.585 0.070 4.655 ;
END
END w_mask_in[12]
PIN w_mask_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.795 0.070 4.865 ;
END
END w_mask_in[13]
PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.005 0.070 5.075 ;
END
END w_mask_in[14]
PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.215 0.070 5.285 ;
END
END w_mask_in[15]
PIN w_mask_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.425 0.070 5.495 ;
END
END w_mask_in[16]
PIN w_mask_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.635 0.070 5.705 ;
END
END w_mask_in[17]
PIN w_mask_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.845 0.070 5.915 ;
END
END w_mask_in[18]
PIN w_mask_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.055 0.070 6.125 ;
END
END w_mask_in[19]
PIN w_mask_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.265 0.070 6.335 ;
END
END w_mask_in[20]
PIN w_mask_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.475 0.070 6.545 ;
END
END w_mask_in[21]
PIN w_mask_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.685 0.070 6.755 ;
END
END w_mask_in[22]
PIN w_mask_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.895 0.070 6.965 ;
END
END w_mask_in[23]
PIN w_mask_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.105 0.070 7.175 ;
END
END w_mask_in[24]
PIN w_mask_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.315 0.070 7.385 ;
END
END w_mask_in[25]
PIN w_mask_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.525 0.070 7.595 ;
END
END w_mask_in[26]
PIN w_mask_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.735 0.070 7.805 ;
END
END w_mask_in[27]
PIN w_mask_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.945 0.070 8.015 ;
END
END w_mask_in[28]
PIN w_mask_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.155 0.070 8.225 ;
END
END w_mask_in[29]
PIN w_mask_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.365 0.070 8.435 ;
END
END w_mask_in[30]
PIN w_mask_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.575 0.070 8.645 ;
END
END w_mask_in[31]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.465 0.070 10.535 ;
END
END rd_out[0]
PIN rd_out[1]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.675 0.070 10.745 ;
END
END rd_out[1]
PIN rd_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.885 0.070 10.955 ;
END
END rd_out[2]
PIN rd_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.095 0.070 11.165 ;
END
END rd_out[3]
PIN rd_out[4]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.305 0.070 11.375 ;
END
END rd_out[4]
PIN rd_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.515 0.070 11.585 ;
END
END rd_out[5]
PIN rd_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.725 0.070 11.795 ;
END
END rd_out[6]
PIN rd_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.935 0.070 12.005 ;
END
END rd_out[7]
PIN rd_out[8]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.145 0.070 12.215 ;
END
END rd_out[8]
PIN rd_out[9]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.355 0.070 12.425 ;
END
END rd_out[9]
PIN rd_out[10]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.565 0.070 12.635 ;
END
END rd_out[10]
PIN rd_out[11]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.775 0.070 12.845 ;
END
END rd_out[11]
PIN rd_out[12]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.985 0.070 13.055 ;
END
END rd_out[12]
PIN rd_out[13]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.195 0.070 13.265 ;
END
END rd_out[13]
PIN rd_out[14]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.405 0.070 13.475 ;
END
END rd_out[14]
PIN rd_out[15]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.615 0.070 13.685 ;
END
END rd_out[15]
PIN rd_out[16]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.825 0.070 13.895 ;
END
END rd_out[16]
PIN rd_out[17]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.035 0.070 14.105 ;
END
END rd_out[17]
PIN rd_out[18]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.245 0.070 14.315 ;
END
END rd_out[18]
PIN rd_out[19]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.455 0.070 14.525 ;
END
END rd_out[19]
PIN rd_out[20]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.665 0.070 14.735 ;
END
END rd_out[20]
PIN rd_out[21]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.875 0.070 14.945 ;
END
END rd_out[21]
PIN rd_out[22]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.085 0.070 15.155 ;
END
END rd_out[22]
PIN rd_out[23]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.295 0.070 15.365 ;
END
END rd_out[23]
PIN rd_out[24]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.505 0.070 15.575 ;
END
END rd_out[24]
PIN rd_out[25]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.715 0.070 15.785 ;
END
END rd_out[25]
PIN rd_out[26]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.925 0.070 15.995 ;
END
END rd_out[26]
PIN rd_out[27]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.135 0.070 16.205 ;
END
END rd_out[27]
PIN rd_out[28]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.345 0.070 16.415 ;
END
END rd_out[28]
PIN rd_out[29]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.555 0.070 16.625 ;
END
END rd_out[29]
PIN rd_out[30]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.765 0.070 16.835 ;
END
END rd_out[30]
PIN rd_out[31]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.975 0.070 17.045 ;
END
END rd_out[31]
PIN wd_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.865 0.070 18.935 ;
END
END wd_in[0]
PIN wd_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.075 0.070 19.145 ;
END
END wd_in[1]
PIN wd_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.285 0.070 19.355 ;
END
END wd_in[2]
PIN wd_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.495 0.070 19.565 ;
END
END wd_in[3]
PIN wd_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.705 0.070 19.775 ;
END
END wd_in[4]
PIN wd_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.915 0.070 19.985 ;
END
END wd_in[5]
PIN wd_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.125 0.070 20.195 ;
END
END wd_in[6]
PIN wd_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.335 0.070 20.405 ;
END
END wd_in[7]
PIN wd_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.545 0.070 20.615 ;
END
END wd_in[8]
PIN wd_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.755 0.070 20.825 ;
END
END wd_in[9]
PIN wd_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.965 0.070 21.035 ;
END
END wd_in[10]
PIN wd_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.175 0.070 21.245 ;
END
END wd_in[11]
PIN wd_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.385 0.070 21.455 ;
END
END wd_in[12]
PIN wd_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.595 0.070 21.665 ;
END
END wd_in[13]
PIN wd_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.805 0.070 21.875 ;
END
END wd_in[14]
PIN wd_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.015 0.070 22.085 ;
END
END wd_in[15]
PIN wd_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.225 0.070 22.295 ;
END
END wd_in[16]
PIN wd_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.435 0.070 22.505 ;
END
END wd_in[17]
PIN wd_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.645 0.070 22.715 ;
END
END wd_in[18]
PIN wd_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.855 0.070 22.925 ;
END
END wd_in[19]
PIN wd_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.065 0.070 23.135 ;
END
END wd_in[20]
PIN wd_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.275 0.070 23.345 ;
END
END wd_in[21]
PIN wd_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.485 0.070 23.555 ;
END
END wd_in[22]
PIN wd_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.695 0.070 23.765 ;
END
END wd_in[23]
PIN wd_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.905 0.070 23.975 ;
END
END wd_in[24]
PIN wd_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.115 0.070 24.185 ;
END
END wd_in[25]
PIN wd_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.325 0.070 24.395 ;
END
END wd_in[26]
PIN wd_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.535 0.070 24.605 ;
END
END wd_in[27]
PIN wd_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.745 0.070 24.815 ;
END
END wd_in[28]
PIN wd_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.955 0.070 25.025 ;
END
END wd_in[29]
PIN wd_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.165 0.070 25.235 ;
END
END wd_in[30]
PIN wd_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.375 0.070 25.445 ;
END
END wd_in[31]
PIN addr_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.265 0.070 27.335 ;
END
END addr_in[0]
PIN addr_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.475 0.070 27.545 ;
END
END addr_in[1]
PIN addr_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.685 0.070 27.755 ;
END
END addr_in[2]
PIN addr_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.895 0.070 27.965 ;
END
END addr_in[3]
PIN addr_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 28.105 0.070 28.175 ;
END
END addr_in[4]
PIN we_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 29.995 0.070 30.065 ;
END
END we_in
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 30.205 0.070 30.275 ;
END
END ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 30.415 0.070 30.485 ;
END
END clk
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER metal4 ;
RECT 1.960 2.100 2.240 31.500 ;
RECT 5.320 2.100 5.600 31.500 ;
RECT 8.680 2.100 8.960 31.500 ;
RECT 12.040 2.100 12.320 31.500 ;
RECT 15.400 2.100 15.680 31.500 ;
RECT 18.760 2.100 19.040 31.500 ;
RECT 22.120 2.100 22.400 31.500 ;
RECT 25.480 2.100 25.760 31.500 ;
RECT 28.840 2.100 29.120 31.500 ;
RECT 32.200 2.100 32.480 31.500 ;
RECT 35.560 2.100 35.840 31.500 ;
RECT 38.920 2.100 39.200 31.500 ;
RECT 42.280 2.100 42.560 31.500 ;
RECT 45.640 2.100 45.920 31.500 ;
RECT 49.000 2.100 49.280 31.500 ;
RECT 52.360 2.100 52.640 31.500 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER metal4 ;
RECT 3.640 2.100 3.920 31.500 ;
RECT 7.000 2.100 7.280 31.500 ;
RECT 10.360 2.100 10.640 31.500 ;
RECT 13.720 2.100 14.000 31.500 ;
RECT 17.080 2.100 17.360 31.500 ;
RECT 20.440 2.100 20.720 31.500 ;
RECT 23.800 2.100 24.080 31.500 ;
RECT 27.160 2.100 27.440 31.500 ;
RECT 30.520 2.100 30.800 31.500 ;
RECT 33.880 2.100 34.160 31.500 ;
RECT 37.240 2.100 37.520 31.500 ;
RECT 40.600 2.100 40.880 31.500 ;
RECT 43.960 2.100 44.240 31.500 ;
RECT 47.320 2.100 47.600 31.500 ;
RECT 50.680 2.100 50.960 31.500 ;
END
END VDD
OBS
LAYER metal1 ;
RECT 0 0 55.100 33.600 ;
LAYER metal2 ;
RECT 0 0 55.100 33.600 ;
LAYER metal3 ;
RECT 0.070 0 55.100 33.600 ;
RECT 0 0.000 0.070 2.065 ;
RECT 0 2.135 0.070 2.275 ;
RECT 0 2.345 0.070 2.485 ;
RECT 0 2.555 0.070 2.695 ;
RECT 0 2.765 0.070 2.905 ;
RECT 0 2.975 0.070 3.115 ;
RECT 0 3.185 0.070 3.325 ;
RECT 0 3.395 0.070 3.535 ;
RECT 0 3.605 0.070 3.745 ;
RECT 0 3.815 0.070 3.955 ;
RECT 0 4.025 0.070 4.165 ;
RECT 0 4.235 0.070 4.375 ;
RECT 0 4.445 0.070 4.585 ;
RECT 0 4.655 0.070 4.795 ;
RECT 0 4.865 0.070 5.005 ;
RECT 0 5.075 0.070 5.215 ;
RECT 0 5.285 0.070 5.425 ;
RECT 0 5.495 0.070 5.635 ;
RECT 0 5.705 0.070 5.845 ;
RECT 0 5.915 0.070 6.055 ;
RECT 0 6.125 0.070 6.265 ;
RECT 0 6.335 0.070 6.475 ;
RECT 0 6.545 0.070 6.685 ;
RECT 0 6.755 0.070 6.895 ;
RECT 0 6.965 0.070 7.105 ;
RECT 0 7.175 0.070 7.315 ;
RECT 0 7.385 0.070 7.525 ;
RECT 0 7.595 0.070 7.735 ;
RECT 0 7.805 0.070 7.945 ;
RECT 0 8.015 0.070 8.155 ;
RECT 0 8.225 0.070 8.365 ;
RECT 0 8.435 0.070 8.575 ;
RECT 0 8.645 0.070 10.465 ;
RECT 0 10.535 0.070 10.675 ;
RECT 0 10.745 0.070 10.885 ;
RECT 0 10.955 0.070 11.095 ;
RECT 0 11.165 0.070 11.305 ;
RECT 0 11.375 0.070 11.515 ;
RECT 0 11.585 0.070 11.725 ;
RECT 0 11.795 0.070 11.935 ;
RECT 0 12.005 0.070 12.145 ;
RECT 0 12.215 0.070 12.355 ;
RECT 0 12.425 0.070 12.565 ;
RECT 0 12.635 0.070 12.775 ;
RECT 0 12.845 0.070 12.985 ;
RECT 0 13.055 0.070 13.195 ;
RECT 0 13.265 0.070 13.405 ;
RECT 0 13.475 0.070 13.615 ;
RECT 0 13.685 0.070 13.825 ;
RECT 0 13.895 0.070 14.035 ;
RECT 0 14.105 0.070 14.245 ;
RECT 0 14.315 0.070 14.455 ;
RECT 0 14.525 0.070 14.665 ;
RECT 0 14.735 0.070 14.875 ;
RECT 0 14.945 0.070 15.085 ;
RECT 0 15.155 0.070 15.295 ;
RECT 0 15.365 0.070 15.505 ;
RECT 0 15.575 0.070 15.715 ;
RECT 0 15.785 0.070 15.925 ;
RECT 0 15.995 0.070 16.135 ;
RECT 0 16.205 0.070 16.345 ;
RECT 0 16.415 0.070 16.555 ;
RECT 0 16.625 0.070 16.765 ;
RECT 0 16.835 0.070 16.975 ;
RECT 0 17.045 0.070 18.865 ;
RECT 0 18.935 0.070 19.075 ;
RECT 0 19.145 0.070 19.285 ;
RECT 0 19.355 0.070 19.495 ;
RECT 0 19.565 0.070 19.705 ;
RECT 0 19.775 0.070 19.915 ;
RECT 0 19.985 0.070 20.125 ;
RECT 0 20.195 0.070 20.335 ;
RECT 0 20.405 0.070 20.545 ;
RECT 0 20.615 0.070 20.755 ;
RECT 0 20.825 0.070 20.965 ;
RECT 0 21.035 0.070 21.175 ;
RECT 0 21.245 0.070 21.385 ;
RECT 0 21.455 0.070 21.595 ;
RECT 0 21.665 0.070 21.805 ;
RECT 0 21.875 0.070 22.015 ;
RECT 0 22.085 0.070 22.225 ;
RECT 0 22.295 0.070 22.435 ;
RECT 0 22.505 0.070 22.645 ;
RECT 0 22.715 0.070 22.855 ;
RECT 0 22.925 0.070 23.065 ;
RECT 0 23.135 0.070 23.275 ;
RECT 0 23.345 0.070 23.485 ;
RECT 0 23.555 0.070 23.695 ;
RECT 0 23.765 0.070 23.905 ;
RECT 0 23.975 0.070 24.115 ;
RECT 0 24.185 0.070 24.325 ;
RECT 0 24.395 0.070 24.535 ;
RECT 0 24.605 0.070 24.745 ;
RECT 0 24.815 0.070 24.955 ;
RECT 0 25.025 0.070 25.165 ;
RECT 0 25.235 0.070 25.375 ;
RECT 0 25.445 0.070 27.265 ;
RECT 0 27.335 0.070 27.475 ;
RECT 0 27.545 0.070 27.685 ;
RECT 0 27.755 0.070 27.895 ;
RECT 0 27.965 0.070 28.105 ;
RECT 0 28.175 0.070 29.995 ;
RECT 0 30.065 0.070 30.205 ;
RECT 0 30.275 0.070 30.415 ;
RECT 0 30.485 0.070 33.600 ;
LAYER metal4 ;
RECT 0 0 55.100 2.100 ;
RECT 0 31.500 55.100 33.600 ;
RECT 0.000 2.100 1.960 31.500 ;
RECT 2.240 2.100 3.640 31.500 ;
RECT 3.920 2.100 5.320 31.500 ;
RECT 5.600 2.100 7.000 31.500 ;
RECT 7.280 2.100 8.680 31.500 ;
RECT 8.960 2.100 10.360 31.500 ;
RECT 10.640 2.100 12.040 31.500 ;
RECT 12.320 2.100 13.720 31.500 ;
RECT 14.000 2.100 15.400 31.500 ;
RECT 15.680 2.100 17.080 31.500 ;
RECT 17.360 2.100 18.760 31.500 ;
RECT 19.040 2.100 20.440 31.500 ;
RECT 20.720 2.100 22.120 31.500 ;
RECT 22.400 2.100 23.800 31.500 ;
RECT 24.080 2.100 25.480 31.500 ;
RECT 25.760 2.100 27.160 31.500 ;
RECT 27.440 2.100 28.840 31.500 ;
RECT 29.120 2.100 30.520 31.500 ;
RECT 30.800 2.100 32.200 31.500 ;
RECT 32.480 2.100 33.880 31.500 ;
RECT 34.160 2.100 35.560 31.500 ;
RECT 35.840 2.100 37.240 31.500 ;
RECT 37.520 2.100 38.920 31.500 ;
RECT 39.200 2.100 40.600 31.500 ;
RECT 40.880 2.100 42.280 31.500 ;
RECT 42.560 2.100 43.960 31.500 ;
RECT 44.240 2.100 45.640 31.500 ;
RECT 45.920 2.100 47.320 31.500 ;
RECT 47.600 2.100 49.000 31.500 ;
RECT 49.280 2.100 50.680 31.500 ;
RECT 50.960 2.100 52.360 31.500 ;
RECT 52.640 2.100 55.100 31.500 ;
LAYER OVERLAP ;
RECT 0 0 55.100 33.600 ;
END
END fakeram45_32x32
END LIBRARY
Enablements/NanGate45/lef/fakeram45_512x64.lef 0 → 100644
VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_512x64
FOREIGN fakeram45_512x64 0 0 ;
SYMMETRY X Y R90 ;
SIZE 110.010 BY 238.000 ;
CLASS BLOCK ;
PIN w_mask_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.065 0.070 2.135 ;
END
END w_mask_in[0]
PIN w_mask_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.115 0.070 3.185 ;
END
END w_mask_in[1]
PIN w_mask_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.165 0.070 4.235 ;
END
END w_mask_in[2]
PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.215 0.070 5.285 ;
END
END w_mask_in[3]
PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.265 0.070 6.335 ;
END
END w_mask_in[4]
PIN w_mask_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.315 0.070 7.385 ;
END
END w_mask_in[5]
PIN w_mask_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.365 0.070 8.435 ;
END
END w_mask_in[6]
PIN w_mask_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.415 0.070 9.485 ;
END
END w_mask_in[7]
PIN w_mask_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.465 0.070 10.535 ;
END
END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.515 0.070 11.585 ;
END
END w_mask_in[9]
PIN w_mask_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.565 0.070 12.635 ;
END
END w_mask_in[10]
PIN w_mask_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.615 0.070 13.685 ;
END
END w_mask_in[11]
PIN w_mask_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.665 0.070 14.735 ;
END
END w_mask_in[12]
PIN w_mask_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.715 0.070 15.785 ;
END
END w_mask_in[13]
PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.765 0.070 16.835 ;
END
END w_mask_in[14]
PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.815 0.070 17.885 ;
END
END w_mask_in[15]
PIN w_mask_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.865 0.070 18.935 ;
END
END w_mask_in[16]
PIN w_mask_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.915 0.070 19.985 ;
END
END w_mask_in[17]
PIN w_mask_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.965 0.070 21.035 ;
END
END w_mask_in[18]
PIN w_mask_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.015 0.070 22.085 ;
END
END w_mask_in[19]
PIN w_mask_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.065 0.070 23.135 ;
END
END w_mask_in[20]
PIN w_mask_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.115 0.070 24.185 ;
END
END w_mask_in[21]
PIN w_mask_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.165 0.070 25.235 ;
END
END w_mask_in[22]
PIN w_mask_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.215 0.070 26.285 ;
END
END w_mask_in[23]
PIN w_mask_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.265 0.070 27.335 ;
END
END w_mask_in[24]
PIN w_mask_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 28.315 0.070 28.385 ;
END
END w_mask_in[25]
PIN w_mask_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 29.365 0.070 29.435 ;
END
END w_mask_in[26]
PIN w_mask_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 30.415 0.070 30.485 ;
END
END w_mask_in[27]
PIN w_mask_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 31.465 0.070 31.535 ;
END
END w_mask_in[28]
PIN w_mask_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 32.515 0.070 32.585 ;
END
END w_mask_in[29]
PIN w_mask_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 33.565 0.070 33.635 ;
END
END w_mask_in[30]
PIN w_mask_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 34.615 0.070 34.685 ;
END
END w_mask_in[31]
PIN w_mask_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 35.665 0.070 35.735 ;
END
END w_mask_in[32]
PIN w_mask_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.715 0.070 36.785 ;
END
END w_mask_in[33]
PIN w_mask_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.765 0.070 37.835 ;
END
END w_mask_in[34]
PIN w_mask_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.815 0.070 38.885 ;
END
END w_mask_in[35]
PIN w_mask_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.865 0.070 39.935 ;
END
END w_mask_in[36]
PIN w_mask_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.915 0.070 40.985 ;
END
END w_mask_in[37]
PIN w_mask_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.965 0.070 42.035 ;
END
END w_mask_in[38]
PIN w_mask_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.015 0.070 43.085 ;
END
END w_mask_in[39]
PIN w_mask_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.065 0.070 44.135 ;
END
END w_mask_in[40]
PIN w_mask_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.115 0.070 45.185 ;
END
END w_mask_in[41]
PIN w_mask_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.165 0.070 46.235 ;
END
END w_mask_in[42]
PIN w_mask_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.215 0.070 47.285 ;
END
END w_mask_in[43]
PIN w_mask_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.265 0.070 48.335 ;
END
END w_mask_in[44]
PIN w_mask_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.315 0.070 49.385 ;
END
END w_mask_in[45]
PIN w_mask_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.365 0.070 50.435 ;
END
END w_mask_in[46]
PIN w_mask_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.415 0.070 51.485 ;
END
END w_mask_in[47]
PIN w_mask_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.465 0.070 52.535 ;
END
END w_mask_in[48]
PIN w_mask_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.515 0.070 53.585 ;
END
END w_mask_in[49]
PIN w_mask_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.565 0.070 54.635 ;
END
END w_mask_in[50]
PIN w_mask_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.615 0.070 55.685 ;
END
END w_mask_in[51]
PIN w_mask_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.665 0.070 56.735 ;
END
END w_mask_in[52]
PIN w_mask_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.715 0.070 57.785 ;
END
END w_mask_in[53]
PIN w_mask_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.765 0.070 58.835 ;
END
END w_mask_in[54]
PIN w_mask_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.815 0.070 59.885 ;
END
END w_mask_in[55]
PIN w_mask_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 60.865 0.070 60.935 ;
END
END w_mask_in[56]
PIN w_mask_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.915 0.070 61.985 ;
END
END w_mask_in[57]
PIN w_mask_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.965 0.070 63.035 ;
END
END w_mask_in[58]
PIN w_mask_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 64.015 0.070 64.085 ;
END
END w_mask_in[59]
PIN w_mask_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 65.065 0.070 65.135 ;
END
END w_mask_in[60]
PIN w_mask_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 66.115 0.070 66.185 ;
END
END w_mask_in[61]
PIN w_mask_in[62]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 67.165 0.070 67.235 ;
END
END w_mask_in[62]
PIN w_mask_in[63]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 68.215 0.070 68.285 ;
END
END w_mask_in[63]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.045 0.070 73.115 ;
END
END rd_out[0]
PIN rd_out[1]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.095 0.070 74.165 ;
END
END rd_out[1]
PIN rd_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.145 0.070 75.215 ;
END
END rd_out[2]
PIN rd_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.195 0.070 76.265 ;
END
END rd_out[3]
PIN rd_out[4]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.245 0.070 77.315 ;
END
END rd_out[4]
PIN rd_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.295 0.070 78.365 ;
END
END rd_out[5]
PIN rd_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.345 0.070 79.415 ;
END
END rd_out[6]
PIN rd_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.395 0.070 80.465 ;
END
END rd_out[7]
PIN rd_out[8]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.445 0.070 81.515 ;
END
END rd_out[8]
PIN rd_out[9]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.495 0.070 82.565 ;
END
END rd_out[9]
PIN rd_out[10]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.545 0.070 83.615 ;
END
END rd_out[10]
PIN rd_out[11]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.595 0.070 84.665 ;
END
END rd_out[11]
PIN rd_out[12]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.645 0.070 85.715 ;
END
END rd_out[12]
PIN rd_out[13]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.695 0.070 86.765 ;
END
END rd_out[13]
PIN rd_out[14]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.745 0.070 87.815 ;
END
END rd_out[14]
PIN rd_out[15]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.795 0.070 88.865 ;
END
END rd_out[15]
PIN rd_out[16]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.845 0.070 89.915 ;
END
END rd_out[16]
PIN rd_out[17]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.895 0.070 90.965 ;
END
END rd_out[17]
PIN rd_out[18]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.945 0.070 92.015 ;
END
END rd_out[18]
PIN rd_out[19]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.995 0.070 93.065 ;
END
END rd_out[19]
PIN rd_out[20]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.045 0.070 94.115 ;
END
END rd_out[20]
PIN rd_out[21]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 95.095 0.070 95.165 ;
END
END rd_out[21]
PIN rd_out[22]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.145 0.070 96.215 ;
END
END rd_out[22]
PIN rd_out[23]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 97.195 0.070 97.265 ;
END
END rd_out[23]
PIN rd_out[24]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 98.245 0.070 98.315 ;
END
END rd_out[24]
PIN rd_out[25]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 99.295 0.070 99.365 ;
END
END rd_out[25]
PIN rd_out[26]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 100.345 0.070 100.415 ;
END
END rd_out[26]
PIN rd_out[27]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 101.395 0.070 101.465 ;
END
END rd_out[27]
PIN rd_out[28]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 102.445 0.070 102.515 ;
END
END rd_out[28]
PIN rd_out[29]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 103.495 0.070 103.565 ;
END
END rd_out[29]
PIN rd_out[30]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 104.545 0.070 104.615 ;
END
END rd_out[30]
PIN rd_out[31]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 105.595 0.070 105.665 ;
END
END rd_out[31]
PIN rd_out[32]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 106.645 0.070 106.715 ;
END
END rd_out[32]
PIN rd_out[33]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 107.695 0.070 107.765 ;
END
END rd_out[33]
PIN rd_out[34]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 108.745 0.070 108.815 ;
END
END rd_out[34]
PIN rd_out[35]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 109.795 0.070 109.865 ;
END
END rd_out[35]
PIN rd_out[36]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 110.845 0.070 110.915 ;
END
END rd_out[36]
PIN rd_out[37]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 111.895 0.070 111.965 ;
END
END rd_out[37]
PIN rd_out[38]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 112.945 0.070 113.015 ;
END
END rd_out[38]
PIN rd_out[39]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 113.995 0.070 114.065 ;
END
END rd_out[39]
PIN rd_out[40]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 115.045 0.070 115.115 ;
END
END rd_out[40]
PIN rd_out[41]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 116.095 0.070 116.165 ;
END
END rd_out[41]
PIN rd_out[42]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 117.145 0.070 117.215 ;
END
END rd_out[42]
PIN rd_out[43]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 118.195 0.070 118.265 ;
END
END rd_out[43]
PIN rd_out[44]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 119.245 0.070 119.315 ;
END
END rd_out[44]
PIN rd_out[45]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 120.295 0.070 120.365 ;
END
END rd_out[45]
PIN rd_out[46]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 121.345 0.070 121.415 ;
END
END rd_out[46]
PIN rd_out[47]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 122.395 0.070 122.465 ;
END
END rd_out[47]
PIN rd_out[48]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 123.445 0.070 123.515 ;
END
END rd_out[48]
PIN rd_out[49]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 124.495 0.070 124.565 ;
END
END rd_out[49]
PIN rd_out[50]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 125.545 0.070 125.615 ;
END
END rd_out[50]
PIN rd_out[51]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 126.595 0.070 126.665 ;
END
END rd_out[51]
PIN rd_out[52]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 127.645 0.070 127.715 ;
END
END rd_out[52]
PIN rd_out[53]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 128.695 0.070 128.765 ;
END
END rd_out[53]
PIN rd_out[54]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 129.745 0.070 129.815 ;
END
END rd_out[54]
PIN rd_out[55]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 130.795 0.070 130.865 ;
END
END rd_out[55]
PIN rd_out[56]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 131.845 0.070 131.915 ;
END
END rd_out[56]
PIN rd_out[57]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 132.895 0.070 132.965 ;
END
END rd_out[57]
PIN rd_out[58]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 133.945 0.070 134.015 ;
END
END rd_out[58]
PIN rd_out[59]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 134.995 0.070 135.065 ;
END
END rd_out[59]
PIN rd_out[60]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 136.045 0.070 136.115 ;
END
END rd_out[60]
PIN rd_out[61]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 137.095 0.070 137.165 ;
END
END rd_out[61]
PIN rd_out[62]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 138.145 0.070 138.215 ;
END
END rd_out[62]
PIN rd_out[63]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 139.195 0.070 139.265 ;
END
END rd_out[63]
PIN wd_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 144.025 0.070 144.095 ;
END
END wd_in[0]
PIN wd_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 145.075 0.070 145.145 ;
END
END wd_in[1]
PIN wd_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 146.125 0.070 146.195 ;
END
END wd_in[2]
PIN wd_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 147.175 0.070 147.245 ;
END
END wd_in[3]
PIN wd_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 148.225 0.070 148.295 ;
END
END wd_in[4]
PIN wd_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 149.275 0.070 149.345 ;
END
END wd_in[5]
PIN wd_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 150.325 0.070 150.395 ;
END
END wd_in[6]
PIN wd_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 151.375 0.070 151.445 ;
END
END wd_in[7]
PIN wd_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 152.425 0.070 152.495 ;
END
END wd_in[8]
PIN wd_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 153.475 0.070 153.545 ;
END
END wd_in[9]
PIN wd_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 154.525 0.070 154.595 ;
END
END wd_in[10]
PIN wd_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 155.575 0.070 155.645 ;
END
END wd_in[11]
PIN wd_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 156.625 0.070 156.695 ;
END
END wd_in[12]
PIN wd_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 157.675 0.070 157.745 ;
END
END wd_in[13]
PIN wd_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 158.725 0.070 158.795 ;
END
END wd_in[14]
PIN wd_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 159.775 0.070 159.845 ;
END
END wd_in[15]
PIN wd_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 160.825 0.070 160.895 ;
END
END wd_in[16]
PIN wd_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 161.875 0.070 161.945 ;
END
END wd_in[17]
PIN wd_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 162.925 0.070 162.995 ;
END
END wd_in[18]
PIN wd_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 163.975 0.070 164.045 ;
END
END wd_in[19]
PIN wd_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 165.025 0.070 165.095 ;
END
END wd_in[20]
PIN wd_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 166.075 0.070 166.145 ;
END
END wd_in[21]
PIN wd_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 167.125 0.070 167.195 ;
END
END wd_in[22]
PIN wd_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 168.175 0.070 168.245 ;
END
END wd_in[23]
PIN wd_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 169.225 0.070 169.295 ;
END
END wd_in[24]
PIN wd_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 170.275 0.070 170.345 ;
END
END wd_in[25]
PIN wd_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 171.325 0.070 171.395 ;
END
END wd_in[26]
PIN wd_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 172.375 0.070 172.445 ;
END
END wd_in[27]
PIN wd_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 173.425 0.070 173.495 ;
END
END wd_in[28]
PIN wd_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 174.475 0.070 174.545 ;
END
END wd_in[29]
PIN wd_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 175.525 0.070 175.595 ;
END
END wd_in[30]
PIN wd_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 176.575 0.070 176.645 ;
END
END wd_in[31]
PIN wd_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 177.625 0.070 177.695 ;
END
END wd_in[32]
PIN wd_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 178.675 0.070 178.745 ;
END
END wd_in[33]
PIN wd_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 179.725 0.070 179.795 ;
END
END wd_in[34]
PIN wd_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 180.775 0.070 180.845 ;
END
END wd_in[35]
PIN wd_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 181.825 0.070 181.895 ;
END
END wd_in[36]
PIN wd_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 182.875 0.070 182.945 ;
END
END wd_in[37]
PIN wd_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 183.925 0.070 183.995 ;
END
END wd_in[38]
PIN wd_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 184.975 0.070 185.045 ;
END
END wd_in[39]
PIN wd_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 186.025 0.070 186.095 ;
END
END wd_in[40]
PIN wd_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 187.075 0.070 187.145 ;
END
END wd_in[41]
PIN wd_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 188.125 0.070 188.195 ;
END
END wd_in[42]
PIN wd_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 189.175 0.070 189.245 ;
END
END wd_in[43]
PIN wd_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 190.225 0.070 190.295 ;
END
END wd_in[44]
PIN wd_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 191.275 0.070 191.345 ;
END
END wd_in[45]
PIN wd_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 192.325 0.070 192.395 ;
END
END wd_in[46]
PIN wd_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 193.375 0.070 193.445 ;
END
END wd_in[47]
PIN wd_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 194.425 0.070 194.495 ;
END
END wd_in[48]
PIN wd_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 195.475 0.070 195.545 ;
END
END wd_in[49]
PIN wd_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 196.525 0.070 196.595 ;
END
END wd_in[50]
PIN wd_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 197.575 0.070 197.645 ;
END
END wd_in[51]
PIN wd_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 198.625 0.070 198.695 ;
END
END wd_in[52]
PIN wd_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 199.675 0.070 199.745 ;
END
END wd_in[53]
PIN wd_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 200.725 0.070 200.795 ;
END
END wd_in[54]
PIN wd_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 201.775 0.070 201.845 ;
END
END wd_in[55]
PIN wd_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 202.825 0.070 202.895 ;
END
END wd_in[56]
PIN wd_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 203.875 0.070 203.945 ;
END
END wd_in[57]
PIN wd_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 204.925 0.070 204.995 ;
END
END wd_in[58]
PIN wd_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 205.975 0.070 206.045 ;
END
END wd_in[59]
PIN wd_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 207.025 0.070 207.095 ;
END
END wd_in[60]
PIN wd_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 208.075 0.070 208.145 ;
END
END wd_in[61]
PIN wd_in[62]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 209.125 0.070 209.195 ;
END
END wd_in[62]
PIN wd_in[63]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 210.175 0.070 210.245 ;
END
END wd_in[63]
PIN addr_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 215.005 0.070 215.075 ;
END
END addr_in[0]
PIN addr_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 216.055 0.070 216.125 ;
END
END addr_in[1]
PIN addr_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 217.105 0.070 217.175 ;
END
END addr_in[2]
PIN addr_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 218.155 0.070 218.225 ;
END
END addr_in[3]
PIN addr_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 219.205 0.070 219.275 ;
END
END addr_in[4]
PIN addr_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 220.255 0.070 220.325 ;
END
END addr_in[5]
PIN addr_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 221.305 0.070 221.375 ;
END
END addr_in[6]
PIN addr_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 222.355 0.070 222.425 ;
END
END addr_in[7]
PIN addr_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 223.405 0.070 223.475 ;
END
END addr_in[8]
PIN we_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 228.235 0.070 228.305 ;
END
END we_in
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 229.285 0.070 229.355 ;
END
END ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 230.335 0.070 230.405 ;
END
END clk
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER metal4 ;
RECT 1.960 2.100 2.240 235.900 ;
RECT 5.320 2.100 5.600 235.900 ;
RECT 8.680 2.100 8.960 235.900 ;
RECT 12.040 2.100 12.320 235.900 ;
RECT 15.400 2.100 15.680 235.900 ;
RECT 18.760 2.100 19.040 235.900 ;
RECT 22.120 2.100 22.400 235.900 ;
RECT 25.480 2.100 25.760 235.900 ;
RECT 28.840 2.100 29.120 235.900 ;
RECT 32.200 2.100 32.480 235.900 ;
RECT 35.560 2.100 35.840 235.900 ;
RECT 38.920 2.100 39.200 235.900 ;
RECT 42.280 2.100 42.560 235.900 ;
RECT 45.640 2.100 45.920 235.900 ;
RECT 49.000 2.100 49.280 235.900 ;
RECT 52.360 2.100 52.640 235.900 ;
RECT 55.720 2.100 56.000 235.900 ;
RECT 59.080 2.100 59.360 235.900 ;
RECT 62.440 2.100 62.720 235.900 ;
RECT 65.800 2.100 66.080 235.900 ;
RECT 69.160 2.100 69.440 235.900 ;
RECT 72.520 2.100 72.800 235.900 ;
RECT 75.880 2.100 76.160 235.900 ;
RECT 79.240 2.100 79.520 235.900 ;
RECT 82.600 2.100 82.880 235.900 ;
RECT 85.960 2.100 86.240 235.900 ;
RECT 89.320 2.100 89.600 235.900 ;
RECT 92.680 2.100 92.960 235.900 ;
RECT 96.040 2.100 96.320 235.900 ;
RECT 99.400 2.100 99.680 235.900 ;
RECT 102.760 2.100 103.040 235.900 ;
RECT 106.120 2.100 106.400 235.900 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER metal4 ;
RECT 3.640 2.100 3.920 235.900 ;
RECT 7.000 2.100 7.280 235.900 ;
RECT 10.360 2.100 10.640 235.900 ;
RECT 13.720 2.100 14.000 235.900 ;
RECT 17.080 2.100 17.360 235.900 ;
RECT 20.440 2.100 20.720 235.900 ;
RECT 23.800 2.100 24.080 235.900 ;
RECT 27.160 2.100 27.440 235.900 ;
RECT 30.520 2.100 30.800 235.900 ;
RECT 33.880 2.100 34.160 235.900 ;
RECT 37.240 2.100 37.520 235.900 ;
RECT 40.600 2.100 40.880 235.900 ;
RECT 43.960 2.100 44.240 235.900 ;
RECT 47.320 2.100 47.600 235.900 ;
RECT 50.680 2.100 50.960 235.900 ;
RECT 54.040 2.100 54.320 235.900 ;
RECT 57.400 2.100 57.680 235.900 ;
RECT 60.760 2.100 61.040 235.900 ;
RECT 64.120 2.100 64.400 235.900 ;
RECT 67.480 2.100 67.760 235.900 ;
RECT 70.840 2.100 71.120 235.900 ;
RECT 74.200 2.100 74.480 235.900 ;
RECT 77.560 2.100 77.840 235.900 ;
RECT 80.920 2.100 81.200 235.900 ;
RECT 84.280 2.100 84.560 235.900 ;
RECT 87.640 2.100 87.920 235.900 ;
RECT 91.000 2.100 91.280 235.900 ;
RECT 94.360 2.100 94.640 235.900 ;
RECT 97.720 2.100 98.000 235.900 ;
RECT 101.080 2.100 101.360 235.900 ;
RECT 104.440 2.100 104.720 235.900 ;
END
END VDD
OBS
LAYER metal1 ;
RECT 0 0 110.010 238.000 ;
LAYER metal2 ;
RECT 0 0 110.010 238.000 ;
LAYER metal3 ;
RECT 0.070 0 110.010 238.000 ;
RECT 0 0.000 0.070 2.065 ;
RECT 0 2.135 0.070 3.115 ;
RECT 0 3.185 0.070 4.165 ;
RECT 0 4.235 0.070 5.215 ;
RECT 0 5.285 0.070 6.265 ;
RECT 0 6.335 0.070 7.315 ;
RECT 0 7.385 0.070 8.365 ;
RECT 0 8.435 0.070 9.415 ;
RECT 0 9.485 0.070 10.465 ;
RECT 0 10.535 0.070 11.515 ;
RECT 0 11.585 0.070 12.565 ;
RECT 0 12.635 0.070 13.615 ;
RECT 0 13.685 0.070 14.665 ;
RECT 0 14.735 0.070 15.715 ;
RECT 0 15.785 0.070 16.765 ;
RECT 0 16.835 0.070 17.815 ;
RECT 0 17.885 0.070 18.865 ;
RECT 0 18.935 0.070 19.915 ;
RECT 0 19.985 0.070 20.965 ;
RECT 0 21.035 0.070 22.015 ;
RECT 0 22.085 0.070 23.065 ;
RECT 0 23.135 0.070 24.115 ;
RECT 0 24.185 0.070 25.165 ;
RECT 0 25.235 0.070 26.215 ;
RECT 0 26.285 0.070 27.265 ;
RECT 0 27.335 0.070 28.315 ;
RECT 0 28.385 0.070 29.365 ;
RECT 0 29.435 0.070 30.415 ;
RECT 0 30.485 0.070 31.465 ;
RECT 0 31.535 0.070 32.515 ;
RECT 0 32.585 0.070 33.565 ;
RECT 0 33.635 0.070 34.615 ;
RECT 0 34.685 0.070 35.665 ;
RECT 0 35.735 0.070 36.715 ;
RECT 0 36.785 0.070 37.765 ;
RECT 0 37.835 0.070 38.815 ;
RECT 0 38.885 0.070 39.865 ;
RECT 0 39.935 0.070 40.915 ;
RECT 0 40.985 0.070 41.965 ;
RECT 0 42.035 0.070 43.015 ;
RECT 0 43.085 0.070 44.065 ;
RECT 0 44.135 0.070 45.115 ;
RECT 0 45.185 0.070 46.165 ;
RECT 0 46.235 0.070 47.215 ;
RECT 0 47.285 0.070 48.265 ;
RECT 0 48.335 0.070 49.315 ;
RECT 0 49.385 0.070 50.365 ;
RECT 0 50.435 0.070 51.415 ;
RECT 0 51.485 0.070 52.465 ;
RECT 0 52.535 0.070 53.515 ;
RECT 0 53.585 0.070 54.565 ;
RECT 0 54.635 0.070 55.615 ;
RECT 0 55.685 0.070 56.665 ;
RECT 0 56.735 0.070 57.715 ;
RECT 0 57.785 0.070 58.765 ;
RECT 0 58.835 0.070 59.815 ;
RECT 0 59.885 0.070 60.865 ;
RECT 0 60.935 0.070 61.915 ;
RECT 0 61.985 0.070 62.965 ;
RECT 0 63.035 0.070 64.015 ;
RECT 0 64.085 0.070 65.065 ;
RECT 0 65.135 0.070 66.115 ;
RECT 0 66.185 0.070 67.165 ;
RECT 0 67.235 0.070 68.215 ;
RECT 0 68.285 0.070 73.045 ;
RECT 0 73.115 0.070 74.095 ;
RECT 0 74.165 0.070 75.145 ;
RECT 0 75.215 0.070 76.195 ;
RECT 0 76.265 0.070 77.245 ;
RECT 0 77.315 0.070 78.295 ;
RECT 0 78.365 0.070 79.345 ;
RECT 0 79.415 0.070 80.395 ;
RECT 0 80.465 0.070 81.445 ;
RECT 0 81.515 0.070 82.495 ;
RECT 0 82.565 0.070 83.545 ;
RECT 0 83.615 0.070 84.595 ;
RECT 0 84.665 0.070 85.645 ;
RECT 0 85.715 0.070 86.695 ;
RECT 0 86.765 0.070 87.745 ;
RECT 0 87.815 0.070 88.795 ;
RECT 0 88.865 0.070 89.845 ;
RECT 0 89.915 0.070 90.895 ;
RECT 0 90.965 0.070 91.945 ;
RECT 0 92.015 0.070 92.995 ;
RECT 0 93.065 0.070 94.045 ;
RECT 0 94.115 0.070 95.095 ;
RECT 0 95.165 0.070 96.145 ;
RECT 0 96.215 0.070 97.195 ;
RECT 0 97.265 0.070 98.245 ;
RECT 0 98.315 0.070 99.295 ;
RECT 0 99.365 0.070 100.345 ;
RECT 0 100.415 0.070 101.395 ;
RECT 0 101.465 0.070 102.445 ;
RECT 0 102.515 0.070 103.495 ;
RECT 0 103.565 0.070 104.545 ;
RECT 0 104.615 0.070 105.595 ;
RECT 0 105.665 0.070 106.645 ;
RECT 0 106.715 0.070 107.695 ;
RECT 0 107.765 0.070 108.745 ;
RECT 0 108.815 0.070 109.795 ;
RECT 0 109.865 0.070 110.845 ;
RECT 0 110.915 0.070 111.895 ;
RECT 0 111.965 0.070 112.945 ;
RECT 0 113.015 0.070 113.995 ;
RECT 0 114.065 0.070 115.045 ;
RECT 0 115.115 0.070 116.095 ;
RECT 0 116.165 0.070 117.145 ;
RECT 0 117.215 0.070 118.195 ;
RECT 0 118.265 0.070 119.245 ;
RECT 0 119.315 0.070 120.295 ;
RECT 0 120.365 0.070 121.345 ;
RECT 0 121.415 0.070 122.395 ;
RECT 0 122.465 0.070 123.445 ;
RECT 0 123.515 0.070 124.495 ;
RECT 0 124.565 0.070 125.545 ;
RECT 0 125.615 0.070 126.595 ;
RECT 0 126.665 0.070 127.645 ;
RECT 0 127.715 0.070 128.695 ;
RECT 0 128.765 0.070 129.745 ;
RECT 0 129.815 0.070 130.795 ;
RECT 0 130.865 0.070 131.845 ;
RECT 0 131.915 0.070 132.895 ;
RECT 0 132.965 0.070 133.945 ;
RECT 0 134.015 0.070 134.995 ;
RECT 0 135.065 0.070 136.045 ;
RECT 0 136.115 0.070 137.095 ;
RECT 0 137.165 0.070 138.145 ;
RECT 0 138.215 0.070 139.195 ;
RECT 0 139.265 0.070 144.025 ;
RECT 0 144.095 0.070 145.075 ;
RECT 0 145.145 0.070 146.125 ;
RECT 0 146.195 0.070 147.175 ;
RECT 0 147.245 0.070 148.225 ;
RECT 0 148.295 0.070 149.275 ;
RECT 0 149.345 0.070 150.325 ;
RECT 0 150.395 0.070 151.375 ;
RECT 0 151.445 0.070 152.425 ;
RECT 0 152.495 0.070 153.475 ;
RECT 0 153.545 0.070 154.525 ;
RECT 0 154.595 0.070 155.575 ;
RECT 0 155.645 0.070 156.625 ;
RECT 0 156.695 0.070 157.675 ;
RECT 0 157.745 0.070 158.725 ;
RECT 0 158.795 0.070 159.775 ;
RECT 0 159.845 0.070 160.825 ;
RECT 0 160.895 0.070 161.875 ;
RECT 0 161.945 0.070 162.925 ;
RECT 0 162.995 0.070 163.975 ;
RECT 0 164.045 0.070 165.025 ;
RECT 0 165.095 0.070 166.075 ;
RECT 0 166.145 0.070 167.125 ;
RECT 0 167.195 0.070 168.175 ;
RECT 0 168.245 0.070 169.225 ;
RECT 0 169.295 0.070 170.275 ;
RECT 0 170.345 0.070 171.325 ;
RECT 0 171.395 0.070 172.375 ;
RECT 0 172.445 0.070 173.425 ;
RECT 0 173.495 0.070 174.475 ;
RECT 0 174.545 0.070 175.525 ;
RECT 0 175.595 0.070 176.575 ;
RECT 0 176.645 0.070 177.625 ;
RECT 0 177.695 0.070 178.675 ;
RECT 0 178.745 0.070 179.725 ;
RECT 0 179.795 0.070 180.775 ;
RECT 0 180.845 0.070 181.825 ;
RECT 0 181.895 0.070 182.875 ;
RECT 0 182.945 0.070 183.925 ;
RECT 0 183.995 0.070 184.975 ;
RECT 0 185.045 0.070 186.025 ;
RECT 0 186.095 0.070 187.075 ;
RECT 0 187.145 0.070 188.125 ;
RECT 0 188.195 0.070 189.175 ;
RECT 0 189.245 0.070 190.225 ;
RECT 0 190.295 0.070 191.275 ;
RECT 0 191.345 0.070 192.325 ;
RECT 0 192.395 0.070 193.375 ;
RECT 0 193.445 0.070 194.425 ;
RECT 0 194.495 0.070 195.475 ;
RECT 0 195.545 0.070 196.525 ;
RECT 0 196.595 0.070 197.575 ;
RECT 0 197.645 0.070 198.625 ;
RECT 0 198.695 0.070 199.675 ;
RECT 0 199.745 0.070 200.725 ;
RECT 0 200.795 0.070 201.775 ;
RECT 0 201.845 0.070 202.825 ;
RECT 0 202.895 0.070 203.875 ;
RECT 0 203.945 0.070 204.925 ;
RECT 0 204.995 0.070 205.975 ;
RECT 0 206.045 0.070 207.025 ;
RECT 0 207.095 0.070 208.075 ;
RECT 0 208.145 0.070 209.125 ;
RECT 0 209.195 0.070 210.175 ;
RECT 0 210.245 0.070 215.005 ;
RECT 0 215.075 0.070 216.055 ;
RECT 0 216.125 0.070 217.105 ;
RECT 0 217.175 0.070 218.155 ;
RECT 0 218.225 0.070 219.205 ;
RECT 0 219.275 0.070 220.255 ;
RECT 0 220.325 0.070 221.305 ;
RECT 0 221.375 0.070 222.355 ;
RECT 0 222.425 0.070 223.405 ;
RECT 0 223.475 0.070 228.235 ;
RECT 0 228.305 0.070 229.285 ;
RECT 0 229.355 0.070 230.335 ;
RECT 0 230.405 0.070 238.000 ;
LAYER metal4 ;
RECT 0 0 110.010 2.100 ;
RECT 0 235.900 110.010 238.000 ;
RECT 0.000 2.100 1.960 235.900 ;
RECT 2.240 2.100 3.640 235.900 ;
RECT 3.920 2.100 5.320 235.900 ;
RECT 5.600 2.100 7.000 235.900 ;
RECT 7.280 2.100 8.680 235.900 ;
RECT 8.960 2.100 10.360 235.900 ;
RECT 10.640 2.100 12.040 235.900 ;
RECT 12.320 2.100 13.720 235.900 ;
RECT 14.000 2.100 15.400 235.900 ;
RECT 15.680 2.100 17.080 235.900 ;
RECT 17.360 2.100 18.760 235.900 ;
RECT 19.040 2.100 20.440 235.900 ;
RECT 20.720 2.100 22.120 235.900 ;
RECT 22.400 2.100 23.800 235.900 ;
RECT 24.080 2.100 25.480 235.900 ;
RECT 25.760 2.100 27.160 235.900 ;
RECT 27.440 2.100 28.840 235.900 ;
RECT 29.120 2.100 30.520 235.900 ;
RECT 30.800 2.100 32.200 235.900 ;
RECT 32.480 2.100 33.880 235.900 ;
RECT 34.160 2.100 35.560 235.900 ;
RECT 35.840 2.100 37.240 235.900 ;
RECT 37.520 2.100 38.920 235.900 ;
RECT 39.200 2.100 40.600 235.900 ;
RECT 40.880 2.100 42.280 235.900 ;
RECT 42.560 2.100 43.960 235.900 ;
RECT 44.240 2.100 45.640 235.900 ;
RECT 45.920 2.100 47.320 235.900 ;
RECT 47.600 2.100 49.000 235.900 ;
RECT 49.280 2.100 50.680 235.900 ;
RECT 50.960 2.100 52.360 235.900 ;
RECT 52.640 2.100 54.040 235.900 ;
RECT 54.320 2.100 55.720 235.900 ;
RECT 56.000 2.100 57.400 235.900 ;
RECT 57.680 2.100 59.080 235.900 ;
RECT 59.360 2.100 60.760 235.900 ;
RECT 61.040 2.100 62.440 235.900 ;
RECT 62.720 2.100 64.120 235.900 ;
RECT 64.400 2.100 65.800 235.900 ;
RECT 66.080 2.100 67.480 235.900 ;
RECT 67.760 2.100 69.160 235.900 ;
RECT 69.440 2.100 70.840 235.900 ;
RECT 71.120 2.100 72.520 235.900 ;
RECT 72.800 2.100 74.200 235.900 ;
RECT 74.480 2.100 75.880 235.900 ;
RECT 76.160 2.100 77.560 235.900 ;
RECT 77.840 2.100 79.240 235.900 ;
RECT 79.520 2.100 80.920 235.900 ;
RECT 81.200 2.100 82.600 235.900 ;
RECT 82.880 2.100 84.280 235.900 ;
RECT 84.560 2.100 85.960 235.900 ;
RECT 86.240 2.100 87.640 235.900 ;
RECT 87.920 2.100 89.320 235.900 ;
RECT 89.600 2.100 91.000 235.900 ;
RECT 91.280 2.100 92.680 235.900 ;
RECT 92.960 2.100 94.360 235.900 ;
RECT 94.640 2.100 96.040 235.900 ;
RECT 96.320 2.100 97.720 235.900 ;
RECT 98.000 2.100 99.400 235.900 ;
RECT 99.680 2.100 101.080 235.900 ;
RECT 101.360 2.100 102.760 235.900 ;
RECT 103.040 2.100 104.440 235.900 ;
RECT 104.720 2.100 106.120 235.900 ;
RECT 106.400 2.100 110.010 235.900 ;
LAYER OVERLAP ;
RECT 0 0 110.010 238.000 ;
END
END fakeram45_512x64
END LIBRARY
Enablements/NanGate45/lef/fakeram45_64x124.lef 0 → 100644
VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_64x124
FOREIGN fakeram45_64x124 0 0 ;
SYMMETRY X Y R90 ;
SIZE 80.560 BY 121.800 ;
CLASS BLOCK ;
PIN w_mask_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.065 0.070 2.135 ;
END
END w_mask_in[0]
PIN w_mask_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.275 0.070 2.345 ;
END
END w_mask_in[1]
PIN w_mask_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.485 0.070 2.555 ;
END
END w_mask_in[2]
PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.695 0.070 2.765 ;
END
END w_mask_in[3]
PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.905 0.070 2.975 ;
END
END w_mask_in[4]
PIN w_mask_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.115 0.070 3.185 ;
END
END w_mask_in[5]
PIN w_mask_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.325 0.070 3.395 ;
END
END w_mask_in[6]
PIN w_mask_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.535 0.070 3.605 ;
END
END w_mask_in[7]
PIN w_mask_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.745 0.070 3.815 ;
END
END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.955 0.070 4.025 ;
END
END w_mask_in[9]
PIN w_mask_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.165 0.070 4.235 ;
END
END w_mask_in[10]
PIN w_mask_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.375 0.070 4.445 ;
END
END w_mask_in[11]
PIN w_mask_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.585 0.070 4.655 ;
END
END w_mask_in[12]
PIN w_mask_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.795 0.070 4.865 ;
END
END w_mask_in[13]
PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.005 0.070 5.075 ;
END
END w_mask_in[14]
PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.215 0.070 5.285 ;
END
END w_mask_in[15]
PIN w_mask_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.425 0.070 5.495 ;
END
END w_mask_in[16]
PIN w_mask_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.635 0.070 5.705 ;
END
END w_mask_in[17]
PIN w_mask_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.845 0.070 5.915 ;
END
END w_mask_in[18]
PIN w_mask_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.055 0.070 6.125 ;
END
END w_mask_in[19]
PIN w_mask_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.265 0.070 6.335 ;
END
END w_mask_in[20]
PIN w_mask_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.475 0.070 6.545 ;
END
END w_mask_in[21]
PIN w_mask_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.685 0.070 6.755 ;
END
END w_mask_in[22]
PIN w_mask_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.895 0.070 6.965 ;
END
END w_mask_in[23]
PIN w_mask_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.105 0.070 7.175 ;
END
END w_mask_in[24]
PIN w_mask_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.315 0.070 7.385 ;
END
END w_mask_in[25]
PIN w_mask_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.525 0.070 7.595 ;
END
END w_mask_in[26]
PIN w_mask_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.735 0.070 7.805 ;
END
END w_mask_in[27]
PIN w_mask_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.945 0.070 8.015 ;
END
END w_mask_in[28]
PIN w_mask_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.155 0.070 8.225 ;
END
END w_mask_in[29]
PIN w_mask_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.365 0.070 8.435 ;
END
END w_mask_in[30]
PIN w_mask_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.575 0.070 8.645 ;
END
END w_mask_in[31]
PIN w_mask_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.785 0.070 8.855 ;
END
END w_mask_in[32]
PIN w_mask_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.995 0.070 9.065 ;
END
END w_mask_in[33]
PIN w_mask_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.205 0.070 9.275 ;
END
END w_mask_in[34]
PIN w_mask_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.415 0.070 9.485 ;
END
END w_mask_in[35]
PIN w_mask_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.625 0.070 9.695 ;
END
END w_mask_in[36]
PIN w_mask_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.835 0.070 9.905 ;
END
END w_mask_in[37]
PIN w_mask_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.045 0.070 10.115 ;
END
END w_mask_in[38]
PIN w_mask_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.255 0.070 10.325 ;
END
END w_mask_in[39]
PIN w_mask_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.465 0.070 10.535 ;
END
END w_mask_in[40]
PIN w_mask_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.675 0.070 10.745 ;
END
END w_mask_in[41]
PIN w_mask_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.885 0.070 10.955 ;
END
END w_mask_in[42]
PIN w_mask_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.095 0.070 11.165 ;
END
END w_mask_in[43]
PIN w_mask_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.305 0.070 11.375 ;
END
END w_mask_in[44]
PIN w_mask_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.515 0.070 11.585 ;
END
END w_mask_in[45]
PIN w_mask_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.725 0.070 11.795 ;
END
END w_mask_in[46]
PIN w_mask_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.935 0.070 12.005 ;
END
END w_mask_in[47]
PIN w_mask_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.145 0.070 12.215 ;
END
END w_mask_in[48]
PIN w_mask_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.355 0.070 12.425 ;
END
END w_mask_in[49]
PIN w_mask_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.565 0.070 12.635 ;
END
END w_mask_in[50]
PIN w_mask_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.775 0.070 12.845 ;
END
END w_mask_in[51]
PIN w_mask_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.985 0.070 13.055 ;
END
END w_mask_in[52]
PIN w_mask_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.195 0.070 13.265 ;
END
END w_mask_in[53]
PIN w_mask_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.405 0.070 13.475 ;
END
END w_mask_in[54]
PIN w_mask_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.615 0.070 13.685 ;
END
END w_mask_in[55]
PIN w_mask_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.825 0.070 13.895 ;
END
END w_mask_in[56]
PIN w_mask_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.035 0.070 14.105 ;
END
END w_mask_in[57]
PIN w_mask_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.245 0.070 14.315 ;
END
END w_mask_in[58]
PIN w_mask_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.455 0.070 14.525 ;
END
END w_mask_in[59]
PIN w_mask_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.665 0.070 14.735 ;
END
END w_mask_in[60]
PIN w_mask_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.875 0.070 14.945 ;
END
END w_mask_in[61]
PIN w_mask_in[62]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.085 0.070 15.155 ;
END
END w_mask_in[62]
PIN w_mask_in[63]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.295 0.070 15.365 ;
END
END w_mask_in[63]
PIN w_mask_in[64]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.505 0.070 15.575 ;
END
END w_mask_in[64]
PIN w_mask_in[65]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.715 0.070 15.785 ;
END
END w_mask_in[65]
PIN w_mask_in[66]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.925 0.070 15.995 ;
END
END w_mask_in[66]
PIN w_mask_in[67]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.135 0.070 16.205 ;
END
END w_mask_in[67]
PIN w_mask_in[68]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.345 0.070 16.415 ;
END
END w_mask_in[68]
PIN w_mask_in[69]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.555 0.070 16.625 ;
END
END w_mask_in[69]
PIN w_mask_in[70]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.765 0.070 16.835 ;
END
END w_mask_in[70]
PIN w_mask_in[71]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.975 0.070 17.045 ;
END
END w_mask_in[71]
PIN w_mask_in[72]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.185 0.070 17.255 ;
END
END w_mask_in[72]
PIN w_mask_in[73]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.395 0.070 17.465 ;
END
END w_mask_in[73]
PIN w_mask_in[74]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.605 0.070 17.675 ;
END
END w_mask_in[74]
PIN w_mask_in[75]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.815 0.070 17.885 ;
END
END w_mask_in[75]
PIN w_mask_in[76]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.025 0.070 18.095 ;
END
END w_mask_in[76]
PIN w_mask_in[77]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.235 0.070 18.305 ;
END
END w_mask_in[77]
PIN w_mask_in[78]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.445 0.070 18.515 ;
END
END w_mask_in[78]
PIN w_mask_in[79]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.655 0.070 18.725 ;
END
END w_mask_in[79]
PIN w_mask_in[80]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.865 0.070 18.935 ;
END
END w_mask_in[80]
PIN w_mask_in[81]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.075 0.070 19.145 ;
END
END w_mask_in[81]
PIN w_mask_in[82]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.285 0.070 19.355 ;
END
END w_mask_in[82]
PIN w_mask_in[83]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.495 0.070 19.565 ;
END
END w_mask_in[83]
PIN w_mask_in[84]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.705 0.070 19.775 ;
END
END w_mask_in[84]
PIN w_mask_in[85]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.915 0.070 19.985 ;
END
END w_mask_in[85]
PIN w_mask_in[86]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.125 0.070 20.195 ;
END
END w_mask_in[86]
PIN w_mask_in[87]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.335 0.070 20.405 ;
END
END w_mask_in[87]
PIN w_mask_in[88]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.545 0.070 20.615 ;
END
END w_mask_in[88]
PIN w_mask_in[89]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.755 0.070 20.825 ;
END
END w_mask_in[89]
PIN w_mask_in[90]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.965 0.070 21.035 ;
END
END w_mask_in[90]
PIN w_mask_in[91]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.175 0.070 21.245 ;
END
END w_mask_in[91]
PIN w_mask_in[92]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.385 0.070 21.455 ;
END
END w_mask_in[92]
PIN w_mask_in[93]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.595 0.070 21.665 ;
END
END w_mask_in[93]
PIN w_mask_in[94]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.805 0.070 21.875 ;
END
END w_mask_in[94]
PIN w_mask_in[95]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.015 0.070 22.085 ;
END
END w_mask_in[95]
PIN w_mask_in[96]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.225 0.070 22.295 ;
END
END w_mask_in[96]
PIN w_mask_in[97]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.435 0.070 22.505 ;
END
END w_mask_in[97]
PIN w_mask_in[98]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.645 0.070 22.715 ;
END
END w_mask_in[98]
PIN w_mask_in[99]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.855 0.070 22.925 ;
END
END w_mask_in[99]
PIN w_mask_in[100]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.065 0.070 23.135 ;
END
END w_mask_in[100]
PIN w_mask_in[101]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.275 0.070 23.345 ;
END
END w_mask_in[101]
PIN w_mask_in[102]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.485 0.070 23.555 ;
END
END w_mask_in[102]
PIN w_mask_in[103]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.695 0.070 23.765 ;
END
END w_mask_in[103]
PIN w_mask_in[104]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.905 0.070 23.975 ;
END
END w_mask_in[104]
PIN w_mask_in[105]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.115 0.070 24.185 ;
END
END w_mask_in[105]
PIN w_mask_in[106]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.325 0.070 24.395 ;
END
END w_mask_in[106]
PIN w_mask_in[107]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.535 0.070 24.605 ;
END
END w_mask_in[107]
PIN w_mask_in[108]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.745 0.070 24.815 ;
END
END w_mask_in[108]
PIN w_mask_in[109]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.955 0.070 25.025 ;
END
END w_mask_in[109]
PIN w_mask_in[110]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.165 0.070 25.235 ;
END
END w_mask_in[110]
PIN w_mask_in[111]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.375 0.070 25.445 ;
END
END w_mask_in[111]
PIN w_mask_in[112]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.585 0.070 25.655 ;
END
END w_mask_in[112]
PIN w_mask_in[113]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.795 0.070 25.865 ;
END
END w_mask_in[113]
PIN w_mask_in[114]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.005 0.070 26.075 ;
END
END w_mask_in[114]
PIN w_mask_in[115]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.215 0.070 26.285 ;
END
END w_mask_in[115]
PIN w_mask_in[116]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.425 0.070 26.495 ;
END
END w_mask_in[116]
PIN w_mask_in[117]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.635 0.070 26.705 ;
END
END w_mask_in[117]
PIN w_mask_in[118]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.845 0.070 26.915 ;
END
END w_mask_in[118]
PIN w_mask_in[119]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.055 0.070 27.125 ;
END
END w_mask_in[119]
PIN w_mask_in[120]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.265 0.070 27.335 ;
END
END w_mask_in[120]
PIN w_mask_in[121]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.475 0.070 27.545 ;
END
END w_mask_in[121]
PIN w_mask_in[122]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.685 0.070 27.755 ;
END
END w_mask_in[122]
PIN w_mask_in[123]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.895 0.070 27.965 ;
END
END w_mask_in[123]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.135 0.070 37.205 ;
END
END rd_out[0]
PIN rd_out[1]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.345 0.070 37.415 ;
END
END rd_out[1]
PIN rd_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.555 0.070 37.625 ;
END
END rd_out[2]
PIN rd_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.765 0.070 37.835 ;
END
END rd_out[3]
PIN rd_out[4]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.975 0.070 38.045 ;
END
END rd_out[4]
PIN rd_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.185 0.070 38.255 ;
END
END rd_out[5]
PIN rd_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.395 0.070 38.465 ;
END
END rd_out[6]
PIN rd_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.605 0.070 38.675 ;
END
END rd_out[7]
PIN rd_out[8]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.815 0.070 38.885 ;
END
END rd_out[8]
PIN rd_out[9]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.025 0.070 39.095 ;
END
END rd_out[9]
PIN rd_out[10]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.235 0.070 39.305 ;
END
END rd_out[10]
PIN rd_out[11]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.445 0.070 39.515 ;
END
END rd_out[11]
PIN rd_out[12]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.655 0.070 39.725 ;
END
END rd_out[12]
PIN rd_out[13]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.865 0.070 39.935 ;
END
END rd_out[13]
PIN rd_out[14]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.075 0.070 40.145 ;
END
END rd_out[14]
PIN rd_out[15]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.285 0.070 40.355 ;
END
END rd_out[15]
PIN rd_out[16]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.495 0.070 40.565 ;
END
END rd_out[16]
PIN rd_out[17]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.705 0.070 40.775 ;
END
END rd_out[17]
PIN rd_out[18]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.915 0.070 40.985 ;
END
END rd_out[18]
PIN rd_out[19]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.125 0.070 41.195 ;
END
END rd_out[19]
PIN rd_out[20]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.335 0.070 41.405 ;
END
END rd_out[20]
PIN rd_out[21]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.545 0.070 41.615 ;
END
END rd_out[21]
PIN rd_out[22]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.755 0.070 41.825 ;
END
END rd_out[22]
PIN rd_out[23]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.965 0.070 42.035 ;
END
END rd_out[23]
PIN rd_out[24]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.175 0.070 42.245 ;
END
END rd_out[24]
PIN rd_out[25]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.385 0.070 42.455 ;
END
END rd_out[25]
PIN rd_out[26]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.595 0.070 42.665 ;
END
END rd_out[26]
PIN rd_out[27]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.805 0.070 42.875 ;
END
END rd_out[27]
PIN rd_out[28]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.015 0.070 43.085 ;
END
END rd_out[28]
PIN rd_out[29]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.225 0.070 43.295 ;
END
END rd_out[29]
PIN rd_out[30]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.435 0.070 43.505 ;
END
END rd_out[30]
PIN rd_out[31]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.645 0.070 43.715 ;
END
END rd_out[31]
PIN rd_out[32]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.855 0.070 43.925 ;
END
END rd_out[32]
PIN rd_out[33]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.065 0.070 44.135 ;
END
END rd_out[33]
PIN rd_out[34]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.275 0.070 44.345 ;
END
END rd_out[34]
PIN rd_out[35]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.485 0.070 44.555 ;
END
END rd_out[35]
PIN rd_out[36]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.695 0.070 44.765 ;
END
END rd_out[36]
PIN rd_out[37]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.905 0.070 44.975 ;
END
END rd_out[37]
PIN rd_out[38]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.115 0.070 45.185 ;
END
END rd_out[38]
PIN rd_out[39]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.325 0.070 45.395 ;
END
END rd_out[39]
PIN rd_out[40]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.535 0.070 45.605 ;
END
END rd_out[40]
PIN rd_out[41]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.745 0.070 45.815 ;
END
END rd_out[41]
PIN rd_out[42]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.955 0.070 46.025 ;
END
END rd_out[42]
PIN rd_out[43]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.165 0.070 46.235 ;
END
END rd_out[43]
PIN rd_out[44]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.375 0.070 46.445 ;
END
END rd_out[44]
PIN rd_out[45]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.585 0.070 46.655 ;
END
END rd_out[45]
PIN rd_out[46]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.795 0.070 46.865 ;
END
END rd_out[46]
PIN rd_out[47]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.005 0.070 47.075 ;
END
END rd_out[47]
PIN rd_out[48]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.215 0.070 47.285 ;
END
END rd_out[48]
PIN rd_out[49]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.425 0.070 47.495 ;
END
END rd_out[49]
PIN rd_out[50]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.635 0.070 47.705 ;
END
END rd_out[50]
PIN rd_out[51]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.845 0.070 47.915 ;
END
END rd_out[51]
PIN rd_out[52]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.055 0.070 48.125 ;
END
END rd_out[52]
PIN rd_out[53]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.265 0.070 48.335 ;
END
END rd_out[53]
PIN rd_out[54]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.475 0.070 48.545 ;
END
END rd_out[54]
PIN rd_out[55]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.685 0.070 48.755 ;
END
END rd_out[55]
PIN rd_out[56]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.895 0.070 48.965 ;
END
END rd_out[56]
PIN rd_out[57]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.105 0.070 49.175 ;
END
END rd_out[57]
PIN rd_out[58]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.315 0.070 49.385 ;
END
END rd_out[58]
PIN rd_out[59]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.525 0.070 49.595 ;
END
END rd_out[59]
PIN rd_out[60]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.735 0.070 49.805 ;
END
END rd_out[60]
PIN rd_out[61]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.945 0.070 50.015 ;
END
END rd_out[61]
PIN rd_out[62]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.155 0.070 50.225 ;
END
END rd_out[62]
PIN rd_out[63]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.365 0.070 50.435 ;
END
END rd_out[63]
PIN rd_out[64]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.575 0.070 50.645 ;
END
END rd_out[64]
PIN rd_out[65]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.785 0.070 50.855 ;
END
END rd_out[65]
PIN rd_out[66]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.995 0.070 51.065 ;
END
END rd_out[66]
PIN rd_out[67]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.205 0.070 51.275 ;
END
END rd_out[67]
PIN rd_out[68]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.415 0.070 51.485 ;
END
END rd_out[68]
PIN rd_out[69]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.625 0.070 51.695 ;
END
END rd_out[69]
PIN rd_out[70]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.835 0.070 51.905 ;
END
END rd_out[70]
PIN rd_out[71]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.045 0.070 52.115 ;
END
END rd_out[71]
PIN rd_out[72]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.255 0.070 52.325 ;
END
END rd_out[72]
PIN rd_out[73]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.465 0.070 52.535 ;
END
END rd_out[73]
PIN rd_out[74]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.675 0.070 52.745 ;
END
END rd_out[74]
PIN rd_out[75]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.885 0.070 52.955 ;
END
END rd_out[75]
PIN rd_out[76]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.095 0.070 53.165 ;
END
END rd_out[76]
PIN rd_out[77]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.305 0.070 53.375 ;
END
END rd_out[77]
PIN rd_out[78]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.515 0.070 53.585 ;
END
END rd_out[78]
PIN rd_out[79]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.725 0.070 53.795 ;
END
END rd_out[79]
PIN rd_out[80]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.935 0.070 54.005 ;
END
END rd_out[80]
PIN rd_out[81]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.145 0.070 54.215 ;
END
END rd_out[81]
PIN rd_out[82]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.355 0.070 54.425 ;
END
END rd_out[82]
PIN rd_out[83]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.565 0.070 54.635 ;
END
END rd_out[83]
PIN rd_out[84]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.775 0.070 54.845 ;
END
END rd_out[84]
PIN rd_out[85]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.985 0.070 55.055 ;
END
END rd_out[85]
PIN rd_out[86]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.195 0.070 55.265 ;
END
END rd_out[86]
PIN rd_out[87]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.405 0.070 55.475 ;
END
END rd_out[87]
PIN rd_out[88]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.615 0.070 55.685 ;
END
END rd_out[88]
PIN rd_out[89]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.825 0.070 55.895 ;
END
END rd_out[89]
PIN rd_out[90]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.035 0.070 56.105 ;
END
END rd_out[90]
PIN rd_out[91]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.245 0.070 56.315 ;
END
END rd_out[91]
PIN rd_out[92]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.455 0.070 56.525 ;
END
END rd_out[92]
PIN rd_out[93]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.665 0.070 56.735 ;
END
END rd_out[93]
PIN rd_out[94]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.875 0.070 56.945 ;
END
END rd_out[94]
PIN rd_out[95]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.085 0.070 57.155 ;
END
END rd_out[95]
PIN rd_out[96]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.295 0.070 57.365 ;
END
END rd_out[96]
PIN rd_out[97]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.505 0.070 57.575 ;
END
END rd_out[97]
PIN rd_out[98]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.715 0.070 57.785 ;
END
END rd_out[98]
PIN rd_out[99]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.925 0.070 57.995 ;
END
END rd_out[99]
PIN rd_out[100]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.135 0.070 58.205 ;
END
END rd_out[100]
PIN rd_out[101]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.345 0.070 58.415 ;
END
END rd_out[101]
PIN rd_out[102]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.555 0.070 58.625 ;
END
END rd_out[102]
PIN rd_out[103]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.765 0.070 58.835 ;
END
END rd_out[103]
PIN rd_out[104]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 58.975 0.070 59.045 ;
END
END rd_out[104]
PIN rd_out[105]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.185 0.070 59.255 ;
END
END rd_out[105]
PIN rd_out[106]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.395 0.070 59.465 ;
END
END rd_out[106]
PIN rd_out[107]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.605 0.070 59.675 ;
END
END rd_out[107]
PIN rd_out[108]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 59.815 0.070 59.885 ;
END
END rd_out[108]
PIN rd_out[109]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 60.025 0.070 60.095 ;
END
END rd_out[109]
PIN rd_out[110]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 60.235 0.070 60.305 ;
END
END rd_out[110]
PIN rd_out[111]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 60.445 0.070 60.515 ;
END
END rd_out[111]
PIN rd_out[112]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 60.655 0.070 60.725 ;
END
END rd_out[112]
PIN rd_out[113]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 60.865 0.070 60.935 ;
END
END rd_out[113]
PIN rd_out[114]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.075 0.070 61.145 ;
END
END rd_out[114]
PIN rd_out[115]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.285 0.070 61.355 ;
END
END rd_out[115]
PIN rd_out[116]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.495 0.070 61.565 ;
END
END rd_out[116]
PIN rd_out[117]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.705 0.070 61.775 ;
END
END rd_out[117]
PIN rd_out[118]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.915 0.070 61.985 ;
END
END rd_out[118]
PIN rd_out[119]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.125 0.070 62.195 ;
END
END rd_out[119]
PIN rd_out[120]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.335 0.070 62.405 ;
END
END rd_out[120]
PIN rd_out[121]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.545 0.070 62.615 ;
END
END rd_out[121]
PIN rd_out[122]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.755 0.070 62.825 ;
END
END rd_out[122]
PIN rd_out[123]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.965 0.070 63.035 ;
END
END rd_out[123]
PIN wd_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.205 0.070 72.275 ;
END
END wd_in[0]
PIN wd_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.415 0.070 72.485 ;
END
END wd_in[1]
PIN wd_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.625 0.070 72.695 ;
END
END wd_in[2]
PIN wd_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.835 0.070 72.905 ;
END
END wd_in[3]
PIN wd_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.045 0.070 73.115 ;
END
END wd_in[4]
PIN wd_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.255 0.070 73.325 ;
END
END wd_in[5]
PIN wd_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.465 0.070 73.535 ;
END
END wd_in[6]
PIN wd_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.675 0.070 73.745 ;
END
END wd_in[7]
PIN wd_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.885 0.070 73.955 ;
END
END wd_in[8]
PIN wd_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.095 0.070 74.165 ;
END
END wd_in[9]
PIN wd_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.305 0.070 74.375 ;
END
END wd_in[10]
PIN wd_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.515 0.070 74.585 ;
END
END wd_in[11]
PIN wd_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.725 0.070 74.795 ;
END
END wd_in[12]
PIN wd_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.935 0.070 75.005 ;
END
END wd_in[13]
PIN wd_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.145 0.070 75.215 ;
END
END wd_in[14]
PIN wd_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.355 0.070 75.425 ;
END
END wd_in[15]
PIN wd_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.565 0.070 75.635 ;
END
END wd_in[16]
PIN wd_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.775 0.070 75.845 ;
END
END wd_in[17]
PIN wd_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.985 0.070 76.055 ;
END
END wd_in[18]
PIN wd_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.195 0.070 76.265 ;
END
END wd_in[19]
PIN wd_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.405 0.070 76.475 ;
END
END wd_in[20]
PIN wd_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.615 0.070 76.685 ;
END
END wd_in[21]
PIN wd_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.825 0.070 76.895 ;
END
END wd_in[22]
PIN wd_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.035 0.070 77.105 ;
END
END wd_in[23]
PIN wd_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.245 0.070 77.315 ;
END
END wd_in[24]
PIN wd_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.455 0.070 77.525 ;
END
END wd_in[25]
PIN wd_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.665 0.070 77.735 ;
END
END wd_in[26]
PIN wd_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.875 0.070 77.945 ;
END
END wd_in[27]
PIN wd_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.085 0.070 78.155 ;
END
END wd_in[28]
PIN wd_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.295 0.070 78.365 ;
END
END wd_in[29]
PIN wd_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.505 0.070 78.575 ;
END
END wd_in[30]
PIN wd_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.715 0.070 78.785 ;
END
END wd_in[31]
PIN wd_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.925 0.070 78.995 ;
END
END wd_in[32]
PIN wd_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.135 0.070 79.205 ;
END
END wd_in[33]
PIN wd_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.345 0.070 79.415 ;
END
END wd_in[34]
PIN wd_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.555 0.070 79.625 ;
END
END wd_in[35]
PIN wd_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.765 0.070 79.835 ;
END
END wd_in[36]
PIN wd_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.975 0.070 80.045 ;
END
END wd_in[37]
PIN wd_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.185 0.070 80.255 ;
END
END wd_in[38]
PIN wd_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.395 0.070 80.465 ;
END
END wd_in[39]
PIN wd_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.605 0.070 80.675 ;
END
END wd_in[40]
PIN wd_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.815 0.070 80.885 ;
END
END wd_in[41]
PIN wd_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.025 0.070 81.095 ;
END
END wd_in[42]
PIN wd_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.235 0.070 81.305 ;
END
END wd_in[43]
PIN wd_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.445 0.070 81.515 ;
END
END wd_in[44]
PIN wd_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.655 0.070 81.725 ;
END
END wd_in[45]
PIN wd_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.865 0.070 81.935 ;
END
END wd_in[46]
PIN wd_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.075 0.070 82.145 ;
END
END wd_in[47]
PIN wd_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.285 0.070 82.355 ;
END
END wd_in[48]
PIN wd_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.495 0.070 82.565 ;
END
END wd_in[49]
PIN wd_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.705 0.070 82.775 ;
END
END wd_in[50]
PIN wd_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.915 0.070 82.985 ;
END
END wd_in[51]
PIN wd_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.125 0.070 83.195 ;
END
END wd_in[52]
PIN wd_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.335 0.070 83.405 ;
END
END wd_in[53]
PIN wd_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.545 0.070 83.615 ;
END
END wd_in[54]
PIN wd_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.755 0.070 83.825 ;
END
END wd_in[55]
PIN wd_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.965 0.070 84.035 ;
END
END wd_in[56]
PIN wd_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.175 0.070 84.245 ;
END
END wd_in[57]
PIN wd_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.385 0.070 84.455 ;
END
END wd_in[58]
PIN wd_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.595 0.070 84.665 ;
END
END wd_in[59]
PIN wd_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.805 0.070 84.875 ;
END
END wd_in[60]
PIN wd_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.015 0.070 85.085 ;
END
END wd_in[61]
PIN wd_in[62]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.225 0.070 85.295 ;
END
END wd_in[62]
PIN wd_in[63]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.435 0.070 85.505 ;
END
END wd_in[63]
PIN wd_in[64]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.645 0.070 85.715 ;
END
END wd_in[64]
PIN wd_in[65]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.855 0.070 85.925 ;
END
END wd_in[65]
PIN wd_in[66]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.065 0.070 86.135 ;
END
END wd_in[66]
PIN wd_in[67]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.275 0.070 86.345 ;
END
END wd_in[67]
PIN wd_in[68]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.485 0.070 86.555 ;
END
END wd_in[68]
PIN wd_in[69]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.695 0.070 86.765 ;
END
END wd_in[69]
PIN wd_in[70]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.905 0.070 86.975 ;
END
END wd_in[70]
PIN wd_in[71]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.115 0.070 87.185 ;
END
END wd_in[71]
PIN wd_in[72]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.325 0.070 87.395 ;
END
END wd_in[72]
PIN wd_in[73]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.535 0.070 87.605 ;
END
END wd_in[73]
PIN wd_in[74]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.745 0.070 87.815 ;
END
END wd_in[74]
PIN wd_in[75]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 87.955 0.070 88.025 ;
END
END wd_in[75]
PIN wd_in[76]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.165 0.070 88.235 ;
END
END wd_in[76]
PIN wd_in[77]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.375 0.070 88.445 ;
END
END wd_in[77]
PIN wd_in[78]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.585 0.070 88.655 ;
END
END wd_in[78]
PIN wd_in[79]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 88.795 0.070 88.865 ;
END
END wd_in[79]
PIN wd_in[80]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.005 0.070 89.075 ;
END
END wd_in[80]
PIN wd_in[81]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.215 0.070 89.285 ;
END
END wd_in[81]
PIN wd_in[82]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.425 0.070 89.495 ;
END
END wd_in[82]
PIN wd_in[83]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.635 0.070 89.705 ;
END
END wd_in[83]
PIN wd_in[84]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 89.845 0.070 89.915 ;
END
END wd_in[84]
PIN wd_in[85]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.055 0.070 90.125 ;
END
END wd_in[85]
PIN wd_in[86]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.265 0.070 90.335 ;
END
END wd_in[86]
PIN wd_in[87]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.475 0.070 90.545 ;
END
END wd_in[87]
PIN wd_in[88]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.685 0.070 90.755 ;
END
END wd_in[88]
PIN wd_in[89]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.895 0.070 90.965 ;
END
END wd_in[89]
PIN wd_in[90]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.105 0.070 91.175 ;
END
END wd_in[90]
PIN wd_in[91]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.315 0.070 91.385 ;
END
END wd_in[91]
PIN wd_in[92]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.525 0.070 91.595 ;
END
END wd_in[92]
PIN wd_in[93]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.735 0.070 91.805 ;
END
END wd_in[93]
PIN wd_in[94]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.945 0.070 92.015 ;
END
END wd_in[94]
PIN wd_in[95]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.155 0.070 92.225 ;
END
END wd_in[95]
PIN wd_in[96]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.365 0.070 92.435 ;
END
END wd_in[96]
PIN wd_in[97]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.575 0.070 92.645 ;
END
END wd_in[97]
PIN wd_in[98]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.785 0.070 92.855 ;
END
END wd_in[98]
PIN wd_in[99]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.995 0.070 93.065 ;
END
END wd_in[99]
PIN wd_in[100]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 93.205 0.070 93.275 ;
END
END wd_in[100]
PIN wd_in[101]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 93.415 0.070 93.485 ;
END
END wd_in[101]
PIN wd_in[102]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 93.625 0.070 93.695 ;
END
END wd_in[102]
PIN wd_in[103]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 93.835 0.070 93.905 ;
END
END wd_in[103]
PIN wd_in[104]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.045 0.070 94.115 ;
END
END wd_in[104]
PIN wd_in[105]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.255 0.070 94.325 ;
END
END wd_in[105]
PIN wd_in[106]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.465 0.070 94.535 ;
END
END wd_in[106]
PIN wd_in[107]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.675 0.070 94.745 ;
END
END wd_in[107]
PIN wd_in[108]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 94.885 0.070 94.955 ;
END
END wd_in[108]
PIN wd_in[109]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 95.095 0.070 95.165 ;
END
END wd_in[109]
PIN wd_in[110]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 95.305 0.070 95.375 ;
END
END wd_in[110]
PIN wd_in[111]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 95.515 0.070 95.585 ;
END
END wd_in[111]
PIN wd_in[112]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 95.725 0.070 95.795 ;
END
END wd_in[112]
PIN wd_in[113]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 95.935 0.070 96.005 ;
END
END wd_in[113]
PIN wd_in[114]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.145 0.070 96.215 ;
END
END wd_in[114]
PIN wd_in[115]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.355 0.070 96.425 ;
END
END wd_in[115]
PIN wd_in[116]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.565 0.070 96.635 ;
END
END wd_in[116]
PIN wd_in[117]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.775 0.070 96.845 ;
END
END wd_in[117]
PIN wd_in[118]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.985 0.070 97.055 ;
END
END wd_in[118]
PIN wd_in[119]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 97.195 0.070 97.265 ;
END
END wd_in[119]
PIN wd_in[120]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 97.405 0.070 97.475 ;
END
END wd_in[120]
PIN wd_in[121]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 97.615 0.070 97.685 ;
END
END wd_in[121]
PIN wd_in[122]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 97.825 0.070 97.895 ;
END
END wd_in[122]
PIN wd_in[123]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 98.035 0.070 98.105 ;
END
END wd_in[123]
PIN addr_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 107.275 0.070 107.345 ;
END
END addr_in[0]
PIN addr_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 107.485 0.070 107.555 ;
END
END addr_in[1]
PIN addr_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 107.695 0.070 107.765 ;
END
END addr_in[2]
PIN addr_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 107.905 0.070 107.975 ;
END
END addr_in[3]
PIN addr_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 108.115 0.070 108.185 ;
END
END addr_in[4]
PIN addr_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 108.325 0.070 108.395 ;
END
END addr_in[5]
PIN we_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 117.565 0.070 117.635 ;
END
END we_in
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 117.775 0.070 117.845 ;
END
END ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 117.985 0.070 118.055 ;
END
END clk
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER metal4 ;
RECT 1.960 2.100 2.240 119.700 ;
RECT 5.320 2.100 5.600 119.700 ;
RECT 8.680 2.100 8.960 119.700 ;
RECT 12.040 2.100 12.320 119.700 ;
RECT 15.400 2.100 15.680 119.700 ;
RECT 18.760 2.100 19.040 119.700 ;
RECT 22.120 2.100 22.400 119.700 ;
RECT 25.480 2.100 25.760 119.700 ;
RECT 28.840 2.100 29.120 119.700 ;
RECT 32.200 2.100 32.480 119.700 ;
RECT 35.560 2.100 35.840 119.700 ;
RECT 38.920 2.100 39.200 119.700 ;
RECT 42.280 2.100 42.560 119.700 ;
RECT 45.640 2.100 45.920 119.700 ;
RECT 49.000 2.100 49.280 119.700 ;
RECT 52.360 2.100 52.640 119.700 ;
RECT 55.720 2.100 56.000 119.700 ;
RECT 59.080 2.100 59.360 119.700 ;
RECT 62.440 2.100 62.720 119.700 ;
RECT 65.800 2.100 66.080 119.700 ;
RECT 69.160 2.100 69.440 119.700 ;
RECT 72.520 2.100 72.800 119.700 ;
RECT 75.880 2.100 76.160 119.700 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER metal4 ;
RECT 3.640 2.100 3.920 119.700 ;
RECT 7.000 2.100 7.280 119.700 ;
RECT 10.360 2.100 10.640 119.700 ;
RECT 13.720 2.100 14.000 119.700 ;
RECT 17.080 2.100 17.360 119.700 ;
RECT 20.440 2.100 20.720 119.700 ;
RECT 23.800 2.100 24.080 119.700 ;
RECT 27.160 2.100 27.440 119.700 ;
RECT 30.520 2.100 30.800 119.700 ;
RECT 33.880 2.100 34.160 119.700 ;
RECT 37.240 2.100 37.520 119.700 ;
RECT 40.600 2.100 40.880 119.700 ;
RECT 43.960 2.100 44.240 119.700 ;
RECT 47.320 2.100 47.600 119.700 ;
RECT 50.680 2.100 50.960 119.700 ;
RECT 54.040 2.100 54.320 119.700 ;
RECT 57.400 2.100 57.680 119.700 ;
RECT 60.760 2.100 61.040 119.700 ;
RECT 64.120 2.100 64.400 119.700 ;
RECT 67.480 2.100 67.760 119.700 ;
RECT 70.840 2.100 71.120 119.700 ;
RECT 74.200 2.100 74.480 119.700 ;
RECT 77.560 2.100 77.840 119.700 ;
END
END VDD
OBS
LAYER metal1 ;
RECT 0 0 80.560 121.800 ;
LAYER metal2 ;
RECT 0 0 80.560 121.800 ;
LAYER metal3 ;
RECT 0.070 0 80.560 121.800 ;
RECT 0 0.000 0.070 2.065 ;
RECT 0 2.135 0.070 2.275 ;
RECT 0 2.345 0.070 2.485 ;
RECT 0 2.555 0.070 2.695 ;
RECT 0 2.765 0.070 2.905 ;
RECT 0 2.975 0.070 3.115 ;
RECT 0 3.185 0.070 3.325 ;
RECT 0 3.395 0.070 3.535 ;
RECT 0 3.605 0.070 3.745 ;
RECT 0 3.815 0.070 3.955 ;
RECT 0 4.025 0.070 4.165 ;
RECT 0 4.235 0.070 4.375 ;
RECT 0 4.445 0.070 4.585 ;
RECT 0 4.655 0.070 4.795 ;
RECT 0 4.865 0.070 5.005 ;
RECT 0 5.075 0.070 5.215 ;
RECT 0 5.285 0.070 5.425 ;
RECT 0 5.495 0.070 5.635 ;
RECT 0 5.705 0.070 5.845 ;
RECT 0 5.915 0.070 6.055 ;
RECT 0 6.125 0.070 6.265 ;
RECT 0 6.335 0.070 6.475 ;
RECT 0 6.545 0.070 6.685 ;
RECT 0 6.755 0.070 6.895 ;
RECT 0 6.965 0.070 7.105 ;
RECT 0 7.175 0.070 7.315 ;
RECT 0 7.385 0.070 7.525 ;
RECT 0 7.595 0.070 7.735 ;
RECT 0 7.805 0.070 7.945 ;
RECT 0 8.015 0.070 8.155 ;
RECT 0 8.225 0.070 8.365 ;
RECT 0 8.435 0.070 8.575 ;
RECT 0 8.645 0.070 8.785 ;
RECT 0 8.855 0.070 8.995 ;
RECT 0 9.065 0.070 9.205 ;
RECT 0 9.275 0.070 9.415 ;
RECT 0 9.485 0.070 9.625 ;
RECT 0 9.695 0.070 9.835 ;
RECT 0 9.905 0.070 10.045 ;
RECT 0 10.115 0.070 10.255 ;
RECT 0 10.325 0.070 10.465 ;
RECT 0 10.535 0.070 10.675 ;
RECT 0 10.745 0.070 10.885 ;
RECT 0 10.955 0.070 11.095 ;
RECT 0 11.165 0.070 11.305 ;
RECT 0 11.375 0.070 11.515 ;
RECT 0 11.585 0.070 11.725 ;
RECT 0 11.795 0.070 11.935 ;
RECT 0 12.005 0.070 12.145 ;
RECT 0 12.215 0.070 12.355 ;
RECT 0 12.425 0.070 12.565 ;
RECT 0 12.635 0.070 12.775 ;
RECT 0 12.845 0.070 12.985 ;
RECT 0 13.055 0.070 13.195 ;
RECT 0 13.265 0.070 13.405 ;
RECT 0 13.475 0.070 13.615 ;
RECT 0 13.685 0.070 13.825 ;
RECT 0 13.895 0.070 14.035 ;
RECT 0 14.105 0.070 14.245 ;
RECT 0 14.315 0.070 14.455 ;
RECT 0 14.525 0.070 14.665 ;
RECT 0 14.735 0.070 14.875 ;
RECT 0 14.945 0.070 15.085 ;
RECT 0 15.155 0.070 15.295 ;
RECT 0 15.365 0.070 15.505 ;
RECT 0 15.575 0.070 15.715 ;
RECT 0 15.785 0.070 15.925 ;
RECT 0 15.995 0.070 16.135 ;
RECT 0 16.205 0.070 16.345 ;
RECT 0 16.415 0.070 16.555 ;
RECT 0 16.625 0.070 16.765 ;
RECT 0 16.835 0.070 16.975 ;
RECT 0 17.045 0.070 17.185 ;
RECT 0 17.255 0.070 17.395 ;
RECT 0 17.465 0.070 17.605 ;
RECT 0 17.675 0.070 17.815 ;
RECT 0 17.885 0.070 18.025 ;
RECT 0 18.095 0.070 18.235 ;
RECT 0 18.305 0.070 18.445 ;
RECT 0 18.515 0.070 18.655 ;
RECT 0 18.725 0.070 18.865 ;
RECT 0 18.935 0.070 19.075 ;
RECT 0 19.145 0.070 19.285 ;
RECT 0 19.355 0.070 19.495 ;
RECT 0 19.565 0.070 19.705 ;
RECT 0 19.775 0.070 19.915 ;
RECT 0 19.985 0.070 20.125 ;
RECT 0 20.195 0.070 20.335 ;
RECT 0 20.405 0.070 20.545 ;
RECT 0 20.615 0.070 20.755 ;
RECT 0 20.825 0.070 20.965 ;
RECT 0 21.035 0.070 21.175 ;
RECT 0 21.245 0.070 21.385 ;
RECT 0 21.455 0.070 21.595 ;
RECT 0 21.665 0.070 21.805 ;
RECT 0 21.875 0.070 22.015 ;
RECT 0 22.085 0.070 22.225 ;
RECT 0 22.295 0.070 22.435 ;
RECT 0 22.505 0.070 22.645 ;
RECT 0 22.715 0.070 22.855 ;
RECT 0 22.925 0.070 23.065 ;
RECT 0 23.135 0.070 23.275 ;
RECT 0 23.345 0.070 23.485 ;
RECT 0 23.555 0.070 23.695 ;
RECT 0 23.765 0.070 23.905 ;
RECT 0 23.975 0.070 24.115 ;
RECT 0 24.185 0.070 24.325 ;
RECT 0 24.395 0.070 24.535 ;
RECT 0 24.605 0.070 24.745 ;
RECT 0 24.815 0.070 24.955 ;
RECT 0 25.025 0.070 25.165 ;
RECT 0 25.235 0.070 25.375 ;
RECT 0 25.445 0.070 25.585 ;
RECT 0 25.655 0.070 25.795 ;
RECT 0 25.865 0.070 26.005 ;
RECT 0 26.075 0.070 26.215 ;
RECT 0 26.285 0.070 26.425 ;
RECT 0 26.495 0.070 26.635 ;
RECT 0 26.705 0.070 26.845 ;
RECT 0 26.915 0.070 27.055 ;
RECT 0 27.125 0.070 27.265 ;
RECT 0 27.335 0.070 27.475 ;
RECT 0 27.545 0.070 27.685 ;
RECT 0 27.755 0.070 27.895 ;
RECT 0 27.965 0.070 37.135 ;
RECT 0 37.205 0.070 37.345 ;
RECT 0 37.415 0.070 37.555 ;
RECT 0 37.625 0.070 37.765 ;
RECT 0 37.835 0.070 37.975 ;
RECT 0 38.045 0.070 38.185 ;
RECT 0 38.255 0.070 38.395 ;
RECT 0 38.465 0.070 38.605 ;
RECT 0 38.675 0.070 38.815 ;
RECT 0 38.885 0.070 39.025 ;
RECT 0 39.095 0.070 39.235 ;
RECT 0 39.305 0.070 39.445 ;
RECT 0 39.515 0.070 39.655 ;
RECT 0 39.725 0.070 39.865 ;
RECT 0 39.935 0.070 40.075 ;
RECT 0 40.145 0.070 40.285 ;
RECT 0 40.355 0.070 40.495 ;
RECT 0 40.565 0.070 40.705 ;
RECT 0 40.775 0.070 40.915 ;
RECT 0 40.985 0.070 41.125 ;
RECT 0 41.195 0.070 41.335 ;
RECT 0 41.405 0.070 41.545 ;
RECT 0 41.615 0.070 41.755 ;
RECT 0 41.825 0.070 41.965 ;
RECT 0 42.035 0.070 42.175 ;
RECT 0 42.245 0.070 42.385 ;
RECT 0 42.455 0.070 42.595 ;
RECT 0 42.665 0.070 42.805 ;
RECT 0 42.875 0.070 43.015 ;
RECT 0 43.085 0.070 43.225 ;
RECT 0 43.295 0.070 43.435 ;
RECT 0 43.505 0.070 43.645 ;
RECT 0 43.715 0.070 43.855 ;
RECT 0 43.925 0.070 44.065 ;
RECT 0 44.135 0.070 44.275 ;
RECT 0 44.345 0.070 44.485 ;
RECT 0 44.555 0.070 44.695 ;
RECT 0 44.765 0.070 44.905 ;
RECT 0 44.975 0.070 45.115 ;
RECT 0 45.185 0.070 45.325 ;
RECT 0 45.395 0.070 45.535 ;
RECT 0 45.605 0.070 45.745 ;
RECT 0 45.815 0.070 45.955 ;
RECT 0 46.025 0.070 46.165 ;
RECT 0 46.235 0.070 46.375 ;
RECT 0 46.445 0.070 46.585 ;
RECT 0 46.655 0.070 46.795 ;
RECT 0 46.865 0.070 47.005 ;
RECT 0 47.075 0.070 47.215 ;
RECT 0 47.285 0.070 47.425 ;
RECT 0 47.495 0.070 47.635 ;
RECT 0 47.705 0.070 47.845 ;
RECT 0 47.915 0.070 48.055 ;
RECT 0 48.125 0.070 48.265 ;
RECT 0 48.335 0.070 48.475 ;
RECT 0 48.545 0.070 48.685 ;
RECT 0 48.755 0.070 48.895 ;
RECT 0 48.965 0.070 49.105 ;
RECT 0 49.175 0.070 49.315 ;
RECT 0 49.385 0.070 49.525 ;
RECT 0 49.595 0.070 49.735 ;
RECT 0 49.805 0.070 49.945 ;
RECT 0 50.015 0.070 50.155 ;
RECT 0 50.225 0.070 50.365 ;
RECT 0 50.435 0.070 50.575 ;
RECT 0 50.645 0.070 50.785 ;
RECT 0 50.855 0.070 50.995 ;
RECT 0 51.065 0.070 51.205 ;
RECT 0 51.275 0.070 51.415 ;
RECT 0 51.485 0.070 51.625 ;
RECT 0 51.695 0.070 51.835 ;
RECT 0 51.905 0.070 52.045 ;
RECT 0 52.115 0.070 52.255 ;
RECT 0 52.325 0.070 52.465 ;
RECT 0 52.535 0.070 52.675 ;
RECT 0 52.745 0.070 52.885 ;
RECT 0 52.955 0.070 53.095 ;
RECT 0 53.165 0.070 53.305 ;
RECT 0 53.375 0.070 53.515 ;
RECT 0 53.585 0.070 53.725 ;
RECT 0 53.795 0.070 53.935 ;
RECT 0 54.005 0.070 54.145 ;
RECT 0 54.215 0.070 54.355 ;
RECT 0 54.425 0.070 54.565 ;
RECT 0 54.635 0.070 54.775 ;
RECT 0 54.845 0.070 54.985 ;
RECT 0 55.055 0.070 55.195 ;
RECT 0 55.265 0.070 55.405 ;
RECT 0 55.475 0.070 55.615 ;
RECT 0 55.685 0.070 55.825 ;
RECT 0 55.895 0.070 56.035 ;
RECT 0 56.105 0.070 56.245 ;
RECT 0 56.315 0.070 56.455 ;
RECT 0 56.525 0.070 56.665 ;
RECT 0 56.735 0.070 56.875 ;
RECT 0 56.945 0.070 57.085 ;
RECT 0 57.155 0.070 57.295 ;
RECT 0 57.365 0.070 57.505 ;
RECT 0 57.575 0.070 57.715 ;
RECT 0 57.785 0.070 57.925 ;
RECT 0 57.995 0.070 58.135 ;
RECT 0 58.205 0.070 58.345 ;
RECT 0 58.415 0.070 58.555 ;
RECT 0 58.625 0.070 58.765 ;
RECT 0 58.835 0.070 58.975 ;
RECT 0 59.045 0.070 59.185 ;
RECT 0 59.255 0.070 59.395 ;
RECT 0 59.465 0.070 59.605 ;
RECT 0 59.675 0.070 59.815 ;
RECT 0 59.885 0.070 60.025 ;
RECT 0 60.095 0.070 60.235 ;
RECT 0 60.305 0.070 60.445 ;
RECT 0 60.515 0.070 60.655 ;
RECT 0 60.725 0.070 60.865 ;
RECT 0 60.935 0.070 61.075 ;
RECT 0 61.145 0.070 61.285 ;
RECT 0 61.355 0.070 61.495 ;
RECT 0 61.565 0.070 61.705 ;
RECT 0 61.775 0.070 61.915 ;
RECT 0 61.985 0.070 62.125 ;
RECT 0 62.195 0.070 62.335 ;
RECT 0 62.405 0.070 62.545 ;
RECT 0 62.615 0.070 62.755 ;
RECT 0 62.825 0.070 62.965 ;
RECT 0 63.035 0.070 72.205 ;
RECT 0 72.275 0.070 72.415 ;
RECT 0 72.485 0.070 72.625 ;
RECT 0 72.695 0.070 72.835 ;
RECT 0 72.905 0.070 73.045 ;
RECT 0 73.115 0.070 73.255 ;
RECT 0 73.325 0.070 73.465 ;
RECT 0 73.535 0.070 73.675 ;
RECT 0 73.745 0.070 73.885 ;
RECT 0 73.955 0.070 74.095 ;
RECT 0 74.165 0.070 74.305 ;
RECT 0 74.375 0.070 74.515 ;
RECT 0 74.585 0.070 74.725 ;
RECT 0 74.795 0.070 74.935 ;
RECT 0 75.005 0.070 75.145 ;
RECT 0 75.215 0.070 75.355 ;
RECT 0 75.425 0.070 75.565 ;
RECT 0 75.635 0.070 75.775 ;
RECT 0 75.845 0.070 75.985 ;
RECT 0 76.055 0.070 76.195 ;
RECT 0 76.265 0.070 76.405 ;
RECT 0 76.475 0.070 76.615 ;
RECT 0 76.685 0.070 76.825 ;
RECT 0 76.895 0.070 77.035 ;
RECT 0 77.105 0.070 77.245 ;
RECT 0 77.315 0.070 77.455 ;
RECT 0 77.525 0.070 77.665 ;
RECT 0 77.735 0.070 77.875 ;
RECT 0 77.945 0.070 78.085 ;
RECT 0 78.155 0.070 78.295 ;
RECT 0 78.365 0.070 78.505 ;
RECT 0 78.575 0.070 78.715 ;
RECT 0 78.785 0.070 78.925 ;
RECT 0 78.995 0.070 79.135 ;
RECT 0 79.205 0.070 79.345 ;
RECT 0 79.415 0.070 79.555 ;
RECT 0 79.625 0.070 79.765 ;
RECT 0 79.835 0.070 79.975 ;
RECT 0 80.045 0.070 80.185 ;
RECT 0 80.255 0.070 80.395 ;
RECT 0 80.465 0.070 80.605 ;
RECT 0 80.675 0.070 80.815 ;
RECT 0 80.885 0.070 81.025 ;
RECT 0 81.095 0.070 81.235 ;
RECT 0 81.305 0.070 81.445 ;
RECT 0 81.515 0.070 81.655 ;
RECT 0 81.725 0.070 81.865 ;
RECT 0 81.935 0.070 82.075 ;
RECT 0 82.145 0.070 82.285 ;
RECT 0 82.355 0.070 82.495 ;
RECT 0 82.565 0.070 82.705 ;
RECT 0 82.775 0.070 82.915 ;
RECT 0 82.985 0.070 83.125 ;
RECT 0 83.195 0.070 83.335 ;
RECT 0 83.405 0.070 83.545 ;
RECT 0 83.615 0.070 83.755 ;
RECT 0 83.825 0.070 83.965 ;
RECT 0 84.035 0.070 84.175 ;
RECT 0 84.245 0.070 84.385 ;
RECT 0 84.455 0.070 84.595 ;
RECT 0 84.665 0.070 84.805 ;
RECT 0 84.875 0.070 85.015 ;
RECT 0 85.085 0.070 85.225 ;
RECT 0 85.295 0.070 85.435 ;
RECT 0 85.505 0.070 85.645 ;
RECT 0 85.715 0.070 85.855 ;
RECT 0 85.925 0.070 86.065 ;
RECT 0 86.135 0.070 86.275 ;
RECT 0 86.345 0.070 86.485 ;
RECT 0 86.555 0.070 86.695 ;
RECT 0 86.765 0.070 86.905 ;
RECT 0 86.975 0.070 87.115 ;
RECT 0 87.185 0.070 87.325 ;
RECT 0 87.395 0.070 87.535 ;
RECT 0 87.605 0.070 87.745 ;
RECT 0 87.815 0.070 87.955 ;
RECT 0 88.025 0.070 88.165 ;
RECT 0 88.235 0.070 88.375 ;
RECT 0 88.445 0.070 88.585 ;
RECT 0 88.655 0.070 88.795 ;
RECT 0 88.865 0.070 89.005 ;
RECT 0 89.075 0.070 89.215 ;
RECT 0 89.285 0.070 89.425 ;
RECT 0 89.495 0.070 89.635 ;
RECT 0 89.705 0.070 89.845 ;
RECT 0 89.915 0.070 90.055 ;
RECT 0 90.125 0.070 90.265 ;
RECT 0 90.335 0.070 90.475 ;
RECT 0 90.545 0.070 90.685 ;
RECT 0 90.755 0.070 90.895 ;
RECT 0 90.965 0.070 91.105 ;
RECT 0 91.175 0.070 91.315 ;
RECT 0 91.385 0.070 91.525 ;
RECT 0 91.595 0.070 91.735 ;
RECT 0 91.805 0.070 91.945 ;
RECT 0 92.015 0.070 92.155 ;
RECT 0 92.225 0.070 92.365 ;
RECT 0 92.435 0.070 92.575 ;
RECT 0 92.645 0.070 92.785 ;
RECT 0 92.855 0.070 92.995 ;
RECT 0 93.065 0.070 93.205 ;
RECT 0 93.275 0.070 93.415 ;
RECT 0 93.485 0.070 93.625 ;
RECT 0 93.695 0.070 93.835 ;
RECT 0 93.905 0.070 94.045 ;
RECT 0 94.115 0.070 94.255 ;
RECT 0 94.325 0.070 94.465 ;
RECT 0 94.535 0.070 94.675 ;
RECT 0 94.745 0.070 94.885 ;
RECT 0 94.955 0.070 95.095 ;
RECT 0 95.165 0.070 95.305 ;
RECT 0 95.375 0.070 95.515 ;
RECT 0 95.585 0.070 95.725 ;
RECT 0 95.795 0.070 95.935 ;
RECT 0 96.005 0.070 96.145 ;
RECT 0 96.215 0.070 96.355 ;
RECT 0 96.425 0.070 96.565 ;
RECT 0 96.635 0.070 96.775 ;
RECT 0 96.845 0.070 96.985 ;
RECT 0 97.055 0.070 97.195 ;
RECT 0 97.265 0.070 97.405 ;
RECT 0 97.475 0.070 97.615 ;
RECT 0 97.685 0.070 97.825 ;
RECT 0 97.895 0.070 98.035 ;
RECT 0 98.105 0.070 107.275 ;
RECT 0 107.345 0.070 107.485 ;
RECT 0 107.555 0.070 107.695 ;
RECT 0 107.765 0.070 107.905 ;
RECT 0 107.975 0.070 108.115 ;
RECT 0 108.185 0.070 108.325 ;
RECT 0 108.395 0.070 117.565 ;
RECT 0 117.635 0.070 117.775 ;
RECT 0 117.845 0.070 117.985 ;
RECT 0 118.055 0.070 121.800 ;
LAYER metal4 ;
RECT 0 0 80.560 2.100 ;
RECT 0 119.700 80.560 121.800 ;
RECT 0.000 2.100 1.960 119.700 ;
RECT 2.240 2.100 3.640 119.700 ;
RECT 3.920 2.100 5.320 119.700 ;
RECT 5.600 2.100 7.000 119.700 ;
RECT 7.280 2.100 8.680 119.700 ;
RECT 8.960 2.100 10.360 119.700 ;
RECT 10.640 2.100 12.040 119.700 ;
RECT 12.320 2.100 13.720 119.700 ;
RECT 14.000 2.100 15.400 119.700 ;
RECT 15.680 2.100 17.080 119.700 ;
RECT 17.360 2.100 18.760 119.700 ;
RECT 19.040 2.100 20.440 119.700 ;
RECT 20.720 2.100 22.120 119.700 ;
RECT 22.400 2.100 23.800 119.700 ;
RECT 24.080 2.100 25.480 119.700 ;
RECT 25.760 2.100 27.160 119.700 ;
RECT 27.440 2.100 28.840 119.700 ;
RECT 29.120 2.100 30.520 119.700 ;
RECT 30.800 2.100 32.200 119.700 ;
RECT 32.480 2.100 33.880 119.700 ;
RECT 34.160 2.100 35.560 119.700 ;
RECT 35.840 2.100 37.240 119.700 ;
RECT 37.520 2.100 38.920 119.700 ;
RECT 39.200 2.100 40.600 119.700 ;
RECT 40.880 2.100 42.280 119.700 ;
RECT 42.560 2.100 43.960 119.700 ;
RECT 44.240 2.100 45.640 119.700 ;
RECT 45.920 2.100 47.320 119.700 ;
RECT 47.600 2.100 49.000 119.700 ;
RECT 49.280 2.100 50.680 119.700 ;
RECT 50.960 2.100 52.360 119.700 ;
RECT 52.640 2.100 54.040 119.700 ;
RECT 54.320 2.100 55.720 119.700 ;
RECT 56.000 2.100 57.400 119.700 ;
RECT 57.680 2.100 59.080 119.700 ;
RECT 59.360 2.100 60.760 119.700 ;
RECT 61.040 2.100 62.440 119.700 ;
RECT 62.720 2.100 64.120 119.700 ;
RECT 64.400 2.100 65.800 119.700 ;
RECT 66.080 2.100 67.480 119.700 ;
RECT 67.760 2.100 69.160 119.700 ;
RECT 69.440 2.100 70.840 119.700 ;
RECT 71.120 2.100 72.520 119.700 ;
RECT 72.800 2.100 74.200 119.700 ;
RECT 74.480 2.100 75.880 119.700 ;
RECT 76.160 2.100 77.560 119.700 ;
RECT 77.840 2.100 80.560 119.700 ;
LAYER OVERLAP ;
RECT 0 0 80.560 121.800 ;
END
END fakeram45_64x124
END LIBRARY
Enablements/NanGate45/lef/fakeram45_64x62.lef 0 → 100644
VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_64x62
FOREIGN fakeram45_64x62 0 0 ;
SYMMETRY X Y R90 ;
SIZE 56.050 BY 102.200 ;
CLASS BLOCK ;
PIN w_mask_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.065 0.070 2.135 ;
END
END w_mask_in[0]
PIN w_mask_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.485 0.070 2.555 ;
END
END w_mask_in[1]
PIN w_mask_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 2.905 0.070 2.975 ;
END
END w_mask_in[2]
PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.325 0.070 3.395 ;
END
END w_mask_in[3]
PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 3.745 0.070 3.815 ;
END
END w_mask_in[4]
PIN w_mask_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.165 0.070 4.235 ;
END
END w_mask_in[5]
PIN w_mask_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 4.585 0.070 4.655 ;
END
END w_mask_in[6]
PIN w_mask_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.005 0.070 5.075 ;
END
END w_mask_in[7]
PIN w_mask_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.425 0.070 5.495 ;
END
END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 5.845 0.070 5.915 ;
END
END w_mask_in[9]
PIN w_mask_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.265 0.070 6.335 ;
END
END w_mask_in[10]
PIN w_mask_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 6.685 0.070 6.755 ;
END
END w_mask_in[11]
PIN w_mask_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.105 0.070 7.175 ;
END
END w_mask_in[12]
PIN w_mask_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.525 0.070 7.595 ;
END
END w_mask_in[13]
PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 7.945 0.070 8.015 ;
END
END w_mask_in[14]
PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.365 0.070 8.435 ;
END
END w_mask_in[15]
PIN w_mask_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 8.785 0.070 8.855 ;
END
END w_mask_in[16]
PIN w_mask_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.205 0.070 9.275 ;
END
END w_mask_in[17]
PIN w_mask_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 9.625 0.070 9.695 ;
END
END w_mask_in[18]
PIN w_mask_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.045 0.070 10.115 ;
END
END w_mask_in[19]
PIN w_mask_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.465 0.070 10.535 ;
END
END w_mask_in[20]
PIN w_mask_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 10.885 0.070 10.955 ;
END
END w_mask_in[21]
PIN w_mask_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.305 0.070 11.375 ;
END
END w_mask_in[22]
PIN w_mask_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 11.725 0.070 11.795 ;
END
END w_mask_in[23]
PIN w_mask_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.145 0.070 12.215 ;
END
END w_mask_in[24]
PIN w_mask_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.565 0.070 12.635 ;
END
END w_mask_in[25]
PIN w_mask_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 12.985 0.070 13.055 ;
END
END w_mask_in[26]
PIN w_mask_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.405 0.070 13.475 ;
END
END w_mask_in[27]
PIN w_mask_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 13.825 0.070 13.895 ;
END
END w_mask_in[28]
PIN w_mask_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.245 0.070 14.315 ;
END
END w_mask_in[29]
PIN w_mask_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 14.665 0.070 14.735 ;
END
END w_mask_in[30]
PIN w_mask_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.085 0.070 15.155 ;
END
END w_mask_in[31]
PIN w_mask_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.505 0.070 15.575 ;
END
END w_mask_in[32]
PIN w_mask_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 15.925 0.070 15.995 ;
END
END w_mask_in[33]
PIN w_mask_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.345 0.070 16.415 ;
END
END w_mask_in[34]
PIN w_mask_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 16.765 0.070 16.835 ;
END
END w_mask_in[35]
PIN w_mask_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.185 0.070 17.255 ;
END
END w_mask_in[36]
PIN w_mask_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 17.605 0.070 17.675 ;
END
END w_mask_in[37]
PIN w_mask_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.025 0.070 18.095 ;
END
END w_mask_in[38]
PIN w_mask_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.445 0.070 18.515 ;
END
END w_mask_in[39]
PIN w_mask_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 18.865 0.070 18.935 ;
END
END w_mask_in[40]
PIN w_mask_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.285 0.070 19.355 ;
END
END w_mask_in[41]
PIN w_mask_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 19.705 0.070 19.775 ;
END
END w_mask_in[42]
PIN w_mask_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.125 0.070 20.195 ;
END
END w_mask_in[43]
PIN w_mask_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.545 0.070 20.615 ;
END
END w_mask_in[44]
PIN w_mask_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 20.965 0.070 21.035 ;
END
END w_mask_in[45]
PIN w_mask_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.385 0.070 21.455 ;
END
END w_mask_in[46]
PIN w_mask_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 21.805 0.070 21.875 ;
END
END w_mask_in[47]
PIN w_mask_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.225 0.070 22.295 ;
END
END w_mask_in[48]
PIN w_mask_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 22.645 0.070 22.715 ;
END
END w_mask_in[49]
PIN w_mask_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.065 0.070 23.135 ;
END
END w_mask_in[50]
PIN w_mask_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.485 0.070 23.555 ;
END
END w_mask_in[51]
PIN w_mask_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 23.905 0.070 23.975 ;
END
END w_mask_in[52]
PIN w_mask_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.325 0.070 24.395 ;
END
END w_mask_in[53]
PIN w_mask_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 24.745 0.070 24.815 ;
END
END w_mask_in[54]
PIN w_mask_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.165 0.070 25.235 ;
END
END w_mask_in[55]
PIN w_mask_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 25.585 0.070 25.655 ;
END
END w_mask_in[56]
PIN w_mask_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.005 0.070 26.075 ;
END
END w_mask_in[57]
PIN w_mask_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.425 0.070 26.495 ;
END
END w_mask_in[58]
PIN w_mask_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 26.845 0.070 26.915 ;
END
END w_mask_in[59]
PIN w_mask_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.265 0.070 27.335 ;
END
END w_mask_in[60]
PIN w_mask_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 27.685 0.070 27.755 ;
END
END w_mask_in[61]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 31.675 0.070 31.745 ;
END
END rd_out[0]
PIN rd_out[1]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 32.095 0.070 32.165 ;
END
END rd_out[1]
PIN rd_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 32.515 0.070 32.585 ;
END
END rd_out[2]
PIN rd_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 32.935 0.070 33.005 ;
END
END rd_out[3]
PIN rd_out[4]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 33.355 0.070 33.425 ;
END
END rd_out[4]
PIN rd_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 33.775 0.070 33.845 ;
END
END rd_out[5]
PIN rd_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 34.195 0.070 34.265 ;
END
END rd_out[6]
PIN rd_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 34.615 0.070 34.685 ;
END
END rd_out[7]
PIN rd_out[8]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 35.035 0.070 35.105 ;
END
END rd_out[8]
PIN rd_out[9]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 35.455 0.070 35.525 ;
END
END rd_out[9]
PIN rd_out[10]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 35.875 0.070 35.945 ;
END
END rd_out[10]
PIN rd_out[11]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.295 0.070 36.365 ;
END
END rd_out[11]
PIN rd_out[12]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 36.715 0.070 36.785 ;
END
END rd_out[12]
PIN rd_out[13]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.135 0.070 37.205 ;
END
END rd_out[13]
PIN rd_out[14]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.555 0.070 37.625 ;
END
END rd_out[14]
PIN rd_out[15]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 37.975 0.070 38.045 ;
END
END rd_out[15]
PIN rd_out[16]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.395 0.070 38.465 ;
END
END rd_out[16]
PIN rd_out[17]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 38.815 0.070 38.885 ;
END
END rd_out[17]
PIN rd_out[18]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.235 0.070 39.305 ;
END
END rd_out[18]
PIN rd_out[19]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 39.655 0.070 39.725 ;
END
END rd_out[19]
PIN rd_out[20]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.075 0.070 40.145 ;
END
END rd_out[20]
PIN rd_out[21]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.495 0.070 40.565 ;
END
END rd_out[21]
PIN rd_out[22]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 40.915 0.070 40.985 ;
END
END rd_out[22]
PIN rd_out[23]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.335 0.070 41.405 ;
END
END rd_out[23]
PIN rd_out[24]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 41.755 0.070 41.825 ;
END
END rd_out[24]
PIN rd_out[25]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.175 0.070 42.245 ;
END
END rd_out[25]
PIN rd_out[26]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 42.595 0.070 42.665 ;
END
END rd_out[26]
PIN rd_out[27]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.015 0.070 43.085 ;
END
END rd_out[27]
PIN rd_out[28]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.435 0.070 43.505 ;
END
END rd_out[28]
PIN rd_out[29]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 43.855 0.070 43.925 ;
END
END rd_out[29]
PIN rd_out[30]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.275 0.070 44.345 ;
END
END rd_out[30]
PIN rd_out[31]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 44.695 0.070 44.765 ;
END
END rd_out[31]
PIN rd_out[32]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.115 0.070 45.185 ;
END
END rd_out[32]
PIN rd_out[33]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.535 0.070 45.605 ;
END
END rd_out[33]
PIN rd_out[34]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 45.955 0.070 46.025 ;
END
END rd_out[34]
PIN rd_out[35]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.375 0.070 46.445 ;
END
END rd_out[35]
PIN rd_out[36]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 46.795 0.070 46.865 ;
END
END rd_out[36]
PIN rd_out[37]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.215 0.070 47.285 ;
END
END rd_out[37]
PIN rd_out[38]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 47.635 0.070 47.705 ;
END
END rd_out[38]
PIN rd_out[39]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.055 0.070 48.125 ;
END
END rd_out[39]
PIN rd_out[40]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.475 0.070 48.545 ;
END
END rd_out[40]
PIN rd_out[41]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 48.895 0.070 48.965 ;
END
END rd_out[41]
PIN rd_out[42]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.315 0.070 49.385 ;
END
END rd_out[42]
PIN rd_out[43]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 49.735 0.070 49.805 ;
END
END rd_out[43]
PIN rd_out[44]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.155 0.070 50.225 ;
END
END rd_out[44]
PIN rd_out[45]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.575 0.070 50.645 ;
END
END rd_out[45]
PIN rd_out[46]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 50.995 0.070 51.065 ;
END
END rd_out[46]
PIN rd_out[47]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.415 0.070 51.485 ;
END
END rd_out[47]
PIN rd_out[48]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 51.835 0.070 51.905 ;
END
END rd_out[48]
PIN rd_out[49]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.255 0.070 52.325 ;
END
END rd_out[49]
PIN rd_out[50]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 52.675 0.070 52.745 ;
END
END rd_out[50]
PIN rd_out[51]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.095 0.070 53.165 ;
END
END rd_out[51]
PIN rd_out[52]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.515 0.070 53.585 ;
END
END rd_out[52]
PIN rd_out[53]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 53.935 0.070 54.005 ;
END
END rd_out[53]
PIN rd_out[54]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.355 0.070 54.425 ;
END
END rd_out[54]
PIN rd_out[55]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 54.775 0.070 54.845 ;
END
END rd_out[55]
PIN rd_out[56]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.195 0.070 55.265 ;
END
END rd_out[56]
PIN rd_out[57]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 55.615 0.070 55.685 ;
END
END rd_out[57]
PIN rd_out[58]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.035 0.070 56.105 ;
END
END rd_out[58]
PIN rd_out[59]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.455 0.070 56.525 ;
END
END rd_out[59]
PIN rd_out[60]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 56.875 0.070 56.945 ;
END
END rd_out[60]
PIN rd_out[61]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 57.295 0.070 57.365 ;
END
END rd_out[61]
PIN wd_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.285 0.070 61.355 ;
END
END wd_in[0]
PIN wd_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 61.705 0.070 61.775 ;
END
END wd_in[1]
PIN wd_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.125 0.070 62.195 ;
END
END wd_in[2]
PIN wd_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.545 0.070 62.615 ;
END
END wd_in[3]
PIN wd_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 62.965 0.070 63.035 ;
END
END wd_in[4]
PIN wd_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 63.385 0.070 63.455 ;
END
END wd_in[5]
PIN wd_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 63.805 0.070 63.875 ;
END
END wd_in[6]
PIN wd_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 64.225 0.070 64.295 ;
END
END wd_in[7]
PIN wd_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 64.645 0.070 64.715 ;
END
END wd_in[8]
PIN wd_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 65.065 0.070 65.135 ;
END
END wd_in[9]
PIN wd_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 65.485 0.070 65.555 ;
END
END wd_in[10]
PIN wd_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 65.905 0.070 65.975 ;
END
END wd_in[11]
PIN wd_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 66.325 0.070 66.395 ;
END
END wd_in[12]
PIN wd_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 66.745 0.070 66.815 ;
END
END wd_in[13]
PIN wd_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 67.165 0.070 67.235 ;
END
END wd_in[14]
PIN wd_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 67.585 0.070 67.655 ;
END
END wd_in[15]
PIN wd_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 68.005 0.070 68.075 ;
END
END wd_in[16]
PIN wd_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 68.425 0.070 68.495 ;
END
END wd_in[17]
PIN wd_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 68.845 0.070 68.915 ;
END
END wd_in[18]
PIN wd_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.265 0.070 69.335 ;
END
END wd_in[19]
PIN wd_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 69.685 0.070 69.755 ;
END
END wd_in[20]
PIN wd_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.105 0.070 70.175 ;
END
END wd_in[21]
PIN wd_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.525 0.070 70.595 ;
END
END wd_in[22]
PIN wd_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 70.945 0.070 71.015 ;
END
END wd_in[23]
PIN wd_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.365 0.070 71.435 ;
END
END wd_in[24]
PIN wd_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 71.785 0.070 71.855 ;
END
END wd_in[25]
PIN wd_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.205 0.070 72.275 ;
END
END wd_in[26]
PIN wd_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 72.625 0.070 72.695 ;
END
END wd_in[27]
PIN wd_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.045 0.070 73.115 ;
END
END wd_in[28]
PIN wd_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.465 0.070 73.535 ;
END
END wd_in[29]
PIN wd_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 73.885 0.070 73.955 ;
END
END wd_in[30]
PIN wd_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.305 0.070 74.375 ;
END
END wd_in[31]
PIN wd_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 74.725 0.070 74.795 ;
END
END wd_in[32]
PIN wd_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.145 0.070 75.215 ;
END
END wd_in[33]
PIN wd_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.565 0.070 75.635 ;
END
END wd_in[34]
PIN wd_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 75.985 0.070 76.055 ;
END
END wd_in[35]
PIN wd_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.405 0.070 76.475 ;
END
END wd_in[36]
PIN wd_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 76.825 0.070 76.895 ;
END
END wd_in[37]
PIN wd_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.245 0.070 77.315 ;
END
END wd_in[38]
PIN wd_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 77.665 0.070 77.735 ;
END
END wd_in[39]
PIN wd_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.085 0.070 78.155 ;
END
END wd_in[40]
PIN wd_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.505 0.070 78.575 ;
END
END wd_in[41]
PIN wd_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 78.925 0.070 78.995 ;
END
END wd_in[42]
PIN wd_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.345 0.070 79.415 ;
END
END wd_in[43]
PIN wd_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 79.765 0.070 79.835 ;
END
END wd_in[44]
PIN wd_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.185 0.070 80.255 ;
END
END wd_in[45]
PIN wd_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 80.605 0.070 80.675 ;
END
END wd_in[46]
PIN wd_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.025 0.070 81.095 ;
END
END wd_in[47]
PIN wd_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.445 0.070 81.515 ;
END
END wd_in[48]
PIN wd_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 81.865 0.070 81.935 ;
END
END wd_in[49]
PIN wd_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.285 0.070 82.355 ;
END
END wd_in[50]
PIN wd_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 82.705 0.070 82.775 ;
END
END wd_in[51]
PIN wd_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.125 0.070 83.195 ;
END
END wd_in[52]
PIN wd_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.545 0.070 83.615 ;
END
END wd_in[53]
PIN wd_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 83.965 0.070 84.035 ;
END
END wd_in[54]
PIN wd_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.385 0.070 84.455 ;
END
END wd_in[55]
PIN wd_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 84.805 0.070 84.875 ;
END
END wd_in[56]
PIN wd_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.225 0.070 85.295 ;
END
END wd_in[57]
PIN wd_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 85.645 0.070 85.715 ;
END
END wd_in[58]
PIN wd_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.065 0.070 86.135 ;
END
END wd_in[59]
PIN wd_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.485 0.070 86.555 ;
END
END wd_in[60]
PIN wd_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 86.905 0.070 86.975 ;
END
END wd_in[61]
PIN addr_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 90.895 0.070 90.965 ;
END
END addr_in[0]
PIN addr_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.315 0.070 91.385 ;
END
END addr_in[1]
PIN addr_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 91.735 0.070 91.805 ;
END
END addr_in[2]
PIN addr_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.155 0.070 92.225 ;
END
END addr_in[3]
PIN addr_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.575 0.070 92.645 ;
END
END addr_in[4]
PIN addr_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 92.995 0.070 93.065 ;
END
END addr_in[5]
PIN we_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 96.985 0.070 97.055 ;
END
END we_in
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 97.405 0.070 97.475 ;
END
END ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER metal3 ;
RECT 0.000 97.825 0.070 97.895 ;
END
END clk
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER metal4 ;
RECT 1.960 2.100 2.240 100.100 ;
RECT 5.320 2.100 5.600 100.100 ;
RECT 8.680 2.100 8.960 100.100 ;
RECT 12.040 2.100 12.320 100.100 ;
RECT 15.400 2.100 15.680 100.100 ;
RECT 18.760 2.100 19.040 100.100 ;
RECT 22.120 2.100 22.400 100.100 ;
RECT 25.480 2.100 25.760 100.100 ;
RECT 28.840 2.100 29.120 100.100 ;
RECT 32.200 2.100 32.480 100.100 ;
RECT 35.560 2.100 35.840 100.100 ;
RECT 38.920 2.100 39.200 100.100 ;
RECT 42.280 2.100 42.560 100.100 ;
RECT 45.640 2.100 45.920 100.100 ;
RECT 49.000 2.100 49.280 100.100 ;
RECT 52.360 2.100 52.640 100.100 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER metal4 ;
RECT 3.640 2.100 3.920 100.100 ;
RECT 7.000 2.100 7.280 100.100 ;
RECT 10.360 2.100 10.640 100.100 ;
RECT 13.720 2.100 14.000 100.100 ;
RECT 17.080 2.100 17.360 100.100 ;
RECT 20.440 2.100 20.720 100.100 ;
RECT 23.800 2.100 24.080 100.100 ;
RECT 27.160 2.100 27.440 100.100 ;
RECT 30.520 2.100 30.800 100.100 ;
RECT 33.880 2.100 34.160 100.100 ;
RECT 37.240 2.100 37.520 100.100 ;
RECT 40.600 2.100 40.880 100.100 ;
RECT 43.960 2.100 44.240 100.100 ;
RECT 47.320 2.100 47.600 100.100 ;
RECT 50.680 2.100 50.960 100.100 ;
END
END VDD
OBS
LAYER metal1 ;
RECT 0 0 56.050 102.200 ;
LAYER metal2 ;
RECT 0 0 56.050 102.200 ;
LAYER metal3 ;
RECT 0.070 0 56.050 102.200 ;
RECT 0 0.000 0.070 2.065 ;
RECT 0 2.135 0.070 2.485 ;
RECT 0 2.555 0.070 2.905 ;
RECT 0 2.975 0.070 3.325 ;
RECT 0 3.395 0.070 3.745 ;
RECT 0 3.815 0.070 4.165 ;
RECT 0 4.235 0.070 4.585 ;
RECT 0 4.655 0.070 5.005 ;
RECT 0 5.075 0.070 5.425 ;
RECT 0 5.495 0.070 5.845 ;
RECT 0 5.915 0.070 6.265 ;
RECT 0 6.335 0.070 6.685 ;
RECT 0 6.755 0.070 7.105 ;
RECT 0 7.175 0.070 7.525 ;
RECT 0 7.595 0.070 7.945 ;
RECT 0 8.015 0.070 8.365 ;
RECT 0 8.435 0.070 8.785 ;
RECT 0 8.855 0.070 9.205 ;
RECT 0 9.275 0.070 9.625 ;
RECT 0 9.695 0.070 10.045 ;
RECT 0 10.115 0.070 10.465 ;
RECT 0 10.535 0.070 10.885 ;
RECT 0 10.955 0.070 11.305 ;
RECT 0 11.375 0.070 11.725 ;
RECT 0 11.795 0.070 12.145 ;
RECT 0 12.215 0.070 12.565 ;
RECT 0 12.635 0.070 12.985 ;
RECT 0 13.055 0.070 13.405 ;
RECT 0 13.475 0.070 13.825 ;
RECT 0 13.895 0.070 14.245 ;
RECT 0 14.315 0.070 14.665 ;
RECT 0 14.735 0.070 15.085 ;
RECT 0 15.155 0.070 15.505 ;
RECT 0 15.575 0.070 15.925 ;
RECT 0 15.995 0.070 16.345 ;
RECT 0 16.415 0.070 16.765 ;
RECT 0 16.835 0.070 17.185 ;
RECT 0 17.255 0.070 17.605 ;
RECT 0 17.675 0.070 18.025 ;
RECT 0 18.095 0.070 18.445 ;
RECT 0 18.515 0.070 18.865 ;
RECT 0 18.935 0.070 19.285 ;
RECT 0 19.355 0.070 19.705 ;
RECT 0 19.775 0.070 20.125 ;
RECT 0 20.195 0.070 20.545 ;
RECT 0 20.615 0.070 20.965 ;
RECT 0 21.035 0.070 21.385 ;
RECT 0 21.455 0.070 21.805 ;
RECT 0 21.875 0.070 22.225 ;
RECT 0 22.295 0.070 22.645 ;
RECT 0 22.715 0.070 23.065 ;
RECT 0 23.135 0.070 23.485 ;
RECT 0 23.555 0.070 23.905 ;
RECT 0 23.975 0.070 24.325 ;
RECT 0 24.395 0.070 24.745 ;
RECT 0 24.815 0.070 25.165 ;
RECT 0 25.235 0.070 25.585 ;
RECT 0 25.655 0.070 26.005 ;
RECT 0 26.075 0.070 26.425 ;
RECT 0 26.495 0.070 26.845 ;
RECT 0 26.915 0.070 27.265 ;
RECT 0 27.335 0.070 27.685 ;
RECT 0 27.755 0.070 31.675 ;
RECT 0 31.745 0.070 32.095 ;
RECT 0 32.165 0.070 32.515 ;
RECT 0 32.585 0.070 32.935 ;
RECT 0 33.005 0.070 33.355 ;
RECT 0 33.425 0.070 33.775 ;
RECT 0 33.845 0.070 34.195 ;
RECT 0 34.265 0.070 34.615 ;
RECT 0 34.685 0.070 35.035 ;
RECT 0 35.105 0.070 35.455 ;
RECT 0 35.525 0.070 35.875 ;
RECT 0 35.945 0.070 36.295 ;
RECT 0 36.365 0.070 36.715 ;
RECT 0 36.785 0.070 37.135 ;
RECT 0 37.205 0.070 37.555 ;
RECT 0 37.625 0.070 37.975 ;
RECT 0 38.045 0.070 38.395 ;
RECT 0 38.465 0.070 38.815 ;
RECT 0 38.885 0.070 39.235 ;
RECT 0 39.305 0.070 39.655 ;
RECT 0 39.725 0.070 40.075 ;
RECT 0 40.145 0.070 40.495 ;
RECT 0 40.565 0.070 40.915 ;
RECT 0 40.985 0.070 41.335 ;
RECT 0 41.405 0.070 41.755 ;
RECT 0 41.825 0.070 42.175 ;
RECT 0 42.245 0.070 42.595 ;
RECT 0 42.665 0.070 43.015 ;
RECT 0 43.085 0.070 43.435 ;
RECT 0 43.505 0.070 43.855 ;
RECT 0 43.925 0.070 44.275 ;
RECT 0 44.345 0.070 44.695 ;
RECT 0 44.765 0.070 45.115 ;
RECT 0 45.185 0.070 45.535 ;
RECT 0 45.605 0.070 45.955 ;
RECT 0 46.025 0.070 46.375 ;
RECT 0 46.445 0.070 46.795 ;
RECT 0 46.865 0.070 47.215 ;
RECT 0 47.285 0.070 47.635 ;
RECT 0 47.705 0.070 48.055 ;
RECT 0 48.125 0.070 48.475 ;
RECT 0 48.545 0.070 48.895 ;
RECT 0 48.965 0.070 49.315 ;
RECT 0 49.385 0.070 49.735 ;
RECT 0 49.805 0.070 50.155 ;
RECT 0 50.225 0.070 50.575 ;
RECT 0 50.645 0.070 50.995 ;
RECT 0 51.065 0.070 51.415 ;
RECT 0 51.485 0.070 51.835 ;
RECT 0 51.905 0.070 52.255 ;
RECT 0 52.325 0.070 52.675 ;
RECT 0 52.745 0.070 53.095 ;
RECT 0 53.165 0.070 53.515 ;
RECT 0 53.585 0.070 53.935 ;
RECT 0 54.005 0.070 54.355 ;
RECT 0 54.425 0.070 54.775 ;
RECT 0 54.845 0.070 55.195 ;
RECT 0 55.265 0.070 55.615 ;
RECT 0 55.685 0.070 56.035 ;
RECT 0 56.105 0.070 56.455 ;
RECT 0 56.525 0.070 56.875 ;
RECT 0 56.945 0.070 57.295 ;
RECT 0 57.365 0.070 61.285 ;
RECT 0 61.355 0.070 61.705 ;
RECT 0 61.775 0.070 62.125 ;
RECT 0 62.195 0.070 62.545 ;
RECT 0 62.615 0.070 62.965 ;
RECT 0 63.035 0.070 63.385 ;
RECT 0 63.455 0.070 63.805 ;
RECT 0 63.875 0.070 64.225 ;
RECT 0 64.295 0.070 64.645 ;
RECT 0 64.715 0.070 65.065 ;
RECT 0 65.135 0.070 65.485 ;
RECT 0 65.555 0.070 65.905 ;
RECT 0 65.975 0.070 66.325 ;
RECT 0 66.395 0.070 66.745 ;
RECT 0 66.815 0.070 67.165 ;
RECT 0 67.235 0.070 67.585 ;
RECT 0 67.655 0.070 68.005 ;
RECT 0 68.075 0.070 68.425 ;
RECT 0 68.495 0.070 68.845 ;
RECT 0 68.915 0.070 69.265 ;
RECT 0 69.335 0.070 69.685 ;
RECT 0 69.755 0.070 70.105 ;
RECT 0 70.175 0.070 70.525 ;
RECT 0 70.595 0.070 70.945 ;
RECT 0 71.015 0.070 71.365 ;
RECT 0 71.435 0.070 71.785 ;
RECT 0 71.855 0.070 72.205 ;
RECT 0 72.275 0.070 72.625 ;
RECT 0 72.695 0.070 73.045 ;
RECT 0 73.115 0.070 73.465 ;
RECT 0 73.535 0.070 73.885 ;
RECT 0 73.955 0.070 74.305 ;
RECT 0 74.375 0.070 74.725 ;
RECT 0 74.795 0.070 75.145 ;
RECT 0 75.215 0.070 75.565 ;
RECT 0 75.635 0.070 75.985 ;
RECT 0 76.055 0.070 76.405 ;
RECT 0 76.475 0.070 76.825 ;
RECT 0 76.895 0.070 77.245 ;
RECT 0 77.315 0.070 77.665 ;
RECT 0 77.735 0.070 78.085 ;
RECT 0 78.155 0.070 78.505 ;
RECT 0 78.575 0.070 78.925 ;
RECT 0 78.995 0.070 79.345 ;
RECT 0 79.415 0.070 79.765 ;
RECT 0 79.835 0.070 80.185 ;
RECT 0 80.255 0.070 80.605 ;
RECT 0 80.675 0.070 81.025 ;
RECT 0 81.095 0.070 81.445 ;
RECT 0 81.515 0.070 81.865 ;
RECT 0 81.935 0.070 82.285 ;
RECT 0 82.355 0.070 82.705 ;
RECT 0 82.775 0.070 83.125 ;
RECT 0 83.195 0.070 83.545 ;
RECT 0 83.615 0.070 83.965 ;
RECT 0 84.035 0.070 84.385 ;
RECT 0 84.455 0.070 84.805 ;
RECT 0 84.875 0.070 85.225 ;
RECT 0 85.295 0.070 85.645 ;
RECT 0 85.715 0.070 86.065 ;
RECT 0 86.135 0.070 86.485 ;
RECT 0 86.555 0.070 86.905 ;
RECT 0 86.975 0.070 90.895 ;
RECT 0 90.965 0.070 91.315 ;
RECT 0 91.385 0.070 91.735 ;
RECT 0 91.805 0.070 92.155 ;
RECT 0 92.225 0.070 92.575 ;
RECT 0 92.645 0.070 92.995 ;
RECT 0 93.065 0.070 96.985 ;
RECT 0 97.055 0.070 97.405 ;
RECT 0 97.475 0.070 97.825 ;
RECT 0 97.895 0.070 102.200 ;
LAYER metal4 ;
RECT 0 0 56.050 2.100 ;
RECT 0 100.100 56.050 102.200 ;
RECT 0.000 2.100 1.960 100.100 ;
RECT 2.240 2.100 3.640 100.100 ;
RECT 3.920 2.100 5.320 100.100 ;
RECT 5.600 2.100 7.000 100.100 ;
RECT 7.280 2.100 8.680 100.100 ;
RECT 8.960 2.100 10.360 100.100 ;
RECT 10.640 2.100 12.040 100.100 ;
RECT 12.320 2.100 13.720 100.100 ;
RECT 14.000 2.100 15.400 100.100 ;
RECT 15.680 2.100 17.080 100.100 ;
RECT 17.360 2.100 18.760 100.100 ;
RECT 19.040 2.100 20.440 100.100 ;
RECT 20.720 2.100 22.120 100.100 ;
RECT 22.400 2.100 23.800 100.100 ;
RECT 24.080 2.100 25.480 100.100 ;
RECT 25.760 2.100 27.160 100.100 ;
RECT 27.440 2.100 28.840 100.100 ;
RECT 29.120 2.100 30.520 100.100 ;
RECT 30.800 2.100 32.200 100.100 ;
RECT 32.480 2.100 33.880 100.100 ;
RECT 34.160 2.100 35.560 100.100 ;
RECT 35.840 2.100 37.240 100.100 ;
RECT 37.520 2.100 38.920 100.100 ;
RECT 39.200 2.100 40.600 100.100 ;
RECT 40.880 2.100 42.280 100.100 ;
RECT 42.560 2.100 43.960 100.100 ;
RECT 44.240 2.100 45.640 100.100 ;
RECT 45.920 2.100 47.320 100.100 ;
RECT 47.600 2.100 49.000 100.100 ;
RECT 49.280 2.100 50.680 100.100 ;
RECT 50.960 2.100 52.360 100.100 ;
RECT 52.640 2.100 56.050 100.100 ;
LAYER OVERLAP ;
RECT 0 0 56.050 102.200 ;
END
END fakeram45_64x62
END LIBRARY
Enablements/NanGate45/lib/fakeram45_128x116.lib 0 → 100644
library(fakeram45_128x116) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-09-13 21:51:08Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1uW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_128x116_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_128x116_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_128x116_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_128x116_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_128x116_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_128x116_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 116;
bit_from : 115;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_128x116_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 7;
bit_from : 6;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_128x116) {
area : 14233.128;
interface_timing : true;
memory() {
type : ram;
address_width : 7;
word_width : 116;
}
pin(clk) {
direction : input;
capacitance : 0.025;
clock : true;
min_period : 0.248 ;
internal_power(){
rise_power(fakeram45_128x116_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("6.316, 6.316")
}
fall_power(fakeram45_128x116_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("6.316, 6.316")
}
}
}
bus(rd_out) {
bus_type : fakeram45_128x116_DATA;
direction : output;
max_capacitance : 0.500;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(fakeram45_128x116_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.285, 0.285", \
"0.285, 0.285" \
)
}
cell_fall(fakeram45_128x116_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.285, 0.285", \
"0.285, 0.285" \
)
}
rise_transition(fakeram45_128x116_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
fall_transition(fakeram45_128x116_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
fall_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
}
}
pin(ce_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
fall_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
}
}
bus(addr_in) {
bus_type : fakeram45_128x116_ADDRESS;
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
fall_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
}
}
bus(wd_in) {
bus_type : fakeram45_128x116_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
fall_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
fall_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_128x116_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_128x116_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
fall_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
fall_power(fakeram45_128x116_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.063, 0.063")
}
}
}
cell_leakage_power : 650.179;
}
}
Enablements/NanGate45/lib/fakeram45_256x48.lib 0 → 100644
library(fakeram45_256x48) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-09-13 21:51:06Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1uW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_256x48_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_256x48_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_256x48_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_256x48_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_256x48_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_256x48_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 48;
bit_from : 47;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_256x48_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 8;
bit_from : 7;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_256x48) {
area : 13267.016;
interface_timing : true;
memory() {
type : ram;
address_width : 8;
word_width : 48;
}
pin(clk) {
direction : input;
capacitance : 0.025;
clock : true;
min_period : 0.230 ;
internal_power(){
rise_power(fakeram45_256x48_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("4.589, 4.589")
}
fall_power(fakeram45_256x48_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("4.589, 4.589")
}
}
}
bus(rd_out) {
bus_type : fakeram45_256x48_DATA;
direction : output;
max_capacitance : 0.500;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(fakeram45_256x48_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.270, 0.270", \
"0.270, 0.270" \
)
}
cell_fall(fakeram45_256x48_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.270, 0.270", \
"0.270, 0.270" \
)
}
rise_transition(fakeram45_256x48_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
fall_transition(fakeram45_256x48_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
fall_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
}
}
pin(ce_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
fall_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
}
}
bus(addr_in) {
bus_type : fakeram45_256x48_ADDRESS;
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
fall_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
}
}
bus(wd_in) {
bus_type : fakeram45_256x48_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
fall_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
fall_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_256x48_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_256x48_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
fall_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
fall_power(fakeram45_256x48_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.046, 0.046")
}
}
}
cell_leakage_power : 690.971;
}
}
Enablements/NanGate45/lib/fakeram45_32x32.lib 0 → 100644
library(fakeram45_32x32) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-09-13 21:51:09Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1uW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_32x32_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_32x32_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_32x32_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_32x32_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_32x32_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_32x32_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 32;
bit_from : 31;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_32x32_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 5;
bit_from : 4;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_32x32) {
area : 1851.360;
interface_timing : true;
memory() {
type : ram;
address_width : 5;
word_width : 32;
}
pin(clk) {
direction : input;
capacitance : 0.025;
clock : true;
min_period : 0.157 ;
internal_power(){
rise_power(fakeram45_32x32_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("1.345, 1.345")
}
fall_power(fakeram45_32x32_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("1.345, 1.345")
}
}
}
bus(rd_out) {
bus_type : fakeram45_32x32_DATA;
direction : output;
max_capacitance : 0.500;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(fakeram45_32x32_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.218, 0.218", \
"0.218, 0.218" \
)
}
cell_fall(fakeram45_32x32_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.218, 0.218", \
"0.218, 0.218" \
)
}
rise_transition(fakeram45_32x32_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
fall_transition(fakeram45_32x32_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
}
pin(ce_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
}
bus(addr_in) {
bus_type : fakeram45_32x32_ADDRESS;
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
}
bus(wd_in) {
bus_type : fakeram45_32x32_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_32x32_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_32x32_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(fakeram45_32x32_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
}
cell_leakage_power : 128.900;
}
}
Enablements/NanGate45/lib/fakeram45_512x64.lib 0 → 100644
library(fakeram45_512x64) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-09-13 21:51:05Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1uW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_512x64_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_512x64_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_512x64_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_512x64_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_512x64_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_512x64_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 64;
bit_from : 63;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_512x64_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 9;
bit_from : 8;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_512x64) {
area : 26182.380;
interface_timing : true;
memory() {
type : ram;
address_width : 9;
word_width : 64;
}
pin(clk) {
direction : input;
capacitance : 0.025;
clock : true;
min_period : 0.299 ;
internal_power(){
rise_power(fakeram45_512x64_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("7.024, 7.024")
}
fall_power(fakeram45_512x64_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("7.024, 7.024")
}
}
}
bus(rd_out) {
bus_type : fakeram45_512x64_DATA;
direction : output;
max_capacitance : 0.500;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(fakeram45_512x64_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.321, 0.321", \
"0.321, 0.321" \
)
}
cell_fall(fakeram45_512x64_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.321, 0.321", \
"0.321, 0.321" \
)
}
rise_transition(fakeram45_512x64_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
fall_transition(fakeram45_512x64_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
fall_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
}
}
pin(ce_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
fall_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
}
}
bus(addr_in) {
bus_type : fakeram45_512x64_ADDRESS;
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
fall_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
}
}
bus(wd_in) {
bus_type : fakeram45_512x64_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
fall_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
fall_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_512x64_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_512x64_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
fall_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
fall_power(fakeram45_512x64_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.070, 0.070")
}
}
}
cell_leakage_power : 1327.240;
}
}
Enablements/NanGate45/lib/fakeram45_64x124.lib 0 → 100644
library(fakeram45_64x124) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-09-13 21:51:08Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1uW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_64x124_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_64x124_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_64x124_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_64x124_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_64x124_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_64x124_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 124;
bit_from : 123;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_64x124_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 6;
bit_from : 5;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_64x124) {
area : 9812.208;
interface_timing : true;
memory() {
type : ram;
address_width : 6;
word_width : 124;
}
pin(clk) {
direction : input;
capacitance : 0.025;
clock : true;
min_period : 0.207 ;
internal_power(){
rise_power(fakeram45_64x124_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("5.492, 5.492")
}
fall_power(fakeram45_64x124_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("5.492, 5.492")
}
}
}
bus(rd_out) {
bus_type : fakeram45_64x124_DATA;
direction : output;
max_capacitance : 0.500;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(fakeram45_64x124_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.238, 0.238", \
"0.238, 0.238" \
)
}
cell_fall(fakeram45_64x124_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.238, 0.238", \
"0.238, 0.238" \
)
}
rise_transition(fakeram45_64x124_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
fall_transition(fakeram45_64x124_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
fall_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
}
}
pin(ce_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
fall_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
}
}
bus(addr_in) {
bus_type : fakeram45_64x124_ADDRESS;
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
fall_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
}
}
bus(wd_in) {
bus_type : fakeram45_64x124_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
fall_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
fall_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_64x124_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x124_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
fall_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
fall_power(fakeram45_64x124_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.055, 0.055")
}
}
}
cell_leakage_power : 415.087;
}
}
Enablements/NanGate45/lib/fakeram45_64x62.lib 0 → 100644
library(fakeram45_64x62) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-09-13 21:51:07Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1uW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_64x62_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_64x62_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_64x62_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_64x62_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_64x62_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_64x62_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 62;
bit_from : 61;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_64x62_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 6;
bit_from : 5;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_64x62) {
area : 5728.310;
interface_timing : true;
memory() {
type : ram;
address_width : 6;
word_width : 62;
}
pin(clk) {
direction : input;
capacitance : 0.025;
clock : true;
min_period : 0.193 ;
internal_power(){
rise_power(fakeram45_64x62_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("3.326, 3.326")
}
fall_power(fakeram45_64x62_energy_template_clkslew) {
index_1 ("0.009, 0.227");
values ("3.326, 3.326")
}
}
}
bus(rd_out) {
bus_type : fakeram45_64x62_DATA;
direction : output;
max_capacitance : 0.500;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(fakeram45_64x62_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.237, 0.237", \
"0.237, 0.237" \
)
}
cell_fall(fakeram45_64x62_mem_out_delay_template) {
index_1 ("0.009, 0.227");
index_2 ("0.005, 0.500");
values ( \
"0.237, 0.237", \
"0.237, 0.237" \
)
}
rise_transition(fakeram45_64x62_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
fall_transition(fakeram45_64x62_mem_out_slew_template) {
index_1 ("0.005, 0.500");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
fall_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
}
}
pin(ce_in){
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
fall_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
}
}
bus(addr_in) {
bus_type : fakeram45_64x62_ADDRESS;
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
rise_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
fall_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
}
}
bus(wd_in) {
bus_type : fakeram45_64x62_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
fall_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
fall_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_64x62_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(fakeram45_64x62_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
fall_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
}
internal_power(){
when : "(we_in)";
rise_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
fall_power(fakeram45_64x62_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.033, 0.033")
}
}
}
cell_leakage_power : 280.070;
}
}
Enablements/NanGate45/qrc/typical.captable 0 → 100644
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Flows/NanGate45/ariane133/def/Util_51/ariane133_fp.def 0 → 100644
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Flows/NanGate45/ariane133/def/Util_51/ariane133_fp_placed_macros.def 0 → 100644
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Flows/NanGate45/ariane133/def/Util_51/manual_floorplan.def 0 → 100644
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Flows/NanGate45/ariane133/def/ariane133_fp.def
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Flows/NanGate45/ariane133/def/ariane133_fp_placed_macros.def
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Flows/NanGate45/ariane133/def/manual_floorplan.def
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Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
...@@ -2,15 +2,15 @@ ...@@ -2,15 +2,15 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators. # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl source lib_setup.tcl
source design_setup.tcl source design_setup.tcl
set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
source mmmc_setup.tcl source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16 setMultiCpuUsage -localCpu 16
set util 0.3 set util 0.3
set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/ set rptDir summaryReport/
set encDir enc/ set encDir enc/
...@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW} ...@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON} set_interactive_constraint_modes {CON}
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
clearGlobalNets clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override globalNetConnect VDD -type pgpin -pin VDD -inst * -override
...@@ -126,16 +128,21 @@ setNanoRouteMode -routeExpAdvancedTechnology true ...@@ -126,16 +128,21 @@ setNanoRouteMode -routeExpAdvancedTechnology true
setNanoRouteMode -grouteExpWithTimingDriven false setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
#route_opt_design
optDesign -postRoute
set rpt_post_route [extract_report postRouteOpt]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
### Run DRC and LVS ### ### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0 verify_drc -limit 0
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc saveDesign ${encDir}/${DESIGN}.enc
......
Flows/util/extract_report.tcl
...@@ -53,12 +53,16 @@ proc extract_wire_length {} { ...@@ -53,12 +53,16 @@ proc extract_wire_length {} {
} }
proc extract_report {stage} { proc extract_report {stage} {
setAnalysisMode -reset
setAnalysisMode -analysisType onChipVariation -cppr both
if { $stage == "preCTS" } { if { $stage == "preCTS" } {
timeDesign -preCTS -prefix ${stage} timeDesign -preCTS -prefix ${stage}
} elseif { $stage == "postCTS" } { } elseif { $stage == "postCTS" } {
timeDesign -postCTS -prefix ${stage} timeDesign -postCTS -prefix ${stage}
} elseif { $stage == "postRoute" } { } elseif { $stage == "postRoute" } {
setAnalysisMode -analysisType onChipVariatio -cppr both timeDesign -postRoute -prefix ${stage}
} elseif { $stage == "postRouetOpt" } {
timeDesign -postRoute -prefix ${stage} timeDesign -postRoute -prefix ${stage}
} }
set rpt1 [extract_from_timing_rpt timingReports/${stage}.summary.gz] set rpt1 [extract_from_timing_rpt timingReports/${stage}.summary.gz]
......
Flows/util/write_required_def.tcl
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
deselectAll deselectAll
set top_module [dbget top.name] set top_module [dbget top.name]
if {[dbget top.terms.pStatus -v -e fixed] == "" } { if {[dbget top.terms.pStatus -v -e fixed] != "" } {
source ../../../../util/place_pin.tcl source ../../../../util/place_pin.tcl
} }
......
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