Updated flow-charts and README

Signed-off-by: sakundu <sakundu@ucsd.edu>

README.md

@@ -11,9 +11,9 @@
   - [Related Links](#related-links)
 
 ## **Testcases**  
-The list of available testcases
+The list of available testcases is as follows.
 - Ariane (RTL)
-  - [RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
+  - [RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist available in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
   - [RTL files for Ariane design with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connections of the 136 macro version.
 - MemPool (RTL)
   - [RTL files for Mempool tile design](./Testcases/mempool/)
@@ -26,10 +26,10 @@ In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the a
 
 All the testcases are available in the [Testcases](./Testcases/) directory. Details of the sub-directories are  
   - *rtl*: directory contains all the required rtl files to synthesize the design.
-  - *sv2v*: If the main repository contains multiple Verilog files or SystemVerilog files, then we convert it to a single synthesizable Verilog RTL. This is availabe in the *sv2v* sub-drectory.
+  - *sv2v*: If the main repository contains multiple Verilog files or SystemVerilog files, then we convert it to a single synthesizable Verilog RTL. This is available in the *sv2v* sub-drectory.
 
 ## **Enablements**
-The list of available enablements
+The list of available enablements is as follows.
 - [NanGate45](./Enablements/NanGate45/)
 - [ASAP7](./Enablements/ASAP7/)
 - [SKY130HD FakeStack](./Enablements/SKY130HD/)
@@ -39,16 +39,15 @@ Open-source enablements NanGate45, ASAP7 and SKY130HD are utilized in our SP&R f
  - *lef* directory contains all the required lef files.
  - *qrc* directory contains all the required qrc tech files.
   
-We also provide the steps to generate the fakeram model for each of the enablements based on the required memory configurations.
+We also provide the steps to generate the fakeram models for each of the enablements based on the required memory configurations.
 
 
 ## **Flows**
 We provide multiple flows for each of the testcases and enablements. They are: (1) a logical synthesis-based SP&R flow using Cadence Genus and Innovus ([Flow-1](./Flows/figures/flow-1.PNG)), (2) a physical synthesis-based SP&R flow using Cadence Genus iSpatial and Innovus ([Flow-2](./Flows/figures/flow-2.PNG)), (3) a logical synthesis-based SP&R flow using Yosys and OpenROAD ([Flow-3](./Flows/figures/flow-3.PNG)), and (4) creation of input data for Physical synthesis-based CircuitTraining using Genus iSpatial ([Flow-4](./Flows/figures/flow-4.PNG)).
 
-The details of each flow are shown below:  
+The details of each flow are are given in the following.
 - **Flow-1:**  
   <img src="./Flows/figures/flow-1.PNG" alt="Flow-1" width="800"/>
-
 - **Flow-2:**  
   <img src="./Flows/figures/flow-2.PNG" alt="Flow-2" width="800"/>    
 - **Flow-3:**  
@@ -57,7 +56,7 @@ The details of each flow are shown below:
   <img src="./Flows/figures/flow-4.PNG" alt="Flow-4" width="800"/>  
 
 
-In the table below, we provide the details of each testcase on each of the enablements for the different flows.
+In the following table, we provide the status details of each testcase on each of the enablements for the different flows.
 <table class="tg">
 <thead>
   <tr>
@@ -146,7 +145,7 @@ In the table below, we provide the details of each testcase on each of the enabl
 </table>
 
 
-The directory structure is as follows *./FLows/\<enablement\>/\<testcase\>/<constraint\|def\|netlist\|scripts\|run>/*. Details of the sub-directories for each testcase on each enablement:
+The directory structure is : *./Flows/\<enablement\>/\<testcase\>/<constraint\|def\|netlist\|scripts\|run>/*. Details of the sub-directories for each testcase on each enablement are as follows.
 - *constraint* directory contains the *.sdc* file.
 - *def* directory contains the def file with pin placement and die area information.
 - *scripts* directory contains required scripts to run SP&R using the Cadence and OpenROAD tools.